Index: trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 46050)
+++ trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 46076)
@@ -183,9 +183,5 @@
     uint32_t        uExitIntrErrorCode;
     /** The VM-exit exit qualification. */
-    RTGCUINTPTR     uExitQualification;
-#if GC_ARCH_BITS == 32
-    /** Alignment. */
-    uint32_t        u32Alignment1;
-#endif
+    uint64_t        uExitQualification;
 
     /** The VM-exit interruption-information field. */
@@ -3910,9 +3906,8 @@
 
                 /* Guest bits. */
-                RTGCUINTREG uGCReg;
-                rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &uGCReg);        AssertRC(rc);
-                Log(("Old Guest Rip %#RGv New %#RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)uGCReg));
-                rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &uGCReg);        AssertRC(rc);
-                Log(("Old Guest Rsp %#RGv New %#RGv\n", (RTGCPTR)pCtx->rsp, (RTGCPTR)uGCReg));
+                rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);        AssertRC(rc);
+                Log(("Old Guest Rip %#RX64 New %#RX64\n", pCtx->rip, u64Val));
+                rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);        AssertRC(rc);
+                Log(("Old Guest Rsp %#RX64 New %#RX64\n", pCtx->rsp, u64Val));
                 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val);       AssertRC(rc);
                 Log(("Old Guest Rflags %#RX32 New %#RX32\n", pCtx->eflags.u32, u32Val));
@@ -4666,5 +4661,5 @@
                 && uExitVector == X86_XCPT_PF)
             {
-                Log(("IDT: Contributory #PF uCR2=%#RGv\n", pMixedCtx->cr2));
+                Log(("IDT: Contributory #PF uCR2=%#RX64\n", pMixedCtx->cr2));
             }
 #endif
@@ -4673,5 +4668,5 @@
             {
                 pVmxTransient->fVectoringPF = true;
-                Log(("IDT: Vectoring #PF uCR2=%#RGv\n", pMixedCtx->cr2));
+                Log(("IDT: Vectoring #PF uCR2=%#RX64\n", pMixedCtx->cr2));
             }
             else if (   (pVCpu->hm.s.vmx.u32XcptBitmap & HMVMX_CONTRIBUTORY_XCPT_MASK)
@@ -4820,5 +4815,5 @@
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RIP))
     {
-        RTGCUINTREG uVal = 0;
+        uint64_t uVal = 0;
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &uVal);
         AssertRCReturn(rc, rc);
@@ -4847,5 +4842,5 @@
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RSP))
     {
-        RTGCUINTREG uVal = 0;
+        uint64_t uVal = 0;
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &uVal);
         AssertRCReturn(rc, rc);
@@ -4982,5 +4977,5 @@
     }
 
-    RTGCUINTREG uGCVal = 0;
+    uint64_t uGCVal = 0;
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR))
     {
@@ -5016,5 +5011,5 @@
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_FS_BASE_MSR))
     {
-        RTGCUINTREG uVal = 0;
+        uint64_t uVal = 0;
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_FS_BASE, &uVal);   AssertRCReturn(rc, rc);
         pMixedCtx->fs.u64Base = uVal;
@@ -5042,5 +5037,5 @@
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_GS_BASE_MSR))
     {
-        RTGCUINTREG uVal = 0;
+        uint64_t uVal = 0;
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GS_BASE, &uVal);   AssertRCReturn(rc, rc);
         pMixedCtx->gs.u64Base = uVal;
@@ -5130,5 +5125,5 @@
                 && CPUMIsGuestPagingEnabledEx(pMixedCtx)))
         {
-            RTGCUINTREG uVal = 0;
+            uint64_t uVal = 0;
             rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &uVal);
             if (pMixedCtx->cr3 != uVal)
@@ -5224,8 +5219,8 @@
     pSelReg->u32Limit = u32Val;
 
-    RTGCUINTREG uGCVal = 0;
-    rc = VMXReadVmcsGstNByIdxVal(idxBase, &uGCVal);
+    uint64_t u64Val = 0;
+    rc = VMXReadVmcsGstNByIdxVal(idxBase, &u64Val);
     AssertRCReturn(rc, rc);
-    pSelReg->u64Base = uGCVal;
+    pSelReg->u64Base = u64Val;
 
     rc = VMXReadVmcs32(idxAccess, &u32Val);
@@ -5325,11 +5320,11 @@
 
     /* Guest GDTR. */
-    RTGCUINTREG uGCVal = 0;
-    uint32_t    u32Val = 0;
+    uint64_t u64Val = 0;
+    uint32_t u32Val = 0;
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_GDTR))
     {
-        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &uGCVal);        AssertRCReturn(rc, rc);
+        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);        AssertRCReturn(rc, rc);
         rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);       AssertRCReturn(rc, rc);
-        pMixedCtx->gdtr.pGdt  = uGCVal;
+        pMixedCtx->gdtr.pGdt  = u64Val;
         pMixedCtx->gdtr.cbGdt = u32Val;
         pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_GDTR;
@@ -5339,7 +5334,7 @@
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_IDTR))
     {
-        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &uGCVal);        AssertRCReturn(rc, rc);
+        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);        AssertRCReturn(rc, rc);
         rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);       AssertRCReturn(rc, rc);
-        pMixedCtx->idtr.pIdt  = uGCVal;
+        pMixedCtx->idtr.pIdt  = u64Val;
         pMixedCtx->idtr.cbIdt = u32Val;
         pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_IDTR;
@@ -6348,5 +6343,5 @@
         pMixedCtx->cr2 = GCPtrFaultAddress;
     }
-    Log(("Injecting u32IntrInfo=%#x u32ErrCode=%#x cbInstr=%#x uCR2=%#RGv\n", u32IntrInfo, u32ErrCode, cbInstr, pMixedCtx->cr2));
+    Log(("Injecting u32IntrInfo=%#x u32ErrCode=%#x cbInstr=%#x uCR2=%#RX64\n", u32IntrInfo, u32ErrCode, cbInstr, pMixedCtx->cr2));
 
     AssertRCReturn(rc, rc);
@@ -7372,5 +7367,5 @@
     else
     {
-        AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitInvlpg: EMInterpretInvlpg %#RGv failed with %Rrc\n",
+        AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitInvlpg: EMInterpretInvlpg %#RX64 failed with %Rrc\n",
                                               pVmxTransient->uExitQualification, rc));
     }
@@ -7921,5 +7916,5 @@
             {
                 case 0: /* CR0 */
-                    Log(("CRX CR0 write rc=%d CR0=%#RGv\n", rc, pMixedCtx->cr0));
+                    Log(("CRX CR0 write rc=%d CR0=%#RX64\n", rc, pMixedCtx->cr0));
                     pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
                     break;
@@ -7929,9 +7924,9 @@
                 case 3: /* CR3 */
                     Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx));
-                    Log(("CRX CR3 write rc=%d CR3=%#RGv\n", rc, pMixedCtx->cr3));
+                    Log(("CRX CR3 write rc=%d CR3=%#RX64\n", rc, pMixedCtx->cr3));
                     pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR3;
                     break;
                 case 4: /* CR4 */
-                    Log(("CRX CR4 write rc=%d CR4=%#RGv\n", rc, pMixedCtx->cr4));
+                    Log(("CRX CR4 write rc=%d CR4=%#RX64\n", rc, pMixedCtx->cr4));
                     pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR4;
                     break;
@@ -8034,5 +8029,5 @@
     /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
     AssertRCReturn(rc, rc);
-    Log(("CS:RIP=%04x:%#RGv\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
+    Log(("CS:RIP=%04x:%#RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
 
     /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
@@ -8300,5 +8295,5 @@
             GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification);
             PVM pVM = pVCpu->CTX_SUFF(pVM);
-            Log(("ApicAccess uAccessType=%#x GCPhys=%RGp Off=%#x\n", uAccessType, GCPhys,
+            Log(("ApicAccess uAccessType=%#x GCPhys=%#RGv Off=%#x\n", uAccessType, GCPhys,
                  VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification)));
 
@@ -8447,5 +8442,5 @@
     VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pMixedCtx), GCPhys, UINT32_MAX);
     rc = VBOXSTRICTRC_VAL(rc2);
-    Log(("EPT misconfig at %#RGv RIP=%#RGv rc=%d\n", GCPhys, pMixedCtx->rip, rc));
+    Log(("EPT misconfig at %#RGv RIP=%#RX64 rc=%d\n", GCPhys, pMixedCtx->rip, rc));
     if (   rc == VINF_SUCCESS
         || rc == VERR_PAGE_TABLE_NOT_PRESENT
@@ -8490,5 +8485,5 @@
 
     /* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
-    AssertMsg(((pVmxTransient->uExitQualification >> 7) & 3) != 2, ("%#RGv", pVmxTransient->uExitQualification));
+    AssertMsg(((pVmxTransient->uExitQualification >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQualification));
 
     RTGCUINT uErrorCode = 0;
@@ -8502,5 +8497,5 @@
     TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
 
-    Log(("EPT violation %#x at %#RGv ErrorCode %#x CS:EIP=%04x:%#RX64\n", (uint32_t)pVmxTransient->uExitQualification, GCPhys,
+    Log(("EPT violation %#x at %#RX64 ErrorCode %#x CS:EIP=%04x:%#RX64\n", pVmxTransient->uExitQualification, GCPhys,
          uErrorCode, pMixedCtx->cs.Sel, pMixedCtx->rip));
 
@@ -8693,5 +8688,5 @@
         rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
         AssertRCReturn(rc, rc);
-        Log(("#GP Gst: RIP %#RX64 ErrorCode=%#x CR0=%#RGv CPL=%u\n", pMixedCtx->rip, pVmxTransient->uExitIntrErrorCode,
+        Log(("#GP Gst: RIP %#RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u\n", pMixedCtx->rip, pVmxTransient->uExitIntrErrorCode,
              pMixedCtx->cr0, CPUMGetGuestCPL(pVCpu)));
         hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
@@ -8778,5 +8773,5 @@
                     break;
                 }
-                Log(("POPF %x -> %#RGv mask=%x RIP=%#RX64\n", uEflags.u, pMixedCtx->rsp, uMask, pMixedCtx->rip));
+                Log(("POPF %x -> %#RX64 mask=%x RIP=%#RX64\n", uEflags.u, pMixedCtx->rsp, uMask, pMixedCtx->rip));
                 pMixedCtx->eflags.u32 =   (pMixedCtx->eflags.u32 & ~(X86_EFL_POPF_BITS & uMask))
                                         | (uEflags.u32 & X86_EFL_POPF_BITS & uMask);
@@ -9004,5 +8999,5 @@
     AssertRCReturn(rc, rc);
 
-    Log(("#PF: cr2=%#RGv cs:rip=%#04x:%#RGv uErrCode %#RX32 cr3=%#RGv\n", pVmxTransient->uExitQualification, pMixedCtx->cs.Sel,
+    Log(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQualification, pMixedCtx->cs.Sel,
          pMixedCtx->rip, pVmxTransient->uExitIntrErrorCode, pMixedCtx->cr3));
 
Index: trunk/src/VBox/VMM/VMMR0/HWVMXR0.h
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWVMXR0.h	(revision 46050)
+++ trunk/src/VBox/VMM/VMMR0/HWVMXR0.h	(revision 46076)
@@ -74,8 +74,6 @@
                                                             VMXReadVmcs64(idxField, pVal)                  \
                                                           : VMXReadVmcs32(idxField, (uint32_t *)pVal)
-#  define VMXReadVmcsGstN(idxField, pVal)                 (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
-                                                            VMXReadVmcs64(idxField, pVal)                  \
-                                                          : VMXReadVmcs32(idxField, (uint32_t *)pVal)
-#  define VMXReadVmcsGstNByIdxVal(idxField, pVal)         VMXReadVmcsGstN(idxField, pVal)
+#  define VMXReadVmcsGstN                                 VMXReadVmcsHstN
+#  define VMXReadVmcsGstNByIdxVal                         VMXReadVmcsHstN
 # elif HC_ARCH_BITS == 32
 #  define VMXReadVmcsHstN                                 VMXReadVmcs32
