Changeset 46098 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- May 15, 2013 2:16:27 PM (12 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r46089 r46098 3866 3866 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc); 3867 3867 Log(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val)); 3868 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);3868 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc); 3869 3869 Log(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val)); 3870 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);3870 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc); 3871 3871 Log(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val)); 3872 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);3872 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc); 3873 3873 Log(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val)); 3874 3874 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc); … … 3906 3906 3907 3907 /* Guest bits. */ 3908 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);3908 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc); 3909 3909 Log(("Old Guest Rip %#RX64 New %#RX64\n", pCtx->rip, u64Val)); 3910 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);3910 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc); 3911 3911 Log(("Old Guest Rsp %#RX64 New %#RX64\n", pCtx->rsp, u64Val)); 3912 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);3912 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc); 3913 3913 Log(("Old Guest Rflags %#RX32 New %#RX32\n", pCtx->eflags.u32, u32Val)); 3914 rc = VMXReadVmcs32(VMX_VMCS16_GUEST_FIELD_VPID, &u32Val); AssertRC(rc);3914 rc = VMXReadVmcs32(VMX_VMCS16_GUEST_FIELD_VPID, &u32Val); AssertRC(rc); 3915 3915 Log(("VMX_VMCS16_GUEST_FIELD_VPID %u\n", u32Val)); 3916 3916 3917 3917 /* Host bits. */ 3918 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);3918 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc); 3919 3919 Log(("Host CR0 %#RHr\n", uHCReg)); 3920 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);3920 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc); 3921 3921 Log(("Host CR3 %#RHr\n", uHCReg)); 3922 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);3922 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc); 3923 3923 Log(("Host CR4 %#RHr\n", uHCReg)); 3924 3924 … … 3926 3926 PCX86DESCHC pDesc; 3927 3927 ASMGetGDTR(&HostGdtr); 3928 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_CS, &u32Val); 3928 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_CS, &u32Val); AssertRC(rc); 3929 3929 Log(("Host CS %#08x\n", u32Val)); 3930 3930 if (u32Val < HostGdtr.cbGdt) … … 3934 3934 } 3935 3935 3936 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_DS, &u32Val); AssertRC(rc);3936 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_DS, &u32Val); AssertRC(rc); 3937 3937 Log(("Host DS %#08x\n", u32Val)); 3938 3938 if (u32Val < HostGdtr.cbGdt) … … 3942 3942 } 3943 3943 3944 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_ES, &u32Val); AssertRC(rc);3944 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_ES, &u32Val); AssertRC(rc); 3945 3945 Log(("Host ES %#08x\n", u32Val)); 3946 3946 if (u32Val < HostGdtr.cbGdt) … … 3950 3950 } 3951 3951 3952 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_FS, &u32Val); AssertRC(rc);3952 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_FS, &u32Val); AssertRC(rc); 3953 3953 Log(("Host FS %#08x\n", u32Val)); 3954 3954 if (u32Val < HostGdtr.cbGdt) … … 3958 3958 } 3959 3959 3960 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_GS, &u32Val); AssertRC(rc);3960 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_GS, &u32Val); AssertRC(rc); 3961 3961 Log(("Host GS %#08x\n", u32Val)); 3962 3962 if (u32Val < HostGdtr.cbGdt) … … 3966 3966 } 3967 3967 3968 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_SS, &u32Val); AssertRC(rc);3968 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_SS, &u32Val); AssertRC(rc); 3969 3969 Log(("Host SS %#08x\n", u32Val)); 3970 3970 if (u32Val < HostGdtr.cbGdt) … … 3974 3974 } 3975 3975 3976 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_TR, &u32Val); AssertRC(rc);3976 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_TR, &u32Val); AssertRC(rc); 3977 3977 Log(("Host TR %#08x\n", u32Val)); 3978 3978 if (u32Val < HostGdtr.cbGdt) … … 3982 3982 } 3983 3983 3984 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);3984 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc); 3985 3985 Log(("Host TR Base %#RHv\n", uHCReg)); 3986 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);3986 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc); 3987 3987 Log(("Host GDTR Base %#RHv\n", uHCReg)); 3988 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);3988 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc); 3989 3989 Log(("Host IDTR Base %#RHv\n", uHCReg)); 3990 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);3990 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc); 3991 3991 Log(("Host SYSENTER CS %#08x\n", u32Val)); 3992 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);3992 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc); 3993 3993 Log(("Host SYSENTER EIP %#RHv\n", uHCReg)); 3994 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);3994 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc); 3995 3995 Log(("Host SYSENTER ESP %#RHv\n", uHCReg)); 3996 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);3996 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc); 3997 3997 Log(("Host RSP %#RHv\n", uHCReg)); 3998 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);3998 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc); 3999 3999 Log(("Host RIP %#RHv\n", uHCReg)); 4000 4000 # if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) … … 4064 4064 #endif /* VBOX_STRICT */ 4065 4065 4066 4066 4067 /** 4067 4068 * Executes the specified handler in 64-bit mode. … … 4126 4127 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z); 4127 4128 4128 /** @todo replace with hmR0VmxEnterRootMode() and LeaveRootMode(). */4129 /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */ 4129 4130 /* Make sure the VMX instructions don't cause #UD faults. */ 4130 4131 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE); … … 4206 4207 AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage)); 4207 4208 AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs, 4208 4209 pVCpu->hm.s.vmx.HCPhysVmcs)); 4209 4210 AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs, 4210 4211 pCache->TestOut.HCPhysVmcs)); … … 4214 4215 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache))); 4215 4216 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, 4216 pCache->TestOut.pCtx));4217 pCache->TestOut.pCtx)); 4217 4218 Assert(!(pCache->TestOut.eflags & X86_EFL_IF)); 4218 4219 #endif … … 4233 4234 static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu) 4234 4235 { 4235 #define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) 4236 { 4237 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); 4238 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; 4239 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; 4240 ++cReadFields; 4236 #define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \ 4237 { \ 4238 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \ 4239 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \ 4240 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \ 4241 ++cReadFields; \ 4241 4242 } 4242 4243 … … 4246 4247 uint32_t cReadFields = 0; 4247 4248 4248 /* Guest-natural selector base fields */ 4249 /* 4250 * Don't remove the #if 0'd fields in this code. They're listed here for consistency 4251 * and serve to indicate exceptions to the rules. 4252 */ 4253 4254 /* Guest-natural selector base fields. */ 4249 4255 #if 0 4250 4256 /* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */ … … 5202 5208 * 5203 5209 * @remarks No-long-jump zone!!! 5204 * @remarks Never call this function directly. Use the VMXLOCAL_READ_SEG() macro 5205 * as that takes care of whether to read from the VMCS cache or not. 5210 * @remarks Never call this function directly!!! Use the VMXLOCAL_READ_SEG() 5211 * macro as that takes care of whether to read from the VMCS cache or 5212 * not. 5206 5213 */ 5207 5214 DECLINLINE(int) hmR0VmxReadSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess, … … 5242 5249 return VINF_SUCCESS; 5243 5250 } 5251 5244 5252 5245 5253 #ifdef VMX_USE_CACHED_VMCS_ACCESSES … … 5252 5260 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel) 5253 5261 #endif 5262 5254 5263 5255 5264 /** … … 5689 5698 5690 5699 Log(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType)); 5700 5691 5701 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType); 5692 5702 AssertRC(rc); … … 7580 7590 { 7581 7591 VMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7592 7582 7593 /* We expose XSETBV to the guest, fallback to the recompiler for emulation. */ 7583 7594 /** @todo check if XSETBV is supported by the recompiler. */ … … 7592 7603 { 7593 7604 VMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7605 7594 7606 /* The guest should not invalidate the host CPU's TLBs, fallback to recompiler. */ 7595 7607 /** @todo implement EMInterpretInvpcid() */ … … 7682 7694 { 7683 7695 VMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7696 7684 7697 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */ 7685 7698 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess); … … 7697 7710 { 7698 7711 VMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7712 7699 7713 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */ 7700 7714 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdrand); … … 7712 7726 { 7713 7727 VMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7728 7714 7729 /* EMInterpretRdmsr() requires CR0, Eflags and SS segment register. */ 7715 7730 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); … … 7843 7858 { 7844 7859 VMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7860 7845 7861 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT. */ 7846 7862 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
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