Changeset 46099 in vbox for trunk/src/VBox/VMM

Timestamp:

May 15, 2013 2:23:49 PM (12 years ago)

Author:

vboxsync

Message:

VMM/VMMR0: Tidying of the assembly code.

Location:

trunk/src/VBox/VMM

Files:

• VMMR0/HMR0Mixed.mac (modified) (45 diffs)
• VMMSwitcher/LegacyandAMD64.mac (modified) (17 diffs)

trunk/src/VBox/VMM/VMMR0/HMR0Mixed.mac

@@ -35 +35 @@
     cli
 
-    ;/* Save all general purpose host registers. */
+    ; Save all general purpose host registers.
     MYPUSHAD
 
-    ;/* First we have to save some final CPU context registers. */
+    ; First we have to save some final CPU context registers.
     mov     eax, VMX_VMCS_HOST_RIP
 %ifdef RT_ARCH_AMD64
@@ -47 +47 @@
     vmwrite eax, ecx
 %endif
-    ;/* Note: assumes success... */
-
-    ;/* Manual save and restore:
-    ; * - General purpose registers except RIP, RSP
-    ; *
-    ; * Trashed:
-    ; * - CR2 (we don't care)
-    ; * - LDTR (reset to 0)
-    ; * - DRx (presumably not changed at all)
-    ; * - DR7 (reset to 0x400)
-    ; * - EFLAGS (reset to RT_BIT(1); not relevant)
-    ; *
-    ; */
-
-    ;/* Save the Guest CPU context pointer. */
+    ; Note: assumes success!
+
+    ; Manual save and restore:
+    ;  - General purpose registers except RIP, RSP.
+    ; 
+    ; Trashed:
+    ;  - CR2 (we don't care).
+    ;  - LDTR (reset to 0).
+    ;  - DRx (presumably not changed at all).
+    ;  - DR7 (reset to 0x400).
+    ;  - EFLAGS (reset to RT_BIT(1); not relevant).
+
+    ; Save the Guest CPU context pointer.
 %ifdef RT_ARCH_AMD64
  %ifdef ASM_CALL64_GCC
@@ -78 +76 @@
 %endif
 
-    ;/* Save segment registers */
-    ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
+    ; Save segment registers.
+    ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case).
     MYPUSHSEGS xAX, ax
 
@@ -101 +99 @@
 .no_cached_writes:
 
-    ; Save the pCache pointer
+    ; Save the pCache pointer.
     push    xBX
 %endif
 
-    ; Save the pCtx pointer
+    ; Save the pCtx pointer.
     push    xSI
 
-    ; Save LDTR
+    ; Save LDTR.
     xor     eax, eax
     sldt    ax
     push    xAX
 
-    ; The TR limit is reset to 0x67; restore it manually
+    ; The TR limit is reset to 0x67; restore it manually.
     str     eax
     push    xAX
 
-    ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
+    ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
     sub     xSP, xS*2
     sgdt    [xSP]
@@ -125 +123 @@
 
 %ifdef VBOX_WITH_DR6_EXPERIMENT
-    ; Restore DR6 - experiment, not safe!
+    ; Load DR6 - experiment, not safe!
     mov     xBX, [xSI + CPUMCTX.dr6]
     mov     dr6, xBX
 %endif
 
-    ; Restore CR2
+    ; Load CR2 if necessary (may be expensive as writing CR2 is a synchronizing instruction).
     mov     xBX, [xSI + CPUMCTX.cr2]
     mov     xDX, cr2
@@ -140 +138 @@
     mov     eax, VMX_VMCS_HOST_RSP
     vmwrite xAX, xSP
-    ;/* Note: assumes success... */
-    ;/* Don't mess with ESP anymore!! */
-
-    ;/* Restore Guest's general purpose registers. */
+    ; Note: assumes success!
+    ; Don't mess with ESP anymore!!!
+
+    ; Load Guest's general purpose registers.
     mov     eax, [xSI + CPUMCTX.eax]
     mov     ebx, [xSI + CPUMCTX.ebx]
@@ -150 +148 @@
     mov     ebp, [xSI + CPUMCTX.ebp]
 
-    ; resume or start?
+    ; Resume or start?
     cmp     xDI, 0                  ; fResume
-    je      .vmlauch_lauch
-
-    ;/* Restore edi & esi. */
+    je      .vmlaunch_launch
+
+    ; Restore edi & esi.
     mov     edi, [xSI + CPUMCTX.edi]
     mov     esi, [xSI + CPUMCTX.esi]
 
     vmresume
-    jmp     .vmlaunch_done;      ;/* here if vmresume detected a failure. */
-
-.vmlauch_lauch:
-    ;/* Restore edi & esi. */
+    jmp     .vmlaunch_done;      ; Here if vmresume detected a failure.
+
+.vmlaunch_launch:
+    ; Restore edi & esi.
     mov     edi, [xSI + CPUMCTX.edi]
     mov     esi, [xSI + CPUMCTX.esi]
 
     vmlaunch
-    jmp     .vmlaunch_done;      ;/* here if vmlaunch detected a failure. */
+    jmp     .vmlaunch_done;      ; Here if vmlaunch detected a failure.
 
 ALIGNCODE(16) ;; @todo YASM BUG - this alignment is wrong on darwin, it's 1 byte off.
@@ -174 +172 @@
     jz      near .vmxstart_start_failed
 
-    ; Restore base and limit of the IDTR & GDTR
+    ; Restore base and limit of the IDTR & GDTR.
     lidt    [xSP]
     add     xSP, xS*2
@@ -181 +179 @@
 
     push    xDI
-    mov     xDI, [xSP + xS * 3]         ; pCtx (*3 to skip the saved LDTR + TR)
+    mov     xDI, [xSP + xS * 3]         ; pCtx (*3 to skip the saved LDTR + TR).
 
     mov     [ss:xDI + CPUMCTX.eax], eax
@@ -195 +193 @@
 
 %ifdef RT_ARCH_AMD64
-    pop     xAX                                 ; the guest edi we pushed above
+    pop     xAX                                 ; The guest edi we pushed above.
     mov     dword [ss:xDI + CPUMCTX.edi], eax
 %else
-    pop     dword [ss:xDI + CPUMCTX.edi]        ; the guest edi we pushed above
+    pop     dword [ss:xDI + CPUMCTX.edi]        ; The guest edi we pushed above.
 %endif
 
 %ifdef VBOX_WITH_DR6_EXPERIMENT
-    ; Save DR6 - experiment, not safe!
+    ; Restore DR6 - experiment, not safe!
     mov     xAX, dr6
     mov     [ss:xDI + CPUMCTX.dr6], xAX
@@ -210 +208 @@
     ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
     ; @todo get rid of sgdt
-    pop     xBX         ; saved TR
+    pop     xBX         ; Saved TR
     sub     xSP, xS*2
     sgdt    [xSP]
     mov     xAX, xBX
-    and     al, 0F8h                                ; mask away TI and RPL bits, get descriptor offset.
+    and     al, 0F8h                                ; Mask away TI and RPL bits, get descriptor offset.
     add     xAX, [xSP + 2]                          ; eax <- GDTR.address + descriptor offset.
-    and     dword [ss:xAX + 4], ~0200h                 ; clear busy flag (2nd type2 bit)
+    and     dword [ss:xAX + 4], ~0200h              ; Clear busy flag (2nd type2 bit).
     ltr     bx
     add     xSP, xS*2
 
-    pop     xAX         ; saved LDTR
+    pop     xAX         ; Saved LDTR
     lldt    ax
 
-    add     xSP, xS      ; pCtx
+    add     xSP, xS     ; pCtx
 
 %ifdef VMX_USE_CACHED_VMCS_ACCESSES
-    pop     xDX         ; saved pCache
+    pop     xDX         ; Saved pCache
 
     mov     ecx, [ss:xDX + VMCSCACHE.Read.cValidEntries]
-    cmp     ecx, 0  ; can't happen
+    cmp     ecx, 0      ; Can't happen
     je      .no_cached_reads
     jmp     .cached_read
@@ -243 +241 @@
 
 %ifdef VBOX_WITH_OLD_VTX_CODE
-    ; Save CR2 for EPT
+    ; Restore CR2 into VMCS-cache field (for EPT).
     mov     xAX, cr2
     mov     [ss:xDX + VMCSCACHE.cr2], xAX
@@ -249 +247 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS xAX, ax
 
-    ; Restore general purpose registers
+    ; Restore general purpose registers.
     MYPOPAD
 
@@ -273 +271 @@
     ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
     ; @todo get rid of sgdt
-    pop     xBX         ; saved TR
+    pop     xBX         ; Saved TR
     sub     xSP, xS*2
     sgdt    [xSP]
     mov     xAX, xBX
-    and     al, 0F8h                                ; mask away TI and RPL bits, get descriptor offset.
+    and     al, 0F8h                                ; Mask away TI and RPL bits, get descriptor offset.
     add     xAX, [xSP + 2]                          ; eax <- GDTR.address + descriptor offset.
-    and     dword [ss:xAX + 4], ~0200h                 ; clear busy flag (2nd type2 bit)
+    and     dword [ss:xAX + 4], ~0200h              ; Clear busy flag (2nd type2 bit).
     ltr     bx
     add     xSP, xS*2
 
-    pop     xAX         ; saved LDTR
+    pop     xAX         ; Saved LDTR
     lldt    ax
 
@@ -292 +290 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS xAX, ax
 
@@ -301 +299 @@
 
 .vmxstart_start_failed:
-    ; Restore base and limit of the IDTR & GDTR
+    ; Restore base and limit of the IDTR & GDTR.
     lidt    [xSP]
     add     xSP, xS*2
@@ -310 +308 @@
     ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
     ; @todo get rid of sgdt
-    pop     xBX         ; saved TR
+    pop     xBX         ; Saved TR
     sub     xSP, xS*2
     sgdt    [xSP]
     mov     xAX, xBX
-    and     al, 0F8h                                ; mask away TI and RPL bits, get descriptor offset.
+    and     al, 0F8h                                ; Mask away TI and RPL bits, get descriptor offset.
     add     xAX, [xSP + 2]                          ; eax <- GDTR.address + descriptor offset.
-    and     dword [ss:xAX + 4], ~0200h                 ; clear busy flag (2nd type2 bit)
+    and     dword [ss:xAX + 4], ~0200h              ; Clear busy flag (2nd type2 bit).
     ltr     bx
     add     xSP, xS*2
 
-    pop     xAX         ; saved LDTR
+    pop     xAX         ; Saved LDTR
     lldt    ax
 
@@ -329 +327 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS xAX, ax
 
@@ -356 +354 @@
     cli
 
-    ;/* Save all general purpose host registers. */
+    ; Save all general purpose host registers.
     MYPUSHAD
 
-    ;/* First we have to save some final CPU context registers. */
+    ; First we have to save some final CPU context registers.
     lea     r10, [.vmlaunch64_done wrt rip]
-    mov     rax, VMX_VMCS_HOST_RIP  ;/* return address (too difficult to continue after VMLAUNCH?) */
+    mov     rax, VMX_VMCS_HOST_RIP      ; Return address (too difficult to continue after VMLAUNCH?).
     vmwrite rax, r10
-    ;/* Note: assumes success... */
-
-    ;/* Manual save and restore:
-    ; * - General purpose registers except RIP, RSP
-    ; *
-    ; * Trashed:
-    ; * - CR2 (we don't care)
-    ; * - LDTR (reset to 0)
-    ; * - DRx (presumably not changed at all)
-    ; * - DR7 (reset to 0x400)
-    ; * - EFLAGS (reset to RT_BIT(1); not relevant)
-    ; *
-    ; */
-
-    ;/* Save the Guest CPU context pointer. */
+    ; Note: assumes success!
+
+    ; Manual save and restore:
+    ;  - General purpose registers except RIP, RSP.
+    ; 
+    ; Trashed:
+    ;  - CR2 (we don't care).
+    ;  - LDTR (reset to 0).
+    ;  - DRx (presumably not changed at all).
+    ;  - DR7 (reset to 0x400).
+    ;  - EFLAGS (reset to RT_BIT(1); not relevant).
+
+    ; Save the Guest CPU context pointer.
 %ifdef ASM_CALL64_GCC
     ; fResume already in rdi
@@ -388 +384 @@
 %endif
 
-    ;/* Save segment registers */
-    ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
+    ; Save segment registers.
+    ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case).
     MYPUSHSEGS xAX, ax
 
@@ -411 +407 @@
 .no_cached_writes:
 
-    ; Save the pCache pointer
+    ; Save the pCache pointer.
     push    xBX
 %endif
 
 %ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-    ; Save the host MSRs and load the guest MSRs
+    ; Save the host MSRs and load the guest MSRs.
     LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
     LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
@@ -428 +424 @@
 %endif
 
-    ; Save the pCtx pointer
+    ; Save the pCtx pointer.
     push    xSI
 
-    ; Save LDTR
+    ; Save LDTR.
     xor     eax, eax
     sldt    ax
     push    xAX
 
-    ; The TR limit is reset to 0x67; restore it manually
+    ; The TR limit is reset to 0x67; restore it manually.
     str     eax
     push    xAX
 
-    ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
+    ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
     sub     xSP, xS*2
     sgdt    [xSP]
@@ -448 +444 @@
 
 %ifdef VBOX_WITH_DR6_EXPERIMENT
-    ; Restore DR6 - experiment, not safe!
+    ; Load DR6 - experiment, not safe!
     mov     xBX, [xSI + CPUMCTX.dr6]
     mov     dr6, xBX
 %endif
 
-    ; Restore CR2
+    ; Load CR2 if necessary (may be expensive as writing CR2 is a synchronizing instruction).
     mov     rbx, qword [xSI + CPUMCTX.cr2]
     mov     rdx, cr2
@@ -463 +459 @@
     mov     eax, VMX_VMCS_HOST_RSP
     vmwrite xAX, xSP
-    ;/* Note: assumes success... */
-    ;/* Don't mess with ESP anymore!! */
-
-    ;/* Restore Guest's general purpose registers. */
+    ; Note: assumes success!
+    ; Don't mess with ESP anymore!!!
+
+    ; Restore Guest's general purpose registers.
     mov     rax, qword [xSI + CPUMCTX.eax]
     mov     rbx, qword [xSI + CPUMCTX.ebx]
@@ -481 +477 @@
     mov     r15, qword [xSI + CPUMCTX.r15]
 
-    ; resume or start?
+    ; Resume or start?
     cmp     xDI, 0                  ; fResume
-    je      .vmlauch64_lauch
-
-    ;/* Restore edi & esi. */
+    je      .vmlaunch64_launch
+
+    ; Restore edi & esi.
     mov     rdi, qword [xSI + CPUMCTX.edi]
     mov     rsi, qword [xSI + CPUMCTX.esi]
 
     vmresume
-    jmp     .vmlaunch64_done;      ;/* here if vmresume detected a failure. */
-
-.vmlauch64_lauch:
-    ;/* Restore rdi & rsi. */
+    jmp     .vmlaunch64_done;      ; Here if vmresume detected a failure.
+
+.vmlaunch64_launch:
+    ; Restore rdi & rsi.
     mov     rdi, qword [xSI + CPUMCTX.edi]
     mov     rsi, qword [xSI + CPUMCTX.esi]
 
     vmlaunch
-    jmp     .vmlaunch64_done;      ;/* here if vmlaunch detected a failure. */
+    jmp     .vmlaunch64_done;      ; Here if vmlaunch detected a failure.
 
 ALIGNCODE(16)
@@ -533 +529 @@
 %endif
 
-    pop     xAX                                 ; the guest edi we pushed above
+    pop     xAX                                 ; The guest edi we pushed above
     mov     qword [xDI + CPUMCTX.edi], rax
 
 %ifdef VBOX_WITH_DR6_EXPERIMENT
-    ; Save DR6 - experiment, not safe!
+    ; Restore DR6 - experiment, not safe!
     mov     xAX, dr6
     mov     [xDI + CPUMCTX.dr6], xAX
@@ -543 +539 @@
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
-    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
+    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p).
     ; @todo get rid of sgdt
-    pop     xBX         ; saved TR
+    pop     xBX         ; Saved TR
     sub     xSP, xS*2
     sgdt    [xSP]
     mov     xAX, xBX
-    and     al, 0F8h                                ; mask away TI and RPL bits, get descriptor offset.
+    and     al, 0F8h                                ; Mask away TI and RPL bits, get descriptor offset.
     add     xAX, [xSP + 2]                          ; eax <- GDTR.address + descriptor offset.
-    and     dword [xAX + 4], ~0200h                 ; clear busy flag (2nd type2 bit)
+    and     dword [xAX + 4], ~0200h                 ; Clear busy flag (2nd type2 bit).
     ltr     bx
     add     xSP, xS*2
 
-    pop     xAX         ; saved LDTR
+    pop     xAX         ; Saved LDTR
     lldt    ax
 
@@ -561 +557 @@
 
 %ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-    ; Save the guest MSRs and load the host MSRs
+    ; Save the guest MSRs and load the host MSRs.
     LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
     LOADHOSTMSREX MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
@@ -574 +570 @@
 
 %ifdef VMX_USE_CACHED_VMCS_ACCESSES
-    pop     xDX         ; saved pCache
+    pop     xDX         ; Saved pCache
 
     mov     ecx, [xDX + VMCSCACHE.Read.cValidEntries]
-    cmp     ecx, 0  ; can't happen
+    cmp     ecx, 0      ; Can't happen
     je      .no_cached_reads
     jmp     .cached_read
@@ -591 +587 @@
 
 %ifdef VBOX_WITH_OLD_VTX_CODE
-    ; Save CR2 for EPT
+    ; Restore CR2 into VMCS-cache field (for EPT).
     mov     xAX, cr2
     mov     [xDX + VMCSCACHE.cr2], xAX
@@ -597 +593 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS xAX, ax
 
-    ; Restore general purpose registers
+    ; Restore general purpose registers.
     MYPOPAD
 
@@ -612 +608 @@
 
 .vmxstart64_invalid_vmcs_ptr:
-    ; Restore base and limit of the IDTR & GDTR
+    ; Restore base and limit of the IDTR & GDTR.
     lidt    [xSP]
     add     xSP, xS*2
@@ -619 +615 @@
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
-    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
+    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p).
     ; @todo get rid of sgdt
-    pop     xBX         ; saved TR
+    pop     xBX         ; Saved TR
     sub     xSP, xS*2
     sgdt    [xSP]
     mov     xAX, xBX
-    and     al, 0F8h                                ; mask away TI and RPL bits, get descriptor offset.
+    and     al, 0F8h                                ; Mask away TI and RPL bits, get descriptor offset.
     add     xAX, [xSP + 2]                          ; eax <- GDTR.address + descriptor offset.
-    and     dword [xAX + 4], ~0200h                 ; clear busy flag (2nd type2 bit)
+    and     dword [xAX + 4], ~0200h                 ; Clear busy flag (2nd type2 bit).
     ltr     bx
     add     xSP, xS*2
 
-    pop     xAX         ; saved LDTR
+    pop     xAX         ; Saved LDTR
     lldt    ax
 
@@ -637 +633 @@
 
 %ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-    ; Load the host MSRs
+    ; Load the host MSRs. Don't bother saving the guest MSRs as vmlaunch/vmresume failed.
     LOADHOSTMSR MSR_K8_KERNEL_GS_BASE
     LOADHOSTMSR MSR_K8_SF_MASK
@@ -653 +649 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS xAX, ax
 
@@ -662 +658 @@
 
 .vmxstart64_start_failed:
-    ; Restore base and limit of the IDTR & GDTR
+    ; Restore base and limit of the IDTR & GDTR.
     lidt    [xSP]
     add     xSP, xS*2
@@ -669 +665 @@
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
-    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
+    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p).
     ; @todo get rid of sgdt
-    pop     xBX         ; saved TR
+    pop     xBX         ; Saved TR
     sub     xSP, xS*2
     sgdt    [xSP]
     mov     xAX, xBX
-    and     al, 0F8h                                ; mask away TI and RPL bits, get descriptor offset.
+    and     al, 0F8h                                ; Mask away TI and RPL bits, get descriptor offset.
     add     xAX, [xSP + 2]                          ; eax <- GDTR.address + descriptor offset.
-    and     dword [xAX + 4], ~0200h                 ; clear busy flag (2nd type2 bit)
+    and     dword [xAX + 4], ~0200h                 ; Clear busy flag (2nd type2 bit).
     ltr     bx
     add     xSP, xS*2
 
-    pop     xAX         ; saved LDTR
+    pop     xAX         ; Saved LDTR
     lldt    ax
 
-    pop     xSI         ; pCtx (needed in rsi by the macros below)
+    pop     xSI         ; pCtx (needed in rsi by the macros below).
 
 %ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-    ; Load the host MSRs
+    ; Load the host MSRs. Don't bother saving the guest MSRs as vmlaunch/vmresume failed.
     LOADHOSTMSR MSR_K8_KERNEL_GS_BASE
     LOADHOSTMSR MSR_K8_SF_MASK
@@ -703 +699 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS xAX, ax
 
@@ -740 +736 @@
     pushf
 
-    ;/* Manual save and restore:
-    ; * - General purpose registers except RIP, RSP, RAX
-    ; *
-    ; * Trashed:
-    ; * - CR2 (we don't care)
-    ; * - LDTR (reset to 0)
-    ; * - DRx (presumably not changed at all)
-    ; * - DR7 (reset to 0x400)
-    ; */
-
-    ;/* Save all general purpose host registers. */
+    ; Manual save and restore:
+    ;  - General purpose registers except RIP, RSP, RAX
+    ; 
+    ; Trashed:
+    ;  - CR2 (we don't care)
+    ;  - LDTR (reset to 0)
+    ;  - DRx (presumably not changed at all)
+    ;  - DR7 (reset to 0x400)
+
+    ; Save all general purpose host registers.
     MYPUSHAD
 
-    ;/* Save the Guest CPU context pointer. */
+    ; Save the Guest CPU context pointer.
     mov     xSI, [xBP + xS*2 + RTHCPHYS_CB*2]   ; pCtx
-    push    xSI                     ; push for saving the state at the end
-
-    ; save host fs, gs, sysenter msr etc
+    push    xSI                                 ; push for saving the state at the end
+
+    ; Save host fs, gs, sysenter msr etc.
     mov     xAX, [xBP + xS*2]       ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
     push    xAX                     ; save for the vmload after vmrun
     vmsave
 
-    ; setup eax for VMLOAD
+    ; Setup eax for VMLOAD.
     mov     xAX, [xBP + xS*2 + RTHCPHYS_CB]     ; pVMCBPhys (64 bits physical address; take low dword only)
 
-    ;/* Restore Guest's general purpose registers. */
-    ;/* EAX is loaded from the VMCB by VMRUN */
+    ; Restore Guest's general purpose registers.
+    ; eax is loaded from the VMCB by VMRUN.
     mov     ebx, [xSI + CPUMCTX.ebx]
     mov     ecx, [xSI + CPUMCTX.ecx]
@@ -774 +769 @@
     mov     esi, [xSI + CPUMCTX.esi]
 
-    ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
+    ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch.
     clgi
     sti
 
-    ; load guest fs, gs, sysenter msr etc
+    ; Load guest fs, gs, sysenter msr etc.
     vmload
-    ; run the VM
+    ; Run the VM.
     vmrun
 
-    ;/* EAX is in the VMCB already; we can use it here. */
-
-    ; save guest fs, gs, sysenter msr etc
+    ; eax is in the VMCB already; we can use it here.
+
+    ; Save guest fs, gs, sysenter msr etc.
     vmsave
 
-    ; load host fs, gs, sysenter msr etc
-    pop     xAX                     ; pushed above
+    ; Load host fs, gs, sysenter msr etc.
+    pop     xAX                     ; Pushed above
     vmload
 
@@ -805 +800 @@
     mov     [ss:xAX + CPUMCTX.ebp], ebp
 
-    ; Restore general purpose registers
+    ; Restore general purpose registers.
     MYPOPAD
 
@@ -829 +824 @@
 ALIGNCODE(16)
 BEGINPROC MY_NAME(SVMR0VMRun64)
-    ; fake a cdecl stack frame
+    ; Fake a cdecl stack frame
  %ifdef ASM_CALL64_GCC
     push    rdx
@@ -844 +839 @@
     pushf
 
-    ;/* Manual save and restore:
-    ; * - General purpose registers except RIP, RSP, RAX
-    ; *
-    ; * Trashed:
-    ; * - CR2 (we don't care)
-    ; * - LDTR (reset to 0)
-    ; * - DRx (presumably not changed at all)
-    ; * - DR7 (reset to 0x400)
-    ; */
-
-    ;/* Save all general purpose host registers. */
+    ; Manual save and restore:
+    ;  - General purpose registers except RIP, RSP, RAX
+    ; 
+    ; Trashed:
+    ;  - CR2 (we don't care)
+    ;  - LDTR (reset to 0)
+    ;  - DRx (presumably not changed at all)
+    ;  - DR7 (reset to 0x400)
+    ; 
+
+    ; Save all general purpose host registers.
     MYPUSHAD
 
-    ;/* Save the Guest CPU context pointer. */
+    ; Save the Guest CPU context pointer.
     mov     rsi, [rbp + xS*2 + RTHCPHYS_CB*2]   ; pCtx
     push    rsi                     ; push for saving the state at the end
 
-    ; save host fs, gs, sysenter msr etc
+    ; Save host fs, gs, sysenter msr etc.
     mov     rax, [rbp + xS*2]       ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
-    push    rax                     ; save for the vmload after vmrun
+    push    rax                     ; Save for the vmload after vmrun
     vmsave
 
-    ; setup eax for VMLOAD
+    ; Setup eax for VMLOAD.
     mov     rax, [rbp + xS*2 + RTHCPHYS_CB]     ; pVMCBPhys (64 bits physical address; take low dword only)
 
-    ;/* Restore Guest's general purpose registers. */
-    ;/* RAX is loaded from the VMCB by VMRUN */
+    ; Restore Guest's general purpose registers.
+    ; rax is loaded from the VMCB by VMRUN.
     mov     rbx, qword [xSI + CPUMCTX.ebx]
     mov     rcx, qword [xSI + CPUMCTX.ecx]
@@ -886 +881 @@
     mov     rsi, qword [xSI + CPUMCTX.esi]
 
-    ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
+    ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch.
     clgi
     sti
 
-    ; load guest fs, gs, sysenter msr etc
+    ; Load guest fs, gs, sysenter msr etc.
     vmload
-    ; run the VM
+    ; Run the VM.
     vmrun
 
-    ;/* RAX is in the VMCB already; we can use it here. */
-
-    ; save guest fs, gs, sysenter msr etc
+    ; rax is in the VMCB already; we can use it here.
+
+    ; Save guest fs, gs, sysenter msr etc.
     vmsave
 
-    ; load host fs, gs, sysenter msr etc
+    ; Load host fs, gs, sysenter msr etc.
     pop     rax                     ; pushed above
     vmload
@@ -925 +920 @@
     mov     qword [rax + CPUMCTX.r15], r15
 
-    ; Restore general purpose registers
+    ; Restore general purpose registers.
     MYPOPAD
 

trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac

@@ -588 +588 @@
     mov     rbp, rsp
 
-    ; Make sure VT-x instructions are allowed
+    ; Make sure VT-x instructions are allowed.
     mov     rax, cr4
     or      rax, X86_CR4_VMXE
     mov     cr4, rax
 
-    ;/* Enter VMX Root Mode */
+    ; Enter VMX Root Mode.
     vmxon   [rbp + 8 + 8]
     jnc     .vmxon_success
@@ -621 +621 @@
     push    qword [rbp + 16 + 8];
 
-    ;/* Save segment registers */
+    ; Save segment registers.
     MYPUSHSEGS rax
 
 %ifdef VMX_USE_CACHED_VMCS_ACCESSES
-    ; Flush the VMCS write cache first (before any other vmreads/vmwrites!)
+    ; Flush the VMCS write cache first (before any other vmreads/vmwrites!).
     mov     rbx, [rbp + 24 + 8]                             ; pCache
 
@@ -662 +662 @@
     mov     qword [rbx + VMCSCACHE.uPos], 3
  %endif
-    ; Save the pCache pointer
+    ; Save the pCache pointer.
     push    rbx
 %endif
 
-    ; Save the host state that's relevant in the temporary 64 bits mode
+    ; Save the host state that's relevant in the temporary 64-bit mode.
     mov     rdx, cr0
     mov     eax, VMX_VMCS_HOST_CR0
@@ -697 +697 @@
 %endif
 
-    ; hopefully we can ignore TR (we restore it anyway on the way back to 32 bits mode)
-
-    ;/* First we have to save some final CPU context registers. */
+    ; Hopefully we can ignore TR (we restore it anyway on the way back to 32-bit mode).
+
+    ; First we have to save some final CPU context registers.
     lea     rdx, [.vmlaunch64_done wrt rip]
-    mov     rax, VMX_VMCS_HOST_RIP  ;/* return address (too difficult to continue after VMLAUNCH?) */
+    mov     rax, VMX_VMCS_HOST_RIP  ; Return address (too difficult to continue after VMLAUNCH?).
     vmwrite rax, rdx
-    ;/* Note: assumes success... */
-
-    ;/* Manual save and restore:
-    ; * - General purpose registers except RIP, RSP
-    ; *
-    ; * Trashed:
-    ; * - CR2 (we don't care)
-    ; * - LDTR (reset to 0)
-    ; * - DRx (presumably not changed at all)
-    ; * - DR7 (reset to 0x400)
-    ; * - EFLAGS (reset to RT_BIT(1); not relevant)
-    ; *
-    ; */
+    ; Note: assumes success!
+
+    ; Manual save and restore:
+    ;  - General purpose registers except RIP, RSP
+    ; 
+    ; Trashed:
+    ;  - CR2 (we don't care)
+    ;  - LDTR (reset to 0)
+    ;  - DRx (presumably not changed at all)
+    ;  - DR7 (reset to 0x400)
+    ;  - EFLAGS (reset to RT_BIT(1); not relevant)
 
 %ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-    ; Load the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
+    ; Load the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs.
     LOADGUESTMSR MSR_K8_LSTAR,          CPUMCTX.msrLSTAR
     LOADGUESTMSR MSR_K6_STAR,           CPUMCTX.msrSTAR
@@ -737 +735 @@
     push    rsi
 
-    ; Restore CR2
+    ; Load CR2 if necessary (may be expensive as writing CR2 is a synchronizing instruction).
     mov     rbx, qword [rsi + CPUMCTX.cr2]
     mov     rdx, cr2
@@ -747 +745 @@
     mov     eax, VMX_VMCS_HOST_RSP
     vmwrite rax, rsp
-    ;/* Note: assumes success... */
-    ;/* Don't mess with ESP anymore!! */
-
-    ;/* Restore Guest's general purpose registers. */
+    ; Note: assumes success!
+    ; Don't mess with ESP anymore!!!
+
+    ; Save Guest's general purpose registers.
     mov     rax, qword [rsi + CPUMCTX.eax]
     mov     rbx, qword [rsi + CPUMCTX.ebx]
@@ -765 +763 @@
     mov     r15, qword [rsi + CPUMCTX.r15]
 
-    ;/* Restore rdi & rsi. */
+    ; Save rdi & rsi.
     mov     rdi, qword [rsi + CPUMCTX.edi]
     mov     rsi, qword [rsi + CPUMCTX.esi]
 
     vmlaunch
-    jmp     .vmlaunch64_done;      ;/* here if vmlaunch detected a failure. */
+    jmp     .vmlaunch64_done;      ; Here if vmlaunch detected a failure.
 
 ALIGNCODE(16)
@@ -799 +797 @@
 %endif
 
-    pop     rax                                 ; the guest edi we pushed above
+    pop     rax         ; The guest edi we pushed above
     mov     qword [rdi + CPUMCTX.edi], rax
 
@@ -817 +815 @@
 
 %ifdef VMX_USE_CACHED_VMCS_ACCESSES
-    pop     rdi         ; saved pCache
+    pop     rdi         ; Saved pCache
 
  %ifdef VBOX_WITH_CRASHDUMP_MAGIC
@@ -830 +828 @@
 
     mov     ecx, [rdi + VMCSCACHE.Read.cValidEntries]
-    cmp     ecx, 0  ; can't happen
+    cmp     ecx, 0  ; Can't happen
     je      .no_cached_reads
     jmp     .cached_read
@@ -844 +842 @@
 
  %ifdef VBOX_WITH_OLD_VTX_CODE
-    ; Save CR2 for EPT
+    ; Restore CR2 into VMCS-cache field (for EPT).
     mov     rax, cr2
     mov     [rdi + VMCSCACHE.cr2], rax
@@ -853 +851 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS rax
 
@@ -870 +868 @@
 %endif
 
-    ; Write back the data and disable the VMCS
-    vmclear qword [rsp]  ;Pushed pVMCS
+    ; Write back the data and disable the VMCS.
+    vmclear qword [rsp]  ; Pushed pVMCS
     add     rsp, 8
 
 .vmstart64_vmxoff_end:
-    ; Disable VMX root mode
+    ; Disable VMX root mode.
     vmxoff
 .vmstart64_vmxon_failed:
@@ -911 +909 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS rax
 
@@ -933 +931 @@
 %endif
 
-    ; Restore segment registers
+    ; Restore segment registers.
     MYPOPSEGS rax
 
@@ -955 +953 @@
     pushf
 
-    ;/* Manual save and restore:
-    ; * - General purpose registers except RIP, RSP, RAX
-    ; *
-    ; * Trashed:
-    ; * - CR2 (we don't care)
-    ; * - LDTR (reset to 0)
-    ; * - DRx (presumably not changed at all)
-    ; * - DR7 (reset to 0x400)
-    ; */
-
-    ;/* Save the Guest CPU context pointer. */
-    push    rsi                     ; push for saving the state at the end
-
-    ; save host fs, gs, sysenter msr etc
+    ; Manual save and restore:
+    ;  - General purpose registers except RIP, RSP, RAX
+    ; 
+    ; Trashed:
+    ;  - CR2 (we don't care)
+    ;  - LDTR (reset to 0)
+    ;  - DRx (presumably not changed at all)
+    ;  - DR7 (reset to 0x400)
+
+    ; Save the Guest CPU context pointer.
+    push    rsi                             ; Push for saving the state at the end
+
+    ; Save host fs, gs, sysenter msr etc
     mov     rax, [rbp + 8 + 8]              ; pVMCBHostPhys (64 bits physical address)
-    push    rax                             ; save for the vmload after vmrun
+    push    rax                             ; Save for the vmload after vmrun
     vmsave
 
-    ; setup eax for VMLOAD
+    ; Setup eax for VMLOAD
     mov     rax, [rbp + 8 + 8 + RTHCPHYS_CB]   ; pVMCBPhys (64 bits physical address)
 
-    ;/* Restore Guest's general purpose registers. */
-    ;/* RAX is loaded from the VMCB by VMRUN */
+    ; Restore Guest's general purpose registers.
+    ; rax is loaded from the VMCB by VMRUN.
     mov     rbx, qword [rsi + CPUMCTX.ebx]
     mov     rcx, qword [rsi + CPUMCTX.ecx]
@@ -993 +990 @@
     mov     rsi, qword [rsi + CPUMCTX.esi]
 
-    ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
+    ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch.
     clgi
     sti
 
-    ; load guest fs, gs, sysenter msr etc
+    ; Load guest fs, gs, sysenter msr etc
     vmload
-    ; run the VM
+    ; Run the VM
     vmrun
 
-    ;/* RAX is in the VMCB already; we can use it here. */
-
-    ; save guest fs, gs, sysenter msr etc
+    ; rax is in the VMCB already; we can use it here.
+
+    ; Save guest fs, gs, sysenter msr etc.
     vmsave
 
-    ; load host fs, gs, sysenter msr etc
-    pop     rax                     ; pushed above
+    ; Load host fs, gs, sysenter msr etc.
+    pop     rax                     ; Pushed above
     vmload