Changeset 46192 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

May 21, 2013 10:25:57 AM (12 years ago)

Author:

vboxsync

Message:

VMM/HM: CR0 and CR4 masks can be 32-bit. Plus hungarian naming fixes.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMVMXR0.cpp (modified) (5 diffs)
• HWVMXR0.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -2132 +2132 @@
     Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
     Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
-    Assert(uSelCS != 0);
-    Assert(uSelTR != 0);
+    Assert(uSelCS);
+    Assert(uSelTR);
 
     /* Assertion is right but we would not have updated u32ExitCtls yet. */
@@ -2880 +2880 @@
 
         /* Write the CR0 mask into the VMCS and update the VCPU's copy of the current CR0 mask. */
-        pVCpu->hm.s.vmx.cr0_mask = u32CR0Mask;
+        pVCpu->hm.s.vmx.u32CR0Mask = u32CR0Mask;
         rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32CR0Mask);
         AssertRCReturn(rc, rc);
@@ -3061 +3061 @@
                     | X86_CR4_PSE
                     | X86_CR4_VMXE;
-        pVCpu->hm.s.vmx.cr4_mask = u32CR4Mask;
+        pVCpu->hm.s.vmx.u32CR4Mask = u32CR4Mask;
         rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
         AssertRCReturn(rc, rc);
@@ -4775 +4775 @@
         AssertRCReturn(rc, rc);
 
-        uVal = (uShadow & pVCpu->hm.s.vmx.cr0_mask) | (uVal & ~pVCpu->hm.s.vmx.cr0_mask);
+        uVal = (uShadow & pVCpu->hm.s.vmx.u32CR0Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR0Mask);
         CPUMSetGuestCR0(pVCpu, uVal);
         pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR0;
@@ -4806 +4806 @@
         AssertRCReturn(rc, rc);
 
-        uVal = (uShadow & pVCpu->hm.s.vmx.cr4_mask) | (uVal & ~pVCpu->hm.s.vmx.cr4_mask);
+        uVal = (uShadow & pVCpu->hm.s.vmx.u32CR4Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR4Mask);
         CPUMSetGuestCR4(pVCpu, uVal);
         pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR4;

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -370 +370 @@
         ASMMemZeroPage(pVCpu->hm.s.vmx.pvVmcs);
 
-        pVCpu->hm.s.vmx.cr0_mask = 0;
-        pVCpu->hm.s.vmx.cr4_mask = 0;
+        pVCpu->hm.s.vmx.u32CR0Mask = 0;
+        pVCpu->hm.s.vmx.u32CR4Mask = 0;
 
         /* Allocate one page for the virtual APIC page for TPR caching. */
@@ -2119 +2119 @@
             val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_MP;
 
-        pVCpu->hm.s.vmx.cr0_mask = val;
+        pVCpu->hm.s.vmx.u32CR0Mask = val;
 
         rc |= VMXWriteVmcs(VMX_VMCS_CTRL_CR0_MASK, val);
@@ -2192 +2192 @@
               | X86_CR4_PSE
               | X86_CR4_VMXE;
-        pVCpu->hm.s.vmx.cr4_mask = val;
+        pVCpu->hm.s.vmx.u32CR4Mask = val;
 
         rc |= VMXWriteVmcs(VMX_VMCS_CTRL_CR4_MASK, val);
@@ -2467 +2467 @@
     VMXReadCachedVmcs(VMX_VMCS_CTRL_CR0_READ_SHADOW,     &valShadow);
     VMXReadCachedVmcs(VMX_VMCS_GUEST_CR0,                &val);
-    val = (valShadow & pVCpu->hm.s.vmx.cr0_mask) | (val & ~pVCpu->hm.s.vmx.cr0_mask);
+    val = (valShadow & pVCpu->hm.s.vmx.u32CR0Mask) | (val & ~pVCpu->hm.s.vmx.u32CR0Mask);
     CPUMSetGuestCR0(pVCpu, val);
 
     VMXReadCachedVmcs(VMX_VMCS_CTRL_CR4_READ_SHADOW,     &valShadow);
     VMXReadCachedVmcs(VMX_VMCS_GUEST_CR4,                &val);
-    val = (valShadow & pVCpu->hm.s.vmx.cr4_mask) | (val & ~pVCpu->hm.s.vmx.cr4_mask);
+    val = (valShadow & pVCpu->hm.s.vmx.u32CR4Mask) | (val & ~pVCpu->hm.s.vmx.u32CR4Mask);
     CPUMSetGuestCR4(pVCpu, val);