Changeset 46267 in vbox for trunk/src/VBox/VMM

Timestamp:

May 26, 2013 11:29:24 AM (12 years ago)

Author:

vboxsync

Message:

VMM: Optimized 64-bit host VT-x world-switch.

Location:

trunk/src/VBox/VMM

Files:

• VMMR0/HMR0A.asm (modified) (4 diffs)
• VMMR0/HMR0Mixed.mac (modified) (11 diffs)
• VMMR0/HMVMXR0.cpp (modified) (12 diffs)
• include/HMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMR0/HMR0A.asm

@@ -58 +58 @@
    %define HM_64_BIT_USE_NULL_SEL
   %endif
+ %endif
+%endif
+
+%ifndef VBOX_WITH_OLD_VTX_CODE
+ %ifdef RT_ARCH_AMD64
+  %define VBOX_SKIP_RESTORE_SEG
  %endif
 %endif
@@ -155 +161 @@
 %endif
 
+%ifdef VBOX_SKIP_RESTORE_SEG
+%macro MYPUSHSEGS64 2
+%endmacro
+
+%macro MYPOPSEGS64 2
+%endmacro
+%else ; !VBOX_SKIP_RESTORE_SEG
 ; trashes, rax, rdx & rcx
 %macro MYPUSHSEGS64 2
@@ -218 +231 @@
  %endif
 %endmacro
+%endif ; VBOX_SKIP_RESTORE_SEG
 
 %macro MYPUSHAD32 0
@@ -270 +284 @@
 
 BEGINCODE
+
+
+;/**
+; * Restores host-state fields.
+; *
+; * @returns VBox status code
+; * @param   u32RestoreHostFlags  x86: [ebp + 08h]  msc: rcx  gcc: rdi   u32RestoreHost - RestoreHost flags.
+; * @param   pRestoreHost         x86: [ebp + 0ch]  msc: rdx  gcc: rsi   pRestoreHost - Pointer to the RestoreHost struct.
+; */
+ALIGNCODE(16)
+BEGINPROC VMXRestoreHostState
+%ifdef RT_ARCH_AMD64
+ %ifndef ASM_CALL64_GCC
+    ; On msc R10, R11 are scratch, RDI and RSI are not. So we must save and restore them!
+    mov         r10, rdi
+    mov         r11, rsi
+    ; Switch to common register usage (i.e. gcc's in this function)
+    mov         rdi, rcx
+    mov         rsi, rdx
+ %endif
+
+    test        edi, VMX_RESTORE_HOST_GDTR
+    jz          near .test_idtr
+    lgdt        [rsi + 18h]                ; pRestoreHost->HostGdtr
+
+.test_idtr:
+    test        edi, VMX_RESTORE_HOST_IDTR
+    jz          near .test_ds
+    lidt        [rsi + 22h]                ; pRestoreHost->HostIdtr
+
+.test_ds:
+    test        edi, VMX_RESTORE_HOST_SEL_DS
+    jz          near .test_es
+    mov         ax, word [rsi]             ; pRestoreHost->uHostSelDS
+    mov         ds, ax              
+
+.test_es:
+    test        edi, VMX_RESTORE_HOST_SEL_ES
+    jz          near .test_fs
+    mov         ax, word [rsi + 2]         ; pRestoreHost->uHostSelES
+    mov         es, ax 
+
+.test_fs:
+    ; We're only restoring the selector. The base is valid and restored by VT-x. If we get an interrupt in between FS & GS
+    ; below, we are fine as the base is what is relevant in 64-bit mode. We need to disable interrupts only during
+    ; writing of the selector as that zaps (trashes) the upper-part of the base until we wrmsr the full 64-bit base.
+
+    test        edi, VMX_RESTORE_HOST_SEL_FS
+    jz          near .test_gs
+    mov         ax, word [rsi + 4]        ; pRestoreHost->uHostSelFS
+    cli                                   ; Disable interrupts as mov fs, ax will zap the upper part of the base
+    mov         fs, ax
+    mov         eax, dword [rsi + 8]      ; pRestoreHost->uHostFSBase - Lo
+    mov         edx, dword [rsi + 0Ch]    ; pRestoreHost->uHostFSBase - Hi
+    mov         ecx, MSR_K8_FS_BASE
+    wrmsr
+    sti                                   ; Re-enable interrupts as fsbase is consistent now
+
+.test_gs:
+    test        edi, VMX_RESTORE_HOST_SEL_GS
+    jz          near .restore_success
+    mov         ax, word [rsi + 6]        ; pRestoreHost->uHostSelGS
+    cli                                   ; Disable interrupts as mov gs, ax will zap the upper part of the base
+    mov         gs, ax
+    mov         eax, dword [rsi + 10h]    ; pRestoreHost->uHostGSBase - Lo
+    mov         edx, dword [rsi + 14h]    ; pRestoreHost->uHostGSBase - Hi
+    mov         ecx, MSR_K8_GS_BASE
+    wrmsr
+    sti                                   ; Re-enable interrupts as gsbase is consistent now
+
+.restore_success:
+    mov         eax, VINF_SUCCESS
+ %ifndef ASM_CALL64_GCC
+    ; Restore RDI and RSI on MSC.
+    mov         rdi, r10
+    mov         rsi, r11
+ %endif
+%else  ; RT_ARCH_X86
+    mov         eax, VERR_NOT_IMPLEMENTED
+%endif
+    ret
+ENDPROC VMXRestoreHostState
 
 

trunk/src/VBox/VMM/VMMR0/HMR0Mixed.mac

@@ -18 +18 @@
 ;
 
+%ifndef VBOX_WITH_OLD_VTX_CODE
+ %ifdef RT_ARCH_AMD64
+  %define VMX_SKIP_GDTR_IDTR
+ %endif
+%endif
 
 ;/**
@@ -116 +121 @@
 
     ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
+%ifdef VMX_SKIP_GDTR_IDTR
     sub     xSP, xS*2
     sgdt    [xSP]
@@ -121 +127 @@
     sub     xSP, xS*2
     sidt    [xSP]
+%endif
 
 %ifdef VBOX_WITH_DR6_EXPERIMENT
@@ -173 +180 @@
 
     ; Restore base and limit of the IDTR & GDTR.
+%ifdef VMX_SKIP_GDTR_IDTR
     lidt    [xSP]
     add     xSP, xS*2
     lgdt    [xSP]
     add     xSP, xS*2
+%endif
 
     push    xDI
@@ -263 +272 @@
 .vmxstart_invalid_vmcs_ptr:
     ; Restore base and limit of the IDTR & GDTR
+%ifdef VMX_SKIP_GDTR_IDTR
     lidt    [xSP]
     add     xSP, xS*2
     lgdt    [xSP]
     add     xSP, xS*2
+%endif
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
@@ -300 +311 @@
 .vmxstart_start_failed:
     ; Restore base and limit of the IDTR & GDTR.
+%ifdef VMX_SKIP_GDTR_IDTR
     lidt    [xSP]
     add     xSP, xS*2
     lgdt    [xSP]
     add     xSP, xS*2
+%endif
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
@@ -437 +450 @@
 
     ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
+%ifdef VMX_SKIP_GDTR_IDTR
     sub     xSP, xS*2
     sgdt    [xSP]
@@ -442 +456 @@
     sub     xSP, xS*2
     sidt    [xSP]
+%endif
 
 %ifdef VBOX_WITH_DR6_EXPERIMENT
@@ -502 +517 @@
 
     ; Restore base and limit of the IDTR & GDTR
+%ifdef VMX_SKIP_GDTR_IDTR
     lidt    [xSP]
     add     xSP, xS*2
     lgdt    [xSP]
     add     xSP, xS*2
+%endif
 
     push    xDI
@@ -609 +626 @@
 .vmxstart64_invalid_vmcs_ptr:
     ; Restore base and limit of the IDTR & GDTR.
+%ifdef VMX_SKIP_GDTR_IDTR
     lidt    [xSP]
     add     xSP, xS*2
     lgdt    [xSP]
     add     xSP, xS*2
+%endif
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
@@ -659 +678 @@
 .vmxstart64_start_failed:
     ; Restore base and limit of the IDTR & GDTR.
+%ifdef VMX_SKIP_GDTR_IDTR
     lidt    [xSP]
     add     xSP, xS*2
     lgdt    [xSP]
     add     xSP, xS*2
+%endif
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -2091 +2091 @@
 {
     int rc = VERR_INTERNAL_ERROR_5;
-    RTSEL uSelCS = 0;
-    RTSEL uSelSS = 0;
     RTSEL uSelDS = 0;
     RTSEL uSelES = 0;
@@ -2100 +2098 @@
 
     /*
-     * Host Selector registers.
+     * Host DS, ES, FS and GS segment registers.
      */
+#if HC_ARCH_BITS == 64
+    pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
+    uSelDS = ASMGetDS();
+    uSelES = ASMGetES();
+    uSelFS = ASMGetFS();
+    uSelGS = ASMGetGS();
+#endif
+
+    /*
+     * Host CS and SS segment registers.
+     */
+    RTSEL uSelCS;
+    RTSEL uSelSS;
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
     if (HMVMX_IS_64BIT_HOST_MODE())
@@ -2119 +2130 @@
 #endif
 
-    /* Note: VT-x is picky about the RPL of the selectors here; we'll restore them manually. */
+    /*
+     * Host TR segment register.
+     */
     uSelTR = ASMGetTR();
 
+#if HC_ARCH_BITS == 64
+    /*
+     * Determine if the host segment registers are suitable for VT-x. Otherwise use zero to gain VM-entry and restore them
+     * before we get preempted. See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
+     */
+    if (uSelDS & (X86_SEL_RPL | X86_SEL_LDT))
+    {
+        pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_DS;
+        pVCpu->hm.s.vmx.RestoreHost.uHostSelDS = uSelDS;
+        uSelDS = 0;
+    }
+    if (uSelES & (X86_SEL_RPL | X86_SEL_LDT))
+    {
+        pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_ES;
+        pVCpu->hm.s.vmx.RestoreHost.uHostSelES = uSelES;
+        uSelES = 0;
+    }
+    if (uSelFS & (X86_SEL_RPL | X86_SEL_LDT))
+    {
+        pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_FS;
+        pVCpu->hm.s.vmx.RestoreHost.uHostSelFS = uSelFS;
+        uSelFS = 0;
+    }
+    if (uSelGS & (X86_SEL_RPL | X86_SEL_LDT))
+    {
+        pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_GS;
+        pVCpu->hm.s.vmx.RestoreHost.uHostSelGS = uSelGS;
+        uSelGS = 0;
+    }
+#endif
+
     /* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers"  */
-    /** @todo Verify if we have any platform that actually run with DS or ES with
-     *        RPL != 0 in kernel space. */
     Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
     Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
@@ -2144 +2186 @@
     rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_CS, uSelCS);      AssertRCReturn(rc, rc);
     rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_SS, uSelSS);      AssertRCReturn(rc, rc);
-    /* Avoid the VMWRITEs as we set the following segments to 0 and the VMCS fields are already  0 (since g_HvmR0 is static) */
-#if 0
+#if HC_ARCH_BITS == 64
     rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_DS, uSelDS);      AssertRCReturn(rc, rc);
     rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_ES, uSelES);      AssertRCReturn(rc, rc);
@@ -2156 +2197 @@
      * Host GDTR and IDTR.
      */
-    /** @todo Despite VT-x -not- restoring the limits on GDTR and IDTR it should
-     *        be safe to -not- save and restore GDTR and IDTR in the assembly
-     *        code and just do it here and don't care if the limits are zapped on
-     *        VM-exit. */
     RTGDTR Gdtr;
     RT_ZERO(Gdtr);
@@ -2182 +2219 @@
         rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);      AssertRCReturn(rc, rc);
         rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);      AssertRCReturn(rc, rc);
+
+#if HC_ARCH_BITS == 64
+        /*
+         * Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps them to the
+         * maximum limit (0xffff) on every VM-exit.
+         */
+        if (Gdtr.cbGdt != 0xffff)
+        {
+            pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDTR;
+            AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
+            memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
+        }
+
+        /*
+         * IDT limit is practically 0xfff. Therefore if the host has the limit as 0xfff, VT-x bloating the limit to 0xffff
+         * is not a problem as it's not possible to get at them anyway. See Intel spec. 6.14.1 "64-Bit Mode IDT" and
+         * Intel spec. 6.2 "Exception and Interrupt Vectors".
+         */
+        if (Idtr.cbIdt < 0x0fff)
+        {
+            pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_IDTR;
+            AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
+            memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
+        }
+#endif
     }
 
@@ -2190 +2252 @@
     if ((uSelTR & X86_SEL_MASK) > Gdtr.cbGdt)
     {
-        AssertMsgFailed(("hmR0VmxSaveHostSegmentRegs: TR selector exceeds limit.TR=%RTsel Gdtr.cbGdt=%#x\n", uSelTR, Gdtr.cbGdt));
+        AssertMsgFailed(("hmR0VmxSaveHostSegmentRegs: TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt));
         return VERR_VMX_INVALID_HOST_STATE;
     }
@@ -2217 +2279 @@
     /*
      * Host FS base and GS base.
-     * For 32-bit hosts the base is handled by the assembly code where we push/pop FS and GS which                                                                .
-     * would take care of the bases. In 64-bit, the MSRs come into play.
      */
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
@@ -2225 +2285 @@
         uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
         uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
-        rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
-        AssertRCReturn(rc, rc);
-        rc = VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
-        AssertRCReturn(rc, rc);
+        rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);          AssertRCReturn(rc, rc);
+        rc = VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);          AssertRCReturn(rc, rc);
+
+# if HC_ARCH_BITS == 64
+        /* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
+        if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
+            pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
+        if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
+            pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
+# endif
     }
 #endif
@@ -5775 +5841 @@
     }
 
+    STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
+    STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
+    STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
     STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
     STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
@@ -6425 +6494 @@
      *        we are actually going to be preempted, not all the time like we
      *        currently do. */
+
+    /* Restore host-state bits that VT-x only restores partially. */
+    if (pVCpu->hm.s.vmx.fRestoreHostFlags)
+    {
+        VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
+        pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
+    }
+
     /*
      * Sync the current VMCS (writes back internal data back into the VMCS region in memory)
@@ -6740 +6817 @@
 #endif
 
-    STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
     TMNotifyStartOfExecution(pVCpu);                            /* Finally, notify TM to resume its clocks as we're about
                                                                     to start executing. */
+    STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
 }
 

trunk/src/VBox/VMM/include/HMInternal.h

@@ -682 +682 @@
         PGMMODE                     enmPrevGuestMode;
 #else
+        uint32_t                    fRestoreHostFlags;
+        VMXRESTOREHOST              RestoreHost;
         /** Set if guest was executing in real mode (extra checks). */
         bool                        fWasInRealMode;