Changeset 46272 in vbox for trunk/src/VBox/Devices/Audio

Timestamp:

May 26, 2013 6:02:48 PM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

86011

Message:

Audio/DevIchHda: Implement support for R0 and RC

File:

• trunk/src/VBox/Devices/Audio/DevIchHda.cpp (modified) (61 diffs)

trunk/src/VBox/Devices/Audio/DevIchHda.cpp

@@ -28 +28 @@
 
 #include <iprt/assert.h>
-#include <iprt/uuid.h>
-#include <iprt/string.h>
-#include <iprt/mem.h>
 #include <iprt/asm.h>
 #include <iprt/asm-math.h>
+#ifdef IN_RING3
+# include <iprt/uuid.h>
+# include <iprt/string.h>
+# include <iprt/mem.h>
+#endif
 
 #include "VBoxDD.h"
@@ -51 +53 @@
 /* HP Pavilion dv4t-1300 */
 # define HDA_PCI_VENDOR_ID 0x103c
-# define HDA_PCI_DEICE_ID 0x30f7
+# define HDA_PCI_DEVICE_ID 0x30f7
 #elif defined(VBOX_WITH_INTEL_HDA)
 /* Intel HDA controller */
 # define HDA_PCI_VENDOR_ID 0x8086
-# define HDA_PCI_DEICE_ID 0x2668
+# define HDA_PCI_DEVICE_ID 0x2668
 #elif defined(VBOX_WITH_NVIDIA_HDA)
 /* nVidia HDA controller */
 # define HDA_PCI_VENDOR_ID 0x10de
-# define HDA_PCI_DEICE_ID 0x0ac0
+# define HDA_PCI_DEVICE_ID 0x0ac0
 #else
 # error "Please specify your HDA device vendor/device IDs"
@@ -453 +455 @@
 {
     /** The PCI device structure. */
-    PCIDevice               PciDev;
-    /** Pointer to the device instance. */
-    PPDMDEVINSR3            pDevIns;
+    PCIDevice                          PciDev;
+    /** R3 Pointer to the device instance. */
+    PPDMDEVINSR3                       pDevInsR3;
+    /** R0 Pointer to the device instance. */
+    PPDMDEVINSR0                       pDevInsR0;
+    /** R0 Pointer to the device instance. */
+    PPDMDEVINSRC                       pDevInsRC;
+
+    uint32_t                           u32Padding;
+
     /** Pointer to the connector of the attached audio driver. */
-    PPDMIAUDIOCONNECTOR     pDrv;
+    R3PTRTYPE(PPDMIAUDIOCONNECTOR)     pDrv;
     /** Pointer to the attached audio driver. */
-    PPDMIBASE               pDrvBase;
+    R3PTRTYPE(PPDMIBASE)               pDrvBase;
     /** The base interface for LUN\#0. */
-    PDMIBASE                IBase;
-    RTGCPHYS                MMIOBaseAddr;
-    uint32_t                au32Regs[HDA_NREGS];
-    HDABDLEDESC             StInBdle;
-    HDABDLEDESC             StOutBdle;
-    HDABDLEDESC             StMicBdle;
+    PDMIBASE                           IBase;
+    RTGCPHYS                           MMIOBaseAddr;
+    uint32_t                           au32Regs[HDA_NREGS];
+    HDABDLEDESC                        StInBdle;
+    HDABDLEDESC                        StOutBdle;
+    HDABDLEDESC                        StMicBdle;
+    uint64_t                           u64CORBBase;
+    uint64_t                           u64RIRBBase;
+    uint64_t                           u64DPBase;
+    /** pointer to CORB buf */
+    R3PTRTYPE(uint32_t *)              pu32CorbBuf;
+    /** size in bytes of CORB buf */
+    uint32_t                           cbCorbBuf;
+    uint32_t                           u32Padding2;
+    /** pointer on RIRB buf */
+    R3PTRTYPE(uint64_t *)              pu64RirbBuf;
+    /** size in bytes of RIRB buf */
+    uint32_t                           cbRirbBuf;
+    /** indicates if HDA in reset. */
+    bool                               fInReset;
     /** Interrupt on completion */
-    bool                    fCviIoc;
-    uint64_t                u64CORBBase;
-    uint64_t                u64RIRBBase;
-    uint64_t                u64DPBase;
-    /** pointer to CORB buf */
-    uint32_t               *pu32CorbBuf;
-    /** size in bytes of CORB buf */
-    uint32_t                cbCorbBuf;
-    /** pointer on RIRB buf */
-    uint64_t               *pu64RirbBuf;
-    /** size in bytes of RIRB buf */
-    uint32_t                cbRirbBuf;
-    /** indicates if HDA in reset. */
-    bool                    fInReset;
+    bool                               fCviIoc;
+    /** Flag whether the R0 part is enabled. */
+    bool                               fR0Enabled;
+    /** Flag whether the RC part is enabled. */
+    bool                               fRCEnabled;
     /** The HDA codec state. */
-    HDACODEC                Codec;
+    R3PTRTYPE(PHDACODEC)               pCodec;
+    uint64_t                           u64BaseTS;
     /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
-    uint8_t                 u8Counter;
-    uint64_t                u64BaseTS;
+    uint8_t                            u8Counter;
+    uint8_t                            au8Padding[7];
 } HDASTATE;
 /** Pointer to the ICH Intel HD Audio Controller state. */
@@ -492 +507 @@
 
 #define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
-    ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
+    ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
 #define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
-    ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
+    ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
 
 
@@ -500 +515 @@
 *   Internal Functions                                                         *
 *******************************************************************************/
+#ifndef VBOX_DEVICE_STRUCT_TESTCASE
 static FNPDMDEVRESET hdaReset;
 
@@ -540 +556 @@
 static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
 
+#ifdef IN_RING3
 DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
                                            PHDASTREAMTRANSFERDESC pStreamDesc);
@@ -545 +562 @@
 #ifdef LOG_ENABLED
 static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
+#endif
 #endif
 
@@ -727 +745 @@
 };
 
-
+#ifdef IN_RING3
 /** HDABDLEDESC field descriptors the v3+ saved state. */
 static SSMFIELD const g_aHdaBDLEDescFields[] =
@@ -756 +774 @@
     SSMFIELD_ENTRY_TERM()
 };
+#endif
 
 /**
@@ -765 +784 @@
 };
 
-
+#ifdef IN_RING3
 DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
 {
     if (pThis->u64DPBase & DPBASE_ENABLED)
-        PDMDevHlpPCIPhysWrite(pThis->pDevIns,
+        PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
                               (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
                               pStreamDesc->pu32Lpib, sizeof(uint32_t));
 }
+#endif
+
 DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
 {
@@ -807 +828 @@
     {
         Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
-        PDMDevHlpPCISetIrq(pThis->pDevIns, 0 , fIrq);
+        PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
     }
     return VINF_SUCCESS;
@@ -919 +940 @@
 }
 
-
+#ifdef IN_RING3
 static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
 {
@@ -926 +947 @@
     {
         Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
-        rc = PDMDevHlpPhysRead(pThis->pDevIns, pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
+        rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
         if (RT_FAILURE(rc))
             AssertRCReturn(rc, rc);
@@ -955 +976 @@
     {
         Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
-        rc = PDMDevHlpPCIPhysWrite(pThis->pDevIns, pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
+        rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
         if (RT_FAILURE(rc))
             AssertRCReturn(rc, rc);
@@ -1003 +1024 @@
         corbRp++;
         cmd = pThis->pu32CorbBuf[corbRp];
-        rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
+        rc = pThis->pCodec->pfnLookup(pThis->pCodec, cmd, &pfn);
         if (RT_FAILURE(rc))
             AssertRCReturn(rc, rc);
@@ -1010 +1031 @@
 
         if (RT_LIKELY(pfn))
-            rc = pfn(&pThis->Codec, cmd, &resp);
+            rc = pfn(pThis->pCodec, cmd, &resp);
         else
             rc = VERR_INVALID_FUNCTION;
@@ -1043 +1064 @@
     return rc;
 }
+#endif
 
 static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
@@ -1069 +1091 @@
 }
 
-
 /* Register access handlers. */
 
@@ -1151 +1172 @@
     else
     {
+#ifdef IN_RING3
         /* enter reset state*/
         if (   HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
@@ -1159 +1181 @@
                 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
         }
-        hdaReset(pThis->pDevIns);
+        hdaReset(pThis->CTX_SUFF(pDevIns));
         GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
         pThis->fInReset = true;
+#else
+        return VINF_IOM_R3_MMIO_WRITE;
+#endif
     }
     if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
@@ -1209 +1234 @@
 {
     /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
-    *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->pDevIns)
+    *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
                                                    - pThis->u64BaseTS, 24, 1000);
     return VINF_SUCCESS;
@@ -1232 +1257 @@
 static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
 {
+#ifdef IN_RING3
     int rc = hdaRegWriteU8(pThis, iReg, u32Value);
     AssertRC(rc);
@@ -1238 +1264 @@
         return hdaCORBCmdProcess(pThis);
     return rc;
+#else
+    return VINF_IOM_R3_MMIO_WRITE;
+#endif
 }
 
@@ -1249 +1278 @@
 static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
 {
+#ifdef IN_RING3
     int rc;
     rc = hdaRegWriteU16(pThis, iReg, u32Value);
@@ -1259 +1289 @@
     rc = hdaCORBCmdProcess(pThis);
     return rc;
+#else
+    return VINF_IOM_R3_MMIO_WRITE;
+#endif
 }
 
@@ -1284 +1317 @@
     else if (fReset)
     {
+#ifdef IN_RING3
         /*
          * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
@@ -1308 +1342 @@
         hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
         hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
+#else
+        return VINF_IOM_R3_MMIO_WRITE;
+#endif
     }
     else
     {
+#ifdef IN_RING3
         /* we enter here to change DMA states only */
         if (   (fInRun && !fRun)
@@ -1319 +1357 @@
             {
                 case ICH6_HDA_REG_SD0CTL:
-                    AUD_set_active_in(pThis->Codec.SwVoiceIn, fRun);
+                    AUD_set_active_in(pThis->pCodec->SwVoiceIn, fRun);
                     break;
                 case ICH6_HDA_REG_SD4CTL:
-                    AUD_set_active_out(pThis->Codec.SwVoiceOut, fRun);
+                    AUD_set_active_out(pThis->pCodec->SwVoiceOut, fRun);
                     break;
                 default:
@@ -1329 +1367 @@
             }
         }
+#else
+        return VINF_IOM_R3_MMIO_WRITE;
+#endif
     }
 
@@ -1406 +1447 @@
 }
 
+#ifdef IN_RING3
 static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
 {
@@ -1463 +1505 @@
 #undef EXTRACT_VALUE
 }
+#endif
 
 static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
 {
-#ifdef VBOX_WITH_HDA_CODEC_EMU
+#ifdef IN_RING3
+# ifdef VBOX_WITH_HDA_CODEC_EMU
     /** @todo a bit more investigation is required here. */
     int rc = 0;
@@ -1477 +1521 @@
     {
         case ICH6_HDA_REG_SD0FMT:
-            rc = hdaCodecOpenVoice(&pThis->Codec, PI_INDEX, &as);
+            rc = hdaCodecOpenVoice(pThis->pCodec, PI_INDEX, &as);
             break;
         case ICH6_HDA_REG_SD4FMT:
-            rc = hdaCodecOpenVoice(&pThis->Codec, PO_INDEX, &as);
+            rc = hdaCodecOpenVoice(pThis->pCodec, PO_INDEX, &as);
             break;
         default:
@@ -1487 +1531 @@
     }
     return hdaRegWriteU16(pThis, iReg, u32Value);
+# else
+    return hdaRegWriteU16(pThis, iReg, u32Value);
+# endif
 #else
-    return hdaRegWriteU16(pThis, iReg, u32Value);
+    return VINF_IOM_R3_MMIO_WRITE;
 #endif
 }
@@ -1523 +1570 @@
 {
     int                         rc  = VINF_SUCCESS;
-    PFNHDACODECVERBPROCESSOR    pfn = NULL;
-    uint64_t                    resp;
 
     /*
@@ -1533 +1578 @@
         && !IRS_ICB(pThis))
     {
+#ifdef IN_RING3
+        PFNHDACODECVERBPROCESSOR    pfn = NULL;
+        uint64_t                    resp;
         uint32_t cmd = IC(pThis);
         if (CORBWP(pThis) != CORBRP(pThis))
@@ -1544 +1592 @@
         IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB);  /* busy */
         Log(("hda: IC:%x\n", cmd));
-        rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
+        rc = pThis->pCodec->pfnLookup(pThis->pCodec, cmd, &pfn);
         if (RT_FAILURE(rc))
             AssertRCReturn(rc, rc);
-        rc = pfn(&pThis->Codec, cmd, &resp);
+        rc = pfn(pThis->pCodec, cmd, &resp);
         if (RT_FAILURE(rc))
             AssertRCReturn(rc, rc);
@@ -1554 +1602 @@
         IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV);  /* result is ready  */
         IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
+#else
+        rc = VINF_IOM_R3_MMIO_WRITE;
+#endif
         return rc;
     }
@@ -1622 +1673 @@
 }
 
+#ifdef IN_RING3
 #ifdef LOG_ENABLED
 static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
@@ -1636 +1688 @@
     for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
     {
-        PDMDevHlpPhysRead(pThis->pDevIns, u64BaseDMA + i*16, bdle, 16);
+        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
         addr = *(uint64_t *)bdle;
         len = *(uint32_t *)&bdle[8];
@@ -1646 +1698 @@
     for (i = 0; i < 8; ++i)
     {
-        PDMDevHlpPhysRead(pThis->pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
+        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
         Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": "   ",
              i , counter));
@@ -1660 +1712 @@
             && pBdle
             && pBdle->u32BdleMaxCvi));
-    PDMDevHlpPhysRead(pThis->pDevIns, pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
+    PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
     pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
     pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
@@ -1844 +1896 @@
          * read from backend input line to the last unreported position or at the begining.
          */
-        cbBackendCopy = AUD_read(pThis->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
+        cbBackendCopy = AUD_read(pThis->pCodec->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
         /*
          * write the HDA DMA buffer
          */
-        PDMDevHlpPCIPhysWrite(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
+        PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
 
         /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
@@ -1886 +1938 @@
     else
     {
-        PDMDevHlpPhysRead(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
+        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
         /*
          * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
@@ -1895 +1947 @@
              * Feed the newly fetched samples, including unreported ones, to the backend.
              */
-            cbBackendCopy = AUD_write (pThis->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
+            cbBackendCopy = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
             hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
         }
@@ -2017 +2069 @@
     }
 }
-
+#endif
 
 /* MMIO callbacks */
@@ -2272 +2324 @@
                 cbReg = 1;
             }
+            if (rc != VINF_SUCCESS)
+                break;
             if (cbReg >= cb)
                 break;
@@ -2351 +2405 @@
 /* PCI callback. */
 
+#ifdef IN_RING3
 /**
  * @callback_method_impl{FNPCIIOREGIONMAP}
@@ -2369 +2424 @@
      */
     Assert(enmType == PCI_ADDRESS_SPACE_MEM);
-    rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
+    rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
 #ifdef NEW_READ_CODE
                                IOMMMIO_FLAGS_READ_DWORD |
@@ -2381 +2436 @@
         return rc;
 
+    if (pThis->fR0Enabled)
+    {
+        rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
+                                     "hdaMMIOWrite", "hdaMMIORead");
+        if (RT_FAILURE(rc))
+            return rc;
+    }
+
+    if (pThis->fRCEnabled)
+    {
+        rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
+                                     "hdaMMIOWrite", "hdaMMIORead");
+        if (RT_FAILURE(rc))
+            return rc;
+    }
+
     pThis->MMIOBaseAddr = GCPhysAddress;
     return VINF_SUCCESS;
@@ -2395 +2466 @@
     PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
     /* Save Codec nodes states */
-    hdaCodecSaveState(&pThis->Codec, pSSM);
+    hdaCodecSaveState(pThis->pCodec, pSSM);
 
     /* Save MMIO registers */
@@ -2422 +2493 @@
      * Load Codec nodes states.
      */
-    int rc = hdaCodecLoadState(&pThis->Codec, pSSM, uVersion);
+    int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
     if (RT_FAILURE(rc))
         return rc;
@@ -2488 +2559 @@
      * Update stuff after the state changes.
      */
-    AUD_set_active_in(pThis->Codec.SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
-    AUD_set_active_out(pThis->Codec.SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
+    AUD_set_active_in(pThis->pCodec->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
+    AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
 
     pThis->u64CORBBase = RT_MAKE_U64(CORBLBASE(pThis), CORBUBASE(pThis));
@@ -2664 +2735 @@
 {
     PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
-    if (pThis->Codec.pfnCodecDbgListNodes)
-        pThis->Codec.pfnCodecDbgListNodes(&pThis->Codec, pHlp, pszArgs);
+    if (pThis->pCodec->pfnCodecDbgListNodes)
+        pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
     else
         pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
@@ -2677 +2748 @@
 {
     PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
-    if (pThis->Codec.pfnCodecDbgSelector)
-        pThis->Codec.pfnCodecDbgSelector(&pThis->Codec, pHlp, pszArgs);
+    if (pThis->pCodec->pfnCodecDbgSelector)
+        pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
     else
         pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
@@ -2774 +2845 @@
     PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
 
-    int rc = hdaCodecDestruct(&pThis->Codec);
-    AssertRC(rc);
+    if (pThis->pCodec)
+    {
+        int rc = hdaCodecDestruct(pThis->pCodec);
+        AssertRC(rc);
+
+        RTMemFree(pThis->pCodec);
+        pThis->pCodec = NULL;
+    }
 
     RTMemFree(pThis->pu32CorbBuf);
@@ -2800 +2877 @@
      * Validations.
      */
-    if (!CFGMR3AreValuesValid(pCfgHandle, "\0"))
+    if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
+                                          "RCEnabled\0"))
         return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
                                 N_ ("Invalid configuration for the Intel HDA device"));
 
-    /// @todo r=michaln: This device may need R0/RC enabling, especially if guests
-    /// poll some register(pThis).
+    rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("HDA configuration error: failed to read RCEnabled as boolean"));
+    rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("HDA configuration error: failed to read R0Enabled as boolean"));
 
     /*
      * Initialize data (most of it anyway).
      */
-    pThis->pDevIns                  = pDevIns;
+    pThis->pDevInsR3                = pDevIns;
+    pThis->pDevInsR0                = PDMDEVINS_2_R0PTR(pDevIns);
+    pThis->pDevInsRC                = PDMDEVINS_2_RCPTR(pDevIns);
     /* IBase */
     pThis->IBase.pfnQueryInterface  = hdaQueryInterface;
@@ -2816 +2902 @@
     /* PCI Device */
     PCIDevSetVendorId           (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
-    PCIDevSetDeviceId           (&pThis->PciDev, HDA_PCI_DEICE_ID); /* HDA */
+    PCIDevSetDeviceId           (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
 
     PCIDevSetCommand            (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
@@ -2932 +3018 @@
     }
 
-    pThis->Codec.pvHDAState = pThis;
-    rc = hdaCodecConstruct(pDevIns, &pThis->Codec, pCfgHandle);
+    /* Construct codec state. */
+    pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
+    if (!pThis->pCodec)
+        return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("HDA: Out of memory allocating codec state"));
+
+    pThis->pCodec->pvHDAState = pThis;
+    rc = hdaCodecConstruct(pDevIns, pThis->pCodec, pCfgHandle);
     if (RT_FAILURE(rc))
         AssertRCReturn(rc, rc);
@@ -2939 +3030 @@
     /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
        verb F20 should provide device/codec recognition. */
-    Assert(pThis->Codec.u16VendorId);
-    Assert(pThis->Codec.u16DeviceId);
-    PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->Codec.u16VendorId); /* 2c ro - intel.) */
-    PCIDevSetSubSystemId(      &pThis->PciDev, pThis->Codec.u16DeviceId); /* 2e ro. */
+    Assert(pThis->pCodec->u16VendorId);
+    Assert(pThis->pCodec->u16DeviceId);
+    PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
+    PCIDevSetSubSystemId(      &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
 
     hdaReset(pDevIns);
-    pThis->Codec.id = 0;
-    pThis->Codec.pfnTransfer = hdaTransfer;
-    pThis->Codec.pfnReset = hdaCodecReset;
+    pThis->pCodec->id = 0;
+    pThis->pCodec->pfnTransfer = hdaTransfer;
+    pThis->pCodec->pfnReset = hdaCodecReset;
 
     /*
@@ -3037 +3128 @@
     "hda",
     /* szRCMod */
-    "",
+    "VBoxDDGC.gc",
     /* szR0Mod */
-    "",
+    "VBoxDDR0.r0",
     /* pszDescription */
     "Intel HD Audio Controller",
     /* fFlags */
-    PDM_DEVREG_FLAGS_DEFAULT_BITS,
+    PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
     /* fClass */
     PDM_DEVREG_CLASS_AUDIO,
@@ -3081 +3172 @@
     PDM_DEVREG_VERSION
 };
+
+#endif /* IN_RING3 */
+#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */