- Timestamp:
- Jun 12, 2013 2:56:47 PM (12 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r46507 r46510 5881 5881 AssertRC(rc); 5882 5882 5883 /* Restore FPU state if necessary and resync on next R0 reentry .*/5883 /* Restore host FPU state if necessary and resync on next R0 reentry .*/ 5884 5884 if (CPUMIsGuestFPUStateActive(pVCpu)) 5885 5885 { … … 5889 5889 } 5890 5890 5891 /* Restore debug registers if necessary and resync on next R0 reentry. */5891 /* Restore host debug registers if necessary and resync on next R0 reentry. */ 5892 5892 if (CPUMIsGuestDebugStateActive(pVCpu)) 5893 5893 { … … 5985 5985 5986 5986 /** 5987 * VMMRZCallRing3callback wrapper which saves the guest state before we5988 * 5987 * VMMRZCallRing3() callback wrapper which saves the guest state before we 5988 * longjump to ring-3 and possibly get preempted. 5989 5989 * 5990 5990 * @param pVCpu Pointer to the VMCPU. … … 5998 5998 DECLCALLBACK(void) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser) 5999 5999 { 6000 /* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion ,*/6000 /* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion. */ 6001 6001 Assert(pVCpu); 6002 6002 Assert(pvUser); … … 7160 7160 #ifdef DEBUG 7161 7161 /* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */ 7162 # define VMX_ASSERT_PREEMPT_CPUID_VAR() \7162 # define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \ 7163 7163 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId() 7164 # define VMX_ASSERT_PREEMPT_CPUID() \ 7164 7165 # define HMVMX_ASSERT_PREEMPT_CPUID() \ 7165 7166 do \ 7166 7167 { \ … … 7169 7170 } while (0) 7170 7171 7171 # define VMX_VALIDATE_EXIT_HANDLER_PARAMS() \ 7172 do { \ 7173 AssertPtr(pVCpu); \ 7174 AssertPtr(pMixedCtx); \ 7175 AssertPtr(pVmxTransient); \ 7176 Assert(pVmxTransient->fVMEntryFailed == false); \ 7177 Assert(ASMIntAreEnabled()); \ 7178 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \ 7179 VMX_ASSERT_PREEMPT_CPUID_VAR(); \ 7180 Log4Func(("vcpu[%u] vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv\n", \ 7181 (unsigned)pVCpu->idCpu)); \ 7182 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \ 7183 if (VMMR0IsLogFlushDisabled(pVCpu)) \ 7184 VMX_ASSERT_PREEMPT_CPUID(); \ 7185 HMVMX_STOP_EXIT_DISPATCH_PROF(); \ 7172 # define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \ 7173 do { \ 7174 AssertPtr(pVCpu); \ 7175 AssertPtr(pMixedCtx); \ 7176 AssertPtr(pVmxTransient); \ 7177 Assert(pVmxTransient->fVMEntryFailed == false); \ 7178 Assert(ASMIntAreEnabled()); \ 7179 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \ 7180 HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \ 7181 Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \ 7182 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \ 7183 if (VMMR0IsLogFlushDisabled(pVCpu)) \ 7184 HMVMX_ASSERT_PREEMPT_CPUID(); \ 7185 HMVMX_STOP_EXIT_DISPATCH_PROF(); \ 7186 7186 } while (0) 7187 # define VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() \ 7188 do { \ 7189 Log4Func(("\n")); \ 7187 7188 # define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() \ 7189 do { \ 7190 Log4Func(("\n")); \ 7190 7191 } while(0) 7191 7192 #else /* Release builds */ 7192 # define VMX_VALIDATE_EXIT_HANDLER_PARAMS() do { HMVMX_STOP_EXIT_DISPATCH_PROF(); } while(0)7193 # define VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() do { } while(0)7193 # define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() do { HMVMX_STOP_EXIT_DISPATCH_PROF(); } while(0) 7194 # define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() do { } while(0) 7194 7195 #endif 7195 7196 … … 7227 7228 HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7228 7229 { 7229 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7230 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7230 7231 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt); 7231 7232 /* 32-bit Windows hosts (4 cores) has trouble with this; causes higher interrupt latency. */ … … 7244 7245 HMVMX_EXIT_DECL hmR0VmxExitXcptNmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7245 7246 { 7246 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7247 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7247 7248 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3); 7248 7249 … … 7349 7350 HMVMX_EXIT_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7350 7351 { 7351 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7352 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7352 7353 7353 7354 /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */ … … 7368 7369 HMVMX_EXIT_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7369 7370 { 7370 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7371 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7371 7372 AssertMsgFailed(("Unexpected NMI-window exit.\n")); 7372 7373 return VERR_VMX_UNEXPECTED_EXIT_CODE; … … 7379 7380 HMVMX_EXIT_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7380 7381 { 7381 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7382 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7382 7383 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd); 7383 7384 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient); … … 7390 7391 HMVMX_EXIT_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7391 7392 { 7392 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7393 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7393 7394 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd); 7394 7395 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient); … … 7401 7402 HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7402 7403 { 7403 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7404 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7404 7405 PVM pVM = pVCpu->CTX_SUFF(pVM); 7405 7406 int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx)); … … 7424 7425 HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7425 7426 { 7426 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7427 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7427 7428 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx); 7428 7429 AssertRCReturn(rc, rc); … … 7441 7442 HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7442 7443 { 7443 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7444 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7444 7445 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx); /** @todo review if CR4 is really required by EM. */ 7445 7446 AssertRCReturn(rc, rc); … … 7470 7471 HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7471 7472 { 7472 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7473 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7473 7474 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx); /** @todo review if CR4 is really required by EM. */ 7474 7475 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx); /* For MSR_K8_TSC_AUX */ … … 7500 7501 HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7501 7502 { 7502 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7503 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7503 7504 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx); /** @todo review if CR4 is really required by EM. */ 7504 7505 rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); /** @todo review if CR0 is really required by EM. */ … … 7527 7528 HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7528 7529 { 7529 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7530 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7530 7531 PVM pVM = pVCpu->CTX_SUFF(pVM); 7531 7532 Assert(!pVM->hm.s.fNestedPaging); … … 7554 7555 HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7555 7556 { 7556 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7557 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7557 7558 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); 7558 7559 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); … … 7579 7580 HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7580 7581 { 7581 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7582 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7582 7583 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); 7583 7584 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); … … 7680 7681 * still get these exits. See Intel spec. "23.8 Restrictions on VMX operation". 7681 7682 */ 7682 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7683 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7683 7684 return VINF_SUCCESS; /** @todo r=ramshankar: correct?. */ 7684 7685 } … … 7691 7692 HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7692 7693 { 7693 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7694 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7694 7695 return VINF_EM_RESET; 7695 7696 } … … 7701 7702 HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7702 7703 { 7703 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7704 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7704 7705 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT); 7705 7706 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx); … … 7724 7725 HMVMX_EXIT_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7725 7726 { 7726 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7727 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7727 7728 hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx); 7728 7729 return VINF_SUCCESS; … … 7735 7736 HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7736 7737 { 7737 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7738 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7738 7739 7739 7740 /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */ … … 7753 7754 HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7754 7755 { 7755 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7756 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7756 7757 7757 7758 /* We expose XSETBV to the guest, fallback to the recompiler for emulation. */ … … 7766 7767 HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7767 7768 { 7768 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7769 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7769 7770 7770 7771 /* The guest should not invalidate the host CPU's TLBs, fallback to recompiler. */ … … 7857 7858 HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7858 7859 { 7859 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7860 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7860 7861 7861 7862 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */ … … 7873 7874 HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7874 7875 { 7875 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7876 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7876 7877 7877 7878 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */ … … 7889 7890 HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7890 7891 { 7891 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7892 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7892 7893 7893 7894 /* EMInterpretRdmsr() requires CR0, Eflags and SS segment register. */ … … 7917 7918 HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 7918 7919 { 7919 VMX_VALIDATE_EXIT_HANDLER_PARAMS();7920 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 7920 7921 PVM pVM = pVCpu->CTX_SUFF(pVM); 7921 7922 int rc = VINF_SUCCESS; … … 8021 8022 HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8022 8023 { 8023 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8024 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8024 8025 8025 8026 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT. */ … … 8038 8039 HMVMX_EXIT_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8039 8040 { 8040 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8041 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8041 8042 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW); 8042 8043 … … 8064 8065 HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8065 8066 { 8066 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8067 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8067 8068 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2); 8068 8069 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient); … … 8196 8197 HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8197 8198 { 8198 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8199 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8199 8200 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1); 8200 8201 … … 8368 8369 HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8369 8370 { 8370 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8371 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8371 8372 8372 8373 /* Check if this task-switch occurred while delivery an event through the guest IDT. */ … … 8422 8423 HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8423 8424 { 8424 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8425 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8425 8426 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG); 8426 8427 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG; … … 8437 8438 HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8438 8439 { 8439 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8440 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8440 8441 8441 8442 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */ … … 8512 8513 HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8513 8514 { 8514 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8515 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8515 8516 8516 8517 /* We should -not- get this VM-exit if the guest is debugging. */ … … 8590 8591 HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8591 8592 { 8592 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8593 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8593 8594 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging); 8594 8595 … … 8642 8643 HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8643 8644 { 8644 VMX_VALIDATE_EXIT_HANDLER_PARAMS();8645 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(); 8645 8646 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging); 8646 8647 … … 8711 8712 static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8712 8713 { 8713 VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();8714 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(); 8714 8715 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); 8715 8716 … … 8734 8735 static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8735 8736 { 8736 VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();8737 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(); 8737 8738 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); 8738 8739 … … 8765 8766 static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8766 8767 { 8767 VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();8768 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(); 8768 8769 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); 8769 8770 … … 8817 8818 static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8818 8819 { 8819 VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();8820 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(); 8820 8821 8821 8822 #ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS … … 8856 8857 static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 8857 8858 { 8858 VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();8859 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(); 8859 8860 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); 8860 8861 … … 9101 9102 static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 9102 9103 { 9103 VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();9104 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(); 9104 9105 9105 9106 /* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in … … 9120 9121 static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) 9121 9122 { 9122 VMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();9123 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(); 9123 9124 PVM pVM = pVCpu->CTX_SUFF(pVM); 9124 9125 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
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