Changeset 46594 in vbox for trunk

Timestamp:

Jun 17, 2013 2:35:56 PM (12 years ago)

Author:

vboxsync

Message:

VMM/HMSVMR0: AMD-V bits.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (11 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -101 +101 @@
 #define HMSVM_VMCB_CLEAN_NP                     RT_BIT(4)
 /** Control registers (CR0, CR3, CR4, EFER). */
-#define HMSVM_VMCB_CLEAN_CRX                    RT_BIT(5)
+#define HMSVM_VMCB_CLEAN_CRX_EFER               RT_BIT(5)
 /** Debug registers (DR6, DR7). */
 #define HMSVM_VMCB_CLEAN_DRX                    RT_BIT(6)
@@ -955 +955 @@
 
         pVmcb->guest.u64CR0 = u64GuestCR0;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX;
+        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
         pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
     }
@@ -992 +992 @@
             pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
 
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX;
+        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
         pVCpu->hm.s.fContextUseFlags &= HM_CHANGED_GUEST_CR3;
     }
@@ -1037 +1037 @@
 
         pVmcb->guest.u64CR4 = u64GuestCR4;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX;
+        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
         pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
     }
@@ -1126 +1126 @@
      * See AMD spec. 15.5.1 "Basic Operation" | "Canonicalization and Consistency Checks".
      */
-    pVmcb->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
+    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR
+    {
+        pVmcb->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
+        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
+    }
 
     /* 64-bit MSRs. */
@@ -1137 +1142 @@
     {
         /* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
-        pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
-    }
+        if (pCtx->msrEFER & MSR_K6_EFER_LME)
+        {
+            pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
+            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+        }
+    }
+
 
     /** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
@@ -2885 +2895 @@
 static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
 {
-    int rc;
     Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
-
     for (;;)
     {
@@ -2900 +2908 @@
         {
             case HMTPRINSTR_READ:
-                rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
+            {
+                int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
                 AssertRC(rc);
 
@@ -2907 +2916 @@
                 pCtx->rip += pPatch->cbOp;
                 break;
+            }
 
             case HMTPRINSTR_WRITE_REG:
             case HMTPRINSTR_WRITE_IMM:
+            {
                 if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
                 {
                     uint32_t u32Val;
-                    rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
+                    int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
                     AssertRC(rc);
                     u8Tpr = u32Val;
@@ -2920 +2931 @@
                     u8Tpr = (uint8_t)pPatch->uSrcOperand;
 
-                rc = PDMApicSetTPR(pVCpu, u8Tpr);
-                AssertRC(rc);
+                int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
+                AssertRC(rc2);
                 pCtx->rip += pPatch->cbOp;
                 break;
+            }
 
             default:
@@ -3247 +3259 @@
         rc = EMInterpretWrmsr(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
         AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
+
+        if (pCtx->ecx == MSR_K6_EFER)
+            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_EFER_MSR;
     }
     else