- Timestamp:
- Jun 20, 2013 4:37:26 PM (12 years ago)
- svn:sync-xref-src-repo-rev:
- 86629
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r46707 r46713 3315 3315 { 3316 3316 /* Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */ 3317 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR0);3318 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS);3319 3320 3317 /* NOTE: The reason we check for attribute value 0 and not just the unusable bit here is because hmR0VmxWriteSegmentReg() 3321 3318 * only updates the VMCS bits with the unusable bit and doesn't change the guest-context value. */ … … 5588 5585 else 5589 5586 Assert(VMMR0IsLogFlushDisabled(pVCpu)); 5590 Log4Func((" \n"));5587 Log4Func(("vcpu[%RU32]\n", pVCpu->idCpu)); 5591 5588 5592 5589 int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx); … … 7938 7935 && pMixedCtx->ecx <= MSR_IA32_X2APIC_END) 7939 7936 { 7940 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_APIC_STATE); 7937 /* We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register 7938 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before 7939 EMInterpretWrmsr() changes it. */ 7941 7940 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE; 7942 7941 }
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