Changeset 46827 in vbox for trunk/src/VBox/VMM

Timestamp:

Jun 27, 2013 11:18:49 AM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

86773

Message:

VMM/HMSVMR0: AMD-V bits.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (8 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -670 +670 @@
         pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
 
-        /* Ignore the priority in the TPR; we take into account the guest TPR anyway while delivering interrupts. */
+        /* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
+           deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
         pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR   = 1;
 
@@ -680 +681 @@
         pVmcb->ctrl.u64LBRVirt = 0;
 
-        /* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from memory. */
+        /* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
         pVmcb->ctrl.u64VmcbCleanBits = 0;
 
-        /* The guest ASID MBNZ, set it to 1. The host uses 0. */
+        /* The host ASID MBZ, for the guest start with 1. */
         pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
 
@@ -2155 +2156 @@
         pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
 
-        Log4(("Setting virtual interrupt intercept\n"));
+        Log4(("Setting virtual interrupt pending intercept\n"));
     }
 }
@@ -2172 +2173 @@
 
     const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
+    const bool fBlockInt  = !(pCtx->eflags.u32 & X86_EFL_IF);
     PSVMVMCB pVmcb        = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
 
@@ -2181 +2183 @@
         Assert(Event.n.u1Valid);
         bool fInject = true;
-        if (   fIntShadow
-            && (   Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
-                || Event.n.u3Type == SVM_EVENT_NMI))
+        if (   Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
+            && (   fBlockInt
+                || fIntShadow))
+        {
+            fInject = false;
+        }
+        else if (   Event.n.u3Type == SVM_EVENT_NMI
+                 && fIntShadow)
         {
             fInject = false;
@@ -2195 +2202 @@
         else
             hmR0SvmSetVirtIntrIntercept(pVmcb);
-    }                                                          /** @todo SMI. SMIs take priority over NMIs. */
+    }                                                              /** @todo SMI. SMIs take priority over NMIs. */
     else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))   /* NMI. NMIs take priority over regular interrupts . */
     {
@@ -2215 +2222 @@
     {
         /* Check if there are guest external interrupts (PIC/APIC) pending and inject them, if the guest can receive them. */
-        const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
         if (   !fBlockInt
             && !fIntShadow)
@@ -2591 +2597 @@
         || HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
     {
+        hmR0SvmUpdateTscOffsetting(pVCpu);
         pSvmTransient->fUpdateTscOffsetting = false;
-        hmR0SvmUpdateTscOffsetting(pVCpu);
     }