Changeset 46871 in vbox
- Timestamp:
- Jun 28, 2013 4:25:06 PM (12 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r46869 r46871 1691 1691 1692 1692 /* 1693 * Correct the hidden CS granularity flag. Haven't seen it being wrong in any other1693 * Correct the hidden CS granularity bit. Haven't seen it being wrong in any other 1694 1694 * register (yet). 1695 1695 */ 1696 /** @todo Verify this. */ 1696 /** @todo SELM might need to be fixed as it too should not care about the 1697 * granularity bit. See @bugref{6785}. */ 1697 1698 if ( !pMixedCtx->cs.Attr.n.u1Granularity 1698 1699 && pMixedCtx->cs.Attr.n.u1Present … … 1702 1703 pMixedCtx->cs.Attr.n.u1Granularity = 1; 1703 1704 } 1705 1704 1706 #ifdef VBOX_STRICT 1705 1707 # define HMSVM_ASSERT_SEG_GRANULARITY(reg) \ … … 1708 1710 ? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \ 1709 1711 : pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \ 1710 ("Invalid Segment Attributes %#x %#x %#llx\n", pMixedCtx->reg.u32Limit, \1712 ("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \ 1711 1713 pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base)) 1712 1714 … … 1945 1947 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a 1946 1948 * page-fault. 1949 * 1950 * @remarks Statistics counter assumes this is a guest event being reflected to 1951 * the guest i.e. 'StatInjectPendingReflect' is incremented always. 1947 1952 */ 1948 1953 DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress) … … 1957 1962 Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, 1958 1963 pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode)); 1964 1965 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect); 1959 1966 } 1960 1967 … … 2045 2052 Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector, 2046 2053 !!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode)); 2054 2047 2055 hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress); 2056 STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect); 2048 2057 } 2049 2058 … … 2203 2212 hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event); 2204 2213 pVCpu->hm.s.Event.fPending = false; 2205 STAM_COUNTER_INC(&pVCpu->hm.s.StatIntReinject); 2214 2215 #ifdef VBOX_WITH_STATISTICS 2216 if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ) 2217 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt); 2218 else 2219 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 2220 #endif 2206 2221 } 2207 2222 else … … 2220 2235 hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event); 2221 2236 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI); 2237 2238 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 2222 2239 } 2223 2240 else … … 2241 2258 2242 2259 hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event); 2243 STAM_COUNTER_INC(&pVCpu->hm.s.StatIn tInject);2260 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt); 2244 2261 } 2245 2262 else … … 2976 2993 * next instruction. */ 2977 2994 /** @todo Investigate this later. */ 2995 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); 2978 2996 break; 2979 2997 … … 3138 3156 3139 3157 /** 3140 * Sets a ndebug (#DB) exception as pending-for-injection into the VM.3158 * Sets a debug (#DB) exception as pending-for-injection into the VM. 3141 3159 * 3142 3160 * @param pVCpu Pointer to the VMCPU. … … 3367 3385 { 3368 3386 uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0); 3387 3388 #ifdef VBOX_STRICT 3389 if ( hmR0SvmIsContributoryXcpt(uIdtVector) 3390 && uExitVector == X86_XCPT_PF) 3391 { 3392 Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2)); 3393 } 3394 #endif 3369 3395 if ( uExitVector == X86_XCPT_PF 3370 3396 && uIdtVector == X86_XCPT_PF) … … 3415 3441 pVCpu->hm.s.Event.fPending = true; 3416 3442 3443 hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */); 3444 3417 3445 /* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */ 3418 3446 Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u, … … 4298 4326 else if (rc == VINF_EM_RAW_GUEST_TRAP) 4299 4327 { 4328 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */ 4329 4300 4330 if (!pSvmTransient->fVectoringPF) 4301 4331 { … … 4303 4333 u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */ 4304 4334 TRPMResetTrap(pVCpu); 4305 4306 4335 hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress); 4307 4336 } … … 4310 4339 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */ 4311 4340 TRPMResetTrap(pVCpu); 4312 pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */4313 4341 hmR0SvmSetPendingXcptDF(pVCpu); 4314 4342 Log4(("#PF: Pending #DF due to vectoring #PF\n")); … … 4367 4395 HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(); 4368 4396 4397 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); 4398 4369 4399 int rc; 4370 4400 if (!(pCtx->cr0 & X86_CR0_NE)) … … 4372 4402 /* Old-style FPU error reporting needs some extra work. */ 4373 4403 /** @todo don't fall back to the recompiler, but do it manually. */ 4374 rc = VERR_EM_INTERPRETER; 4375 } 4376 else 4377 { 4378 hmR0SvmSetPendingXcptMF(pVCpu); 4379 rc = VINF_SUCCESS; 4380 } 4381 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); 4382 return rc; 4404 return VERR_EM_INTERPRETER; 4405 } 4406 4407 hmR0SvmSetPendingXcptMF(pVCpu); 4408 return VINF_SUCCESS; 4383 4409 } 4384 4410 … … 4403 4429 { 4404 4430 /* Reflect the exception back to the guest. */ 4405 SVMEVENT Event; 4406 Event.u = 0; 4407 Event.n.u1Valid = 1; 4408 Event.n.u3Type = SVM_EVENT_EXCEPTION; 4409 Event.n.u8Vector = X86_XCPT_DB; 4410 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */); 4411 4431 hmR0SvmSetPendingXcptDB(pVCpu); 4412 4432 rc = VINF_SUCCESS; 4413 4433 } -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r46850 r46871 4711 4711 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a 4712 4712 * page-fault. 4713 * 4714 * @remarks Statistics counter assumes this is a guest event being injected or 4715 * re-injected into the guest, i.e. 'StatInjectPendingReflect' is 4716 * always incremented. 4713 4717 */ 4714 4718 DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntrInfo, uint32_t cbInstr, uint32_t u32ErrCode, … … 4721 4725 pVCpu->hm.s.Event.cbInstr = cbInstr; 4722 4726 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress; 4727 4728 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect); 4723 4729 } 4724 4730 … … 4858 4864 Log4(("IDT: vcpu[%RU32] Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->idCpu, 4859 4865 pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.u32ErrCode)); 4866 4860 4867 break; 4861 4868 } … … 4867 4874 Log4(("IDT: vcpu[%RU32] Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->idCpu, 4868 4875 pVCpu->hm.s.Event.u64IntrInfo, uIdtVector, uExitVector)); 4876 4869 4877 break; 4870 4878 } … … 5798 5806 Log4(("TRPM->HM event: u32IntrInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n", 5799 5807 u32IntrInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress)); 5808 5800 5809 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, cbInstr, uErrCode, GCPtrFaultAddress); 5810 STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect); 5801 5811 } 5802 5812 … … 6096 6106 AssertRCReturn(rc, rc); 6097 6107 pVCpu->hm.s.Event.fPending = false; 6098 STAM_COUNTER_INC(&pVCpu->hm.s.StatIntReinject); 6108 6109 #ifdef VBOX_WITH_STATISTICS 6110 if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT) 6111 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt); 6112 else 6113 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 6114 #endif 6099 6115 } 6100 6116 else … … 6114 6130 AssertRCReturn(rc, rc); 6115 6131 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI); 6132 6133 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 6116 6134 } 6117 6135 else … … 6137 6155 rc = hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntrInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 6138 6156 0 /* GCPtrFaultAddress */, &uIntrState); 6139 STAM_COUNTER_INC(&pVCpu->hm.s.StatIntInject); 6157 6158 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt); 6140 6159 } 6141 6160 else … … 8717 8736 return VERR_EM_INTERPRETER; 8718 8737 } 8738 8719 8739 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo), 8720 8740 pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode, 0 /* GCPtrFaultAddress */); -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r46850 r46871 593 593 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.u32ErrCode, 594 594 (RTGCPTR)pCtx->rip)); 595 STAM_COUNTER_INC(&pVCpu->hm.s.StatIn tReinject);595 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect); 596 596 Event.u = pVCpu->hm.s.Event.u64IntrInfo; 597 597 hmR0SvmInjectEvent(pVCpu, pVmcb, pCtx, &Event); … … 617 617 618 618 hmR0SvmInjectEvent(pVCpu, pVmcb, pCtx, &Event); 619 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 619 620 return VINF_SUCCESS; 620 621 } … … 725 726 else 726 727 Event.n.u3Type = SVM_EVENT_EXCEPTION; 728 729 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 727 730 } 728 731 else 732 { 729 733 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ; 730 731 STAM_COUNTER_INC(&pVCpu->hm.s.StatIntInject); 734 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt); 735 } 736 732 737 hmR0SvmInjectEvent(pVCpu, pVmcb, pCtx, &Event); 733 738 } /* if (interrupts can be dispatched) */ … … 2224 2229 goto ResumeExecution; 2225 2230 2231 case SVM_EXIT_INTR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt); /* no break */ 2226 2232 case SVM_EXIT_FERR_FREEZE: 2227 case SVM_EXIT_INTR:2228 2233 case SVM_EXIT_NMI: 2229 2234 case SVM_EXIT_SMI: … … 2806 2811 if (exitCode == SVM_EXIT_INTR) 2807 2812 { 2808 STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);2809 2813 /* On the next entry we'll only sync the host context. */ 2810 2814 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_HOST_CONTEXT; -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r46724 r46871 1095 1095 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntrInfo, 1096 1096 pVCpu->hm.s.Event.u32ErrCode, (RTGCPTR)pCtx->rip, pCtx->cr2)); 1097 STAM_COUNTER_INC(&pVCpu->hm.s.StatIn tReinject);1097 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect); 1098 1098 rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, pVCpu->hm.s.Event.u64IntrInfo, 0, pVCpu->hm.s.Event.u32ErrCode); 1099 1099 AssertRC(rc); … … 1121 1121 AssertRC(rc); 1122 1122 1123 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 1123 1124 return VINF_SUCCESS; 1124 1125 } … … 1233 1234 else 1234 1235 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); 1236 1237 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt); 1235 1238 } 1236 1239 else 1240 { 1237 1241 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); 1238 1239 STAM_COUNTER_INC(&pVCpu->hm.s.StatIntInject); 1242 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt); 1243 } 1244 1240 1245 rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode); 1241 1246 AssertRC(rc); … … 5015 5020 && !VMX_EXIT_INTERRUPTION_INFO_IS_VALID(intInfo)) 5016 5021 { 5017 STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);5018 5022 /* On the next entry we'll only sync the host context. */ 5019 5023 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_HOST_CONTEXT; -
trunk/src/VBox/VMM/VMMR3/HM.cpp
r46842 r46871 222 222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."), 223 223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."), 224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt ."),225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt ."),226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt ."),227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal ."),224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."), 225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."), 226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."), 227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."), 228 228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."), 229 229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."), … … 689 689 690 690 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!."); 691 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code."); 691 692 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc."); 692 693 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total)."); 693 694 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3."); 694 695 695 HM_REG_COUNTER(&pVCpu->hm.s.StatIn tInject, "/HM/CPU%d/Irq/Inject", "Injecting hardwareinterrupt into the guest.");696 HM_REG_COUNTER(&pVCpu->hm.s.StatIn tReinject, "/HM/CPU%d/Irq/Reinject", "Re-injecting an eventinto the guest.");697 HM_REG_COUNTER(&pVCpu->hm.s.Stat PendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost", "Exiting to ring-3 due to preemption pending on the host.");696 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest."); 697 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest."); 698 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest."); 698 699 699 700 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs."); … … 720 721 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint."); 721 722 722 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading just RIP (+RSP, RFLAGs for old VT-x code).");723 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading more of thestate.");723 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state."); 724 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state."); 724 725 725 726 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base."); 726 727 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit."); 727 728 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK."); 728 729 729 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector."); 730 730 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL."); … … 791 791 { 792 792 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, 793 " Forwarded interrupts.",794 (j < 0x20) ? "/HM/CPU%d/ Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);793 "Injected event.", 794 (j < 0x20) ? "/HM/CPU%d/EventInject/Event/Trap/%02X" : "/HM/CPU%d/EventInject/Event/IRQ/%02X", i, j); 795 795 } 796 796 -
trunk/src/VBox/VMM/include/HMInternal.h
r46849 r46871 792 792 STAMPROFILEADV StatSpinPokeFailed; 793 793 794 STAMCOUNTER StatIntInject; 794 STAMCOUNTER StatInjectInterrupt; 795 STAMCOUNTER StatInjectXcpt; 796 STAMCOUNTER StatInjectPendingReflect; 795 797 796 798 STAMCOUNTER StatExitShadowNM; … … 848 850 STAMCOUNTER StatExitMtf; 849 851 STAMCOUNTER StatExitApicAccess; 850 STAMCOUNTER StatIntReinject;851 852 STAMCOUNTER StatPendingHostIrq; 852 853
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