Changeset 46925 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Jul 3, 2013 11:16:39 AM (12 years ago)

Author:

vboxsync

Message:

VMM: Optimized world-switch with lazy restoration LDTR and TR on Intel.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMR0A.asm (modified) (1 diff)
• HMR0Mixed.mac (modified) (10 diffs)
• HMVMXR0.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR0/HMR0A.asm

@@ -318 +318 @@
 .test_es:
     test        edi, VMX_RESTORE_HOST_SEL_ES
-    jz          near .test_fs
+    jz          near .test_ldtr
     mov         ax, word [rsi + VMXRESTOREHOST.uHostSelES]
     mov         es, ax
+
+.test_ldtr:
+    test        edi, VMX_RESTORE_HOST_SEL_LDTR
+    jz          near .test_tr
+    mov         ax, word [rsi + VMXRESTOREHOST.uHostSelLDTR]
+    lldt        ax
+
+.test_tr:
+    test        edi, VMX_RESTORE_HOST_SEL_TR
+    jz          near .test_fs
+    mov         dx, word [rsi + VMXRESTOREHOST.uHostSelTR]
+    xor         xAX, xAX
+    mov         ax, dx
+    and         al, X86_SEL_MASK                                  ; Mask away TI and RPL bits leaving only the descriptor offset.
+    add         xAX, qword [rsi + VMXRESTOREHOST.HostGdtr + 2]    ; xAX <- descriptor offset + GDTR.pGdt.
+    and         dword [ss:xAX + 4], ~RT_BIT(9)                    ; Clear the busy flag in TSS (bits 0-7=base, bit 9=busy bit).
+    ltr         dx
 
 .test_fs:

trunk/src/VBox/VMM/VMMR0/HMR0Mixed.mac

@@ -21 +21 @@
  %ifdef RT_ARCH_AMD64
   %define VMX_SKIP_GDTR_IDTR
+  %define VMX_SKIP_LDTR_TR
  %endif
 %endif
@@ -111 +112 @@
     push    xSI
 
+%ifndef VMX_SKIP_LDTR_TR
     ; Save LDTR.
     xor     eax, eax
@@ -119 +121 @@
     str     eax
     push    xAX
-
+%endif
+
+%ifndef VMX_SKIP_GDTR_IDTR
     ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
-%ifndef VMX_SKIP_GDTR_IDTR
     sub     xSP, xCB * 2
     sgdt    [xSP]
@@ -182 +185 @@
 
     push    xDI
-    mov     xDI, [xSP + xCB * 3]         ; pCtx (*3 to skip the saved LDTR + TR).
+%ifndef VMX_SKIP_LDTR_TR
+    mov     xDI, [xSP + xCB * 3]         ; pCtx (*3 to skip the saved xDI, LDTR + TR).
+%else
+    mov     xDI, [xSP + xCB]             ; pCtx
+%endif
 
     mov     [ss:xDI + CPUMCTX.eax], eax
@@ -202 +209 @@
 %endif
 
+%ifndef VMX_SKIP_LDTR_TR
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
     ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
@@ -217 +225 @@
     pop     xAX         ; Saved LDTR
     lldt    ax
+%endif
 
     add     xSP, xCB     ; pCtx
@@ -267 +276 @@
 %endif
 
+%ifndef VMX_SKIP_LDTR_TR
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
     ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
@@ -282 +292 @@
     pop     xAX         ; Saved LDTR
     lldt    ax
+%endif
 
 %ifdef VMX_USE_CACHED_VMCS_ACCESSES
@@ -306 +317 @@
 %endif
 
+%ifndef VMX_SKIP_LDTR_TR
     ; Restore TSS selector; must mark it as not busy before using ltr (!)
     ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
@@ -321 +333 @@
     pop     xAX         ; Saved LDTR
     lldt    ax
+%endif
 
 %ifdef VMX_USE_CACHED_VMCS_ACCESSES

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -2138 +2138 @@
 {
     int rc = VERR_INTERNAL_ERROR_5;
-    RTSEL uSelDS = 0;
-    RTSEL uSelES = 0;
-    RTSEL uSelFS = 0;
-    RTSEL uSelGS = 0;
-    RTSEL uSelTR = 0;
+    RTSEL uSelDS   = 0;
+    RTSEL uSelES   = 0;
+    RTSEL uSelFS   = 0;
+    RTSEL uSelGS   = 0;
+    RTSEL uSelTR   = 0;
+    RTSEL uSelLDTR = 0;
 
     /*
@@ -2149 +2150 @@
 #if HC_ARCH_BITS == 64
     pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
-    uSelDS = ASMGetDS();
-    uSelES = ASMGetES();
-    uSelFS = ASMGetFS();
-    uSelGS = ASMGetGS();
+    uSelDS   = ASMGetDS();
+    uSelES   = ASMGetES();
+    uSelFS   = ASMGetFS();
+    uSelGS   = ASMGetGS();
+    uSelLDTR = ASMGetLDTR();
 #endif
 
@@ -2210 +2212 @@
         pVCpu->hm.s.vmx.RestoreHost.uHostSelGS = uSelGS;
         uSelGS = 0;
+    }
+
+    /*
+     * VT-x unconditionally writes LDTR to 0 on all VM-exits. If the host has something different, we shall restore it.
+     * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
+     */
+    if (uSelLDTR)
+    {
+        pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_LDTR;
+        pVCpu->hm.s.vmx.RestoreHost.uHostSelLDTR = uSelLDTR;
     }
 #endif
@@ -2317 +2329 @@
 #if HC_ARCH_BITS == 64
         uTRBase = X86DESC64_BASE(pDesc);
+
+        /*
+         * VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on all VM-exits.
+         * The type is the same for 64-bit busy TSS[1]. The limit needs manual restoration if the host has something else.
+         * Task switching is not supported in 64-bit mode[2], but the limit still matters as IOPM is supported in 64-bit mode.
+         * Restoring the limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
+         *
+         * [1] See Intel spec. 3.5 "System Descriptor Types".
+         * [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
+         */
+        Assert(pDesc->System.u4Type == 11);
+        if (   pDesc->System.u16LimitLow != 0x67
+            || pDesc->System.u4LimitHigh)
+        {
+            pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_TR;
+            pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
+
+            /* Store the GDTR here as we need it while restoring TR. */
+            memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
+        }
 #else
         uTRBase = X86DESC_BASE(pDesc);