Changeset 47260 in vbox

Timestamp:

Jul 19, 2013 1:58:55 PM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

87389

Message:

VMM/HMSVMR0: Implement NRIP for instruction intercepts and MSRs. IOIO exits still a todo.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (13 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -3523 +3523 @@
 
 
+/**
+ * Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
+ * CPU, otherwise advances the RIP by @a cb bytes.
+ *
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest-CPU context.
+ * @param   cb          RIP increment value in bytes.
+ *
+ * @remarks Use this function only from #VMEXIT's where the NRIP value is valid
+ *          when NRIP_SAVE is supported by the CPU!
+ */
+DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
+{
+    if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
+    {
+        PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
+        pCtx->rip = pVmcb->ctrl.u64NextRIP;
+    }
+    else
+        pCtx->rip += cb;
+}
+
+
 /* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
 /* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
@@ -3564 +3587 @@
 {
     HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
-    pCtx->rip += 2;         /* Hardcoded opcode, AMD-V doesn't give us this information. */
+
+    hmR0SvmUpdateRip(pVCpu, pCtx, 2);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
     return VINF_SUCCESS;
@@ -3576 +3600 @@
 {
     HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
-    pCtx->rip += 2;         /* Hardcoded opcode, AMD-V doesn't give us this information. */
+
+    hmR0SvmUpdateRip(pVCpu, pCtx, 2);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
     return VINF_SUCCESS;
@@ -3591 +3616 @@
     int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
     if (RT_LIKELY(rc == VINF_SUCCESS))
-        pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        hmR0SvmUpdateRip(pVCpu, pCtx, 2);
     else
     {
@@ -3612 +3637 @@
     if (RT_LIKELY(rc == VINF_SUCCESS))
     {
-        pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        hmR0SvmUpdateRip(pVCpu, pCtx, 2);
         pSvmTransient->fUpdateTscOffsetting = true;
     }
@@ -3634 +3659 @@
     if (RT_LIKELY(rc == VINF_SUCCESS))
     {
-        pCtx->rip += 3;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        hmR0SvmUpdateRip(pVCpu, pCtx, 3);
         pSvmTransient->fUpdateTscOffsetting = true;
     }
@@ -3655 +3680 @@
     int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
     if (RT_LIKELY(rc == VINF_SUCCESS))
-        pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        hmR0SvmUpdateRip(pVCpu, pCtx, 2);
     else
     {
@@ -3689 +3714 @@
 {
     HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
-    pCtx->rip++;        /* Hardcoded opcode, AMD-V doesn't give us this information. */
+    hmR0SvmUpdateRip(pVCpu, pCtx, 1);
     int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
@@ -3704 +3729 @@
     int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
     if (RT_LIKELY(rc == VINF_SUCCESS))
-        pCtx->rip += 3;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        hmR0SvmUpdateRip(pVCpu, pCtx, 3);
     else
     {
@@ -3726 +3751 @@
         ||  rc == VINF_SUCCESS)
     {
-        pCtx->rip += 3;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        hmR0SvmUpdateRip(pVCpu, pCtx, 3);
 
         if (   rc == VINF_EM_HALT
@@ -3842 +3867 @@
     PVM      pVM   = pVCpu->CTX_SUFF(pVM);
 
-    /** @todo r=ramshankar: This cannot be right if prefixes are involved. When
-     *        NRIP_SAVE isn't available we have to disassemble the instruction. */
     int rc;
     if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
@@ -3860 +3883 @@
                 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
             }
-            pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+            hmR0SvmUpdateRip(pVCpu, pCtx, 2);
             return VINF_SUCCESS;
         }
 
-        rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
-        if (RT_LIKELY(rc == VINF_SUCCESS))
-            pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
+        {
+            rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
+            if (RT_LIKELY(rc == VINF_SUCCESS))
+                pCtx->rip = pVmcb->ctrl.u64NextRIP;
+            else
+                AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
+        }
         else
-            AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
+        {
+            VBOXSTRICTRC rcStrict = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
+            rc = VBOXSTRICTRC_VAL(rcStrict);
+            if (RT_UNLIKELY(rc != VINF_SUCCESS))
+                AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
+            /* RIP updated by EMInterpretInstruction(). */
+        }
 
         /* If this is an X2APIC WRMSR access, update the APIC state as well. */
@@ -3888 +3922 @@
         /* MSR Read access. */
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
-        rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
-        if (RT_LIKELY(rc == VINF_SUCCESS))
-            pCtx->rip += 2;     /* Hardcoded opcode, AMD-V doesn't give us this information. */
+        Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
+
+        if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
+        {
+            rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
+            if (RT_LIKELY(rc == VINF_SUCCESS))
+                pCtx->rip = pVmcb->ctrl.u64NextRIP;
+            else
+                AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
+        }
         else
-            AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
+        {
+            VBOXSTRICTRC rcStrict = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
+            rc = VBOXSTRICTRC_VAL(rcStrict);
+            if (RT_UNLIKELY(rc != VINF_SUCCESS))
+                AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
+            /* RIP updated by EMInterpretInstruction(). */
+        }
     }