Changeset 47286 in vbox for trunk/src

Timestamp:

Jul 20, 2013 4:08:07 PM (11 years ago)

Author:

vboxsync

Message:

32-bit mov fixes.

File:

• trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py (modified) (11 diffs)

trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py

@@ -496 +496 @@
         fRexByteRegs = oGen.oTarget.is64Bit();
         oGen.write('        %s %s, %s\n'
-                   % (self.sInstr, gregName(iOp1, cbEffOp * 8, fRexByteRegs),  gregName(iOp2, cbEffOp * 8, fRexByteRegs),));
+                   % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp),));
         return True;
 
@@ -504 +504 @@
         if iOp2 == 13 and iMod == 0 and cAddrBits == 64:
             oGen.write('altrexb '); # Alternative encoding for rip relative addressing.
-        if cbEffOp == 8:
-            oGen.write('%s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));
-        elif cbEffOp == 4:
-            oGen.write('%s %s, [' % (self.sInstr, g_asGRegs32[iOp1],));
-        elif cbEffOp == 2:
-            oGen.write('%s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));
-        elif cbEffOp == 1:
-            oGen.write('%s %s, [' % (self.sInstr, g_asGRegs8Rex[iOp1],));
-        else:
-            assert False;
-
+        oGen.write('%s %s, [' % (self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp),));
         if (iOp2 == 5 or iOp2 == 13) and iMod == 0:
             oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,))
@@ -547 +537 @@
             ## @todo Enable testing this in environments where we can make assumptions (boot sector).
             oGen.write('        %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'
-                       % ( self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));
+                       % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), cbEffOp * 8,));
         else:
-            oGen.write('        altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'
-                       % ( iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));
+            oGen.write('        altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP] ; iOp1=%s cbEffOp=%s\n'
+                       % ( iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), cbEffOp * 8, iOp1, cbEffOp));
         return True;
 
@@ -559 +549 @@
         #       necessity for iScale=1, but doesn't hurt for the rest.
         oGen.write('        altsibx%u %s %s, [%s * %#x'
-                   % (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iIndexReg, cAddrBits), iScale,));
+                   % (iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBits(iIndexReg, cAddrBits), iScale,));
         if offDisp is not None:
             oGen.write(' + %#x' % (offDisp,));
@@ -569 +559 @@
         """ Writes the instruction taking a register and base only (with reg), SIB form. """
         oGen.write('        altsibx%u %s %s, [%s'
-                   % (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iBaseReg, cAddrBits),));
+                   % (iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBits(iBaseReg, cAddrBits),));
         if offDisp is not None:
             oGen.write(' + %#x' % (offDisp,));
@@ -584 +574 @@
         #       which is index and which is base.
         oGen.write('        %s %s, [%s + %s * %u'
-                   % ( self.sInstr, gregName(iOp1, cbEffOp * 8),
-                       gregName(iBaseReg, cAddrBits), gregName(iIndexReg, cAddrBits), iScale,));
+                   % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp),
+                       oGen.gregNameBits(iBaseReg, cAddrBits), oGen.gregNameBits(iIndexReg, cAddrBits), iScale,));
         if offDisp is not None:
             oGen.write(' + %#x' % (offDisp,));
@@ -1326 +1316 @@
 #
 g_aoInstructionTests = [
-    #InstrTest_Mov_Gv_Ev(),
+    InstrTest_Mov_Gv_Ev(),
     ##InstrTest_MovSxD_Gv_Ev(),
     InstrTest_DivIDiv(fIsIDiv = False),
@@ -1756 +1746 @@
                 while iTmpReg2 in [iBaseReg, iIndexReg, iTmpReg1]:
                     iTmpReg2 += 1;
-                sTmpReg2 = gregName(iTmpReg2, cAddrBits);
+                sTmpReg2 = self.gregNameBits(iTmpReg2, cAddrBits);
                 self.write('        push    sAX\n'
                            '        push    %s\n'
@@ -1766 +1756 @@
                     self.write('        mov     %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sTmpReg2,));
                 self.write('        add     %s, 0x200\n' % (sTmpReg2,));
-                self.write('        mov     %s, %s\n' % (gregName(X86_GREG_xAX, cAddrBits), sTmpReg2,));
+                self.write('        mov     %s, %s\n' % (self.gregNameBits(X86_GREG_xAX, cAddrBits), sTmpReg2,));
                 if u32Disp is not None:
-                    self.write('        sub     %s, %d\n' % ( gregName(X86_GREG_xAX, cAddrBits), convU32ToSigned(u32Disp), ));
+                    self.write('        sub     %s, %d\n'
+                               % ( self.gregNameBits(X86_GREG_xAX, cAddrBits), convU32ToSigned(u32Disp), ));
                 self.write('        xor     edx, edx\n'
                            '%if xCB == 2\n'
@@ -1775 +1766 @@
                 self.write('        push    %u\n' % (iScale + 1,));
                 self.write('        div     %s [xSP]\n' % ('qword' if cAddrBits == 64 else 'dword',));
-                self.write('        sub     %s, %s\n' % (sTmpReg2, gregName(X86_GREG_xDX, cAddrBits),));
+                self.write('        sub     %s, %s\n' % (sTmpReg2, self.gregNameBits(X86_GREG_xDX, cAddrBits),));
                 self.write('        pop     sDX\n'
                            '        pop     sDX\n'); # sTmpReg2 is eff address; sAX is sIndexReg value.
@@ -1785 +1776 @@
                     self.write('        pop     %s\n' % (self.oTarget.asGRegs[iTmpReg1],));
                 else:
-                    self.write('        mov     %s, %s\n' % (sBaseReg, gregName(X86_GREG_xAX, cAddrBits),));
+                    self.write('        mov     %s, %s\n' % (sBaseReg, self.gregNameBits(X86_GREG_xAX, cAddrBits),));
                     self.write('        pop     sAX\n');