Changeset 47287 in vbox for trunk/src/VBox

Timestamp:

Jul 20, 2013 8:06:43 PM (11 years ago)

Author:

vboxsync

Message:

Back to the MOVXSD instruction.

File:

• trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py (modified) (8 diffs)

trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py

@@ -488 +488 @@
         self.fnCalcResult = fnCalcResult;
         self.acbOpVars    = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars);
+        self.fTestRegForm = True;
+        self.fTestMemForm = True;
 
     ## @name Test Instruction Writers
@@ -494 +496 @@
     def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
         """ Writes the instruction with two general registers as operands. """
-        fRexByteRegs = oGen.oTarget.is64Bit();
         oGen.write('        %s %s, %s\n'
                    % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp),));
@@ -586 +587 @@
     ## @name Memory setups
     ## @{
+
     def generateMemSetupReadByLabel(self, oGen, cbEffOp, uInput):
         """ Sets up memory for a memory read. """
@@ -794 +796 @@
 
         # Register tests
-        if True:
+        if self.fTestRegForm:
             for cbEffOp in self.acbOpVars:
                 if cbEffOp > cbMaxOp:
@@ -825 +827 @@
 
         # Memory test.
-        if True:
+        if self.fTestMemForm:
             for cAddrBits in oGen.oTarget.getAddrModes():
                 for cbEffOp in self.acbOpVars:
@@ -853 +855 @@
                                 # SIB - currently only short list of inputs or things may get seriously out of hand.
                                 self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, oGen.iModReg, auShortInputs);
-                    #break;
-                #break;
-
-
         return True;
 
     def generateTest(self, oGen, sTestFnName):
         oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,));
-        #oGen.write('        int3\n');
 
         self.generateStandardTests(oGen);
 
-        #oGen.write('        int3\n');
         oGen.write('        ret\n');
         oGen.write('VBINSTST_ENDPROC   %s\n' % (sTestFnName,));
@@ -898 +894 @@
     def __init__(self):
         InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]);
+        self.fTestMemForm = False; # drop this...
 
     def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
+        """ Writes the instruction with two general registers as operands. """
         if cbEffOp == 8:
-            oGen.write('        %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs32[iOp2]));
-        elif cbEffOp == 4 or cbEffOp == 2:
-            abInstr = [];
-            if cbEffOp != oGen.oTarget.getDefOpBytes():
-                abInstr.append(X86_OP_PRF_SIZE_OP);
-            abInstr += calcRexPrefixForTwoModRmRegs(iOp1, iOp2);
-            abInstr.append(0x63);
-            abInstr += calcModRmForTwoRegs(iOp1, iOp2);
-            oGen.writeInstrBytes(abInstr);
+            oGen.write('        movsxd %s, %s\n'
+                       % ( oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp / 2),));
         else:
-            assert False;
-            assert False;
+            oGen.write('        oddmovsxd %s, %s\n'
+                       % ( oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp),));
         return True;
 
@@ -1317 +1308 @@
 g_aoInstructionTests = [
     InstrTest_Mov_Gv_Ev(),
-    ##InstrTest_MovSxD_Gv_Ev(),
+    InstrTest_MovSxD_Gv_Ev(),
     InstrTest_DivIDiv(fIsIDiv = False),
     InstrTest_DivIDiv(fIsIDiv = True),