Changeset 47322 in vbox
- Timestamp:
- Jul 22, 2013 5:57:43 PM (12 years ago)
- File:
-
- 1 edited
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trunk/include/VBox/vmm/hm_vmx.h (modified) (25 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/hm_vmx.h
r47320 r47322 578 578 */ 579 579 /** And-mask for setting reserved bits to zero */ 580 #define VMX_EFLAGS_RESERVED_0 (~0xffc08028)580 #define VMX_EFLAGS_RESERVED_0 (~0xffc08028) 581 581 /** Or-mask for setting reserved bits to 1 */ 582 #define VMX_EFLAGS_RESERVED_1 0x00000002582 #define VMX_EFLAGS_RESERVED_1 0x00000002 583 583 /** @} */ 584 584 … … 587 587 */ 588 588 /** -1 Invalid exit code */ 589 #define VMX_EXIT_INVALID -1589 #define VMX_EXIT_INVALID -1 590 590 /** 0 Exception or non-maskable interrupt (NMI). */ 591 #define VMX_EXIT_XCPT_OR_NMI 0591 #define VMX_EXIT_XCPT_OR_NMI 0 592 592 /** 1 External interrupt. */ 593 #define VMX_EXIT_EXT_INT 1593 #define VMX_EXIT_EXT_INT 1 594 594 /** 2 Triple fault. */ 595 #define VMX_EXIT_TRIPLE_FAULT 2595 #define VMX_EXIT_TRIPLE_FAULT 2 596 596 /** 3 INIT signal. */ 597 #define VMX_EXIT_INIT_SIGNAL 3597 #define VMX_EXIT_INIT_SIGNAL 3 598 598 /** 4 Start-up IPI (SIPI). */ 599 #define VMX_EXIT_SIPI 4599 #define VMX_EXIT_SIPI 4 600 600 /** 5 I/O system-management interrupt (SMI). */ 601 #define VMX_EXIT_IO_SMI 5601 #define VMX_EXIT_IO_SMI 5 602 602 /** 6 Other SMI. */ 603 #define VMX_EXIT_SMI 6603 #define VMX_EXIT_SMI 6 604 604 /** 7 Interrupt window exiting. */ 605 #define VMX_EXIT_INT_WINDOW 7605 #define VMX_EXIT_INT_WINDOW 7 606 606 /** 8 NMI window exiting. */ 607 #define VMX_EXIT_NMI_WINDOW 8607 #define VMX_EXIT_NMI_WINDOW 8 608 608 /** 9 Task switch. */ 609 #define VMX_EXIT_TASK_SWITCH 9609 #define VMX_EXIT_TASK_SWITCH 9 610 610 /** 10 Guest software attempted to execute CPUID. */ 611 #define VMX_EXIT_CPUID 10611 #define VMX_EXIT_CPUID 10 612 612 /** 10 Guest software attempted to execute GETSEC. */ 613 #define VMX_EXIT_GETSEC 11613 #define VMX_EXIT_GETSEC 11 614 614 /** 12 Guest software attempted to execute HLT. */ 615 #define VMX_EXIT_HLT 12615 #define VMX_EXIT_HLT 12 616 616 /** 13 Guest software attempted to execute INVD. */ 617 #define VMX_EXIT_INVD 13617 #define VMX_EXIT_INVD 13 618 618 /** 14 Guest software attempted to execute INVLPG. */ 619 #define VMX_EXIT_INVLPG 14619 #define VMX_EXIT_INVLPG 14 620 620 /** 15 Guest software attempted to execute RDPMC. */ 621 #define VMX_EXIT_RDPMC 15621 #define VMX_EXIT_RDPMC 15 622 622 /** 16 Guest software attempted to execute RDTSC. */ 623 #define VMX_EXIT_RDTSC 16623 #define VMX_EXIT_RDTSC 16 624 624 /** 17 Guest software attempted to execute RSM in SMM. */ 625 #define VMX_EXIT_RSM 17625 #define VMX_EXIT_RSM 17 626 626 /** 18 Guest software executed VMCALL. */ 627 #define VMX_EXIT_VMCALL 18627 #define VMX_EXIT_VMCALL 18 628 628 /** 19 Guest software executed VMCLEAR. */ 629 #define VMX_EXIT_VMCLEAR 19629 #define VMX_EXIT_VMCLEAR 19 630 630 /** 20 Guest software executed VMLAUNCH. */ 631 #define VMX_EXIT_VMLAUNCH 20631 #define VMX_EXIT_VMLAUNCH 20 632 632 /** 21 Guest software executed VMPTRLD. */ 633 #define VMX_EXIT_VMPTRLD 21633 #define VMX_EXIT_VMPTRLD 21 634 634 /** 22 Guest software executed VMPTRST. */ 635 #define VMX_EXIT_VMPTRST 22635 #define VMX_EXIT_VMPTRST 22 636 636 /** 23 Guest software executed VMREAD. */ 637 #define VMX_EXIT_VMREAD 23637 #define VMX_EXIT_VMREAD 23 638 638 /** 24 Guest software executed VMRESUME. */ 639 #define VMX_EXIT_VMRESUME 24639 #define VMX_EXIT_VMRESUME 24 640 640 /** 25 Guest software executed VMWRITE. */ 641 #define VMX_EXIT_VMWRITE 25641 #define VMX_EXIT_VMWRITE 25 642 642 /** 26 Guest software executed VMXOFF. */ 643 #define VMX_EXIT_VMXOFF 26643 #define VMX_EXIT_VMXOFF 26 644 644 /** 27 Guest software executed VMXON. */ 645 #define VMX_EXIT_VMXON 27645 #define VMX_EXIT_VMXON 27 646 646 /** 28 Control-register accesses. */ 647 #define VMX_EXIT_MOV_CRX 28647 #define VMX_EXIT_MOV_CRX 28 648 648 /** 29 Debug-register accesses. */ 649 #define VMX_EXIT_MOV_DRX 29649 #define VMX_EXIT_MOV_DRX 29 650 650 /** 30 I/O instruction. */ 651 #define VMX_EXIT_IO_INSTR 30651 #define VMX_EXIT_IO_INSTR 30 652 652 /** 31 RDMSR. Guest software attempted to execute RDMSR. */ 653 #define VMX_EXIT_RDMSR 31653 #define VMX_EXIT_RDMSR 31 654 654 /** 32 WRMSR. Guest software attempted to execute WRMSR. */ 655 #define VMX_EXIT_WRMSR 32655 #define VMX_EXIT_WRMSR 32 656 656 /** 33 VM-entry failure due to invalid guest state. */ 657 #define VMX_EXIT_ERR_INVALID_GUEST_STATE 33657 #define VMX_EXIT_ERR_INVALID_GUEST_STATE 33 658 658 /** 34 VM-entry failure due to MSR loading. */ 659 #define VMX_EXIT_ERR_MSR_LOAD 34659 #define VMX_EXIT_ERR_MSR_LOAD 34 660 660 /** 36 Guest software executed MWAIT. */ 661 #define VMX_EXIT_MWAIT 36661 #define VMX_EXIT_MWAIT 36 662 662 /** 37 VM exit due to monitor trap flag. */ 663 #define VMX_EXIT_MTF 37663 #define VMX_EXIT_MTF 37 664 664 /** 39 Guest software attempted to execute MONITOR. */ 665 #define VMX_EXIT_MONITOR 39665 #define VMX_EXIT_MONITOR 39 666 666 /** 40 Guest software attempted to execute PAUSE. */ 667 #define VMX_EXIT_PAUSE 40667 #define VMX_EXIT_PAUSE 40 668 668 /** 41 VM-entry failure due to machine-check. */ 669 #define VMX_EXIT_ERR_MACHINE_CHECK 41669 #define VMX_EXIT_ERR_MACHINE_CHECK 41 670 670 /** 43 TPR below threshold. Guest software executed MOV to CR8. */ 671 #define VMX_EXIT_TPR_BELOW_THRESHOLD 43671 #define VMX_EXIT_TPR_BELOW_THRESHOLD 43 672 672 /** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */ 673 #define VMX_EXIT_APIC_ACCESS 44673 #define VMX_EXIT_APIC_ACCESS 44 674 674 /** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */ 675 #define VMX_EXIT_XDTR_ACCESS 46675 #define VMX_EXIT_XDTR_ACCESS 46 676 676 /** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */ 677 #define VMX_EXIT_TR_ACCESS 47677 #define VMX_EXIT_TR_ACCESS 47 678 678 /** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */ 679 #define VMX_EXIT_EPT_VIOLATION 48679 #define VMX_EXIT_EPT_VIOLATION 48 680 680 /** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */ 681 #define VMX_EXIT_EPT_MISCONFIG 49681 #define VMX_EXIT_EPT_MISCONFIG 49 682 682 /** 50 INVEPT. Guest software attempted to execute INVEPT. */ 683 #define VMX_EXIT_INVEPT 50683 #define VMX_EXIT_INVEPT 50 684 684 /** 51 RDTSCP. Guest software attempted to execute RDTSCP. */ 685 #define VMX_EXIT_RDTSCP 51685 #define VMX_EXIT_RDTSCP 51 686 686 /** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */ 687 #define VMX_EXIT_PREEMPT_TIMER 52687 #define VMX_EXIT_PREEMPT_TIMER 52 688 688 /** 53 INVVPID. Guest software attempted to execute INVVPID. */ 689 #define VMX_EXIT_INVVPID 53689 #define VMX_EXIT_INVVPID 53 690 690 /** 54 WBINVD. Guest software attempted to execute WBINVD. */ 691 #define VMX_EXIT_WBINVD 54691 #define VMX_EXIT_WBINVD 54 692 692 /** 55 XSETBV. Guest software attempted to execute XSETBV. */ 693 #define VMX_EXIT_XSETBV 55693 #define VMX_EXIT_XSETBV 55 694 694 /** 57 RDRAND. Guest software attempted to execute RDRAND. */ 695 #define VMX_EXIT_RDRAND 57695 #define VMX_EXIT_RDRAND 57 696 696 /** 58 INVPCID. Guest software attempted to execute INVPCID. */ 697 #define VMX_EXIT_INVPCID 58697 #define VMX_EXIT_INVPCID 58 698 698 /** 59 VMFUNC. Guest software attempted to execute VMFUNC. */ 699 #define VMX_EXIT_VMFUNC 59699 #define VMX_EXIT_VMFUNC 59 700 700 /** The maximum exit value (inclusive). */ 701 #define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)701 #define VMX_EXIT_MAX (VMX_EXIT_VMFUNC) 702 702 /** @} */ 703 703 … … 706 706 * @{ 707 707 */ 708 /** 1VMCALL executed in VMX root operation. */709 #define VMX_ERROR_VMCALL 1710 /** 2VMCLEAR with invalid physical address. */711 #define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2712 /** 3VMCLEAR with VMXON pointer. */713 #define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3714 /** 4VMLAUNCH with non-clear VMCS. */715 #define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4716 /** 5VMRESUME with non-launched VMCS. */717 #define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5718 /** 6VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */719 #define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6720 /** 7 VMentry with invalid control field(s). */721 #define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7722 /** 8 VMentry with invalid host-state field(s). */723 #define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8724 /** 9VMPTRLD with invalid physical address. */725 #define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9726 /** 10VMPTRLD with VMXON pointer. */727 #define VMX_ERROR_VMPTRLD_VMXON_PTR 10728 /** 11VMPTRLD with incorrect VMCS revision identifier. */729 #define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11730 /** 12VMREAD/VMWRITE from/to unsupported VMCS component. */731 #define VMX_ERROR_VMREAD_INVALID_COMPONENT 12732 #define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT733 /** 13VMWRITE to read-only VMCS component. */734 #define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13735 /** 15VMXON executed in VMX root operation. */736 #define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15737 /** 16VM entry with invalid executive-VMCS pointer. */738 #define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16739 /** 17VM entry with non-launched executive VMCS. */740 #define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17741 /** 18VM entry with executive-VMCS pointer not VMXON pointer. */742 #define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18743 /** 19VMCALL with non-clear VMCS. */744 #define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19745 /** 20VMCALL with invalid VM-exit control fields. */746 #define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20747 /** 22VMCALL with incorrect MSEG revision identifier. */748 #define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22749 /** 23VMXOFF under dual-monitor treatment of SMIs and SMM. */750 #define VMX_ERROR_VMXOFF_DUAL_MONITOR 23751 /** 24VMCALL with invalid SMM-monitor features. */752 #define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24753 /** 25VM entry with invalid VM-execution control fields in executive VMCS. */754 #define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25755 /** 26VM entry with events blocked by MOV SS. */756 #define VMX_ERROR_VMENTRY_MOV_SS 26757 /** 26Invalid operand to INVEPT/INVVPID. */758 #define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28708 /** VMCALL executed in VMX root operation. */ 709 #define VMX_ERROR_VMCALL 1 710 /** VMCLEAR with invalid physical address. */ 711 #define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2 712 /** VMCLEAR with VMXON pointer. */ 713 #define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3 714 /** VMLAUNCH with non-clear VMCS. */ 715 #define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4 716 /** VMRESUME with non-launched VMCS. */ 717 #define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5 718 /** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */ 719 #define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6 720 /** VM-entry with invalid control field(s). */ 721 #define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7 722 /** VM-entry with invalid host-state field(s). */ 723 #define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8 724 /** VMPTRLD with invalid physical address. */ 725 #define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9 726 /** VMPTRLD with VMXON pointer. */ 727 #define VMX_ERROR_VMPTRLD_VMXON_PTR 10 728 /** VMPTRLD with incorrect VMCS revision identifier. */ 729 #define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11 730 /** VMREAD/VMWRITE from/to unsupported VMCS component. */ 731 #define VMX_ERROR_VMREAD_INVALID_COMPONENT 12 732 #define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT 733 /** VMWRITE to read-only VMCS component. */ 734 #define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13 735 /** VMXON executed in VMX root operation. */ 736 #define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15 737 /** VM entry with invalid executive-VMCS pointer. */ 738 #define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16 739 /** VM entry with non-launched executive VMCS. */ 740 #define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17 741 /** VM entry with executive-VMCS pointer not VMXON pointer. */ 742 #define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18 743 /** VMCALL with non-clear VMCS. */ 744 #define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19 745 /** VMCALL with invalid VM-exit control fields. */ 746 #define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20 747 /** VMCALL with incorrect MSEG revision identifier. */ 748 #define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22 749 /** VMXOFF under dual-monitor treatment of SMIs and SMM. */ 750 #define VMX_ERROR_VMXOFF_DUAL_MONITOR 23 751 /** VMCALL with invalid SMM-monitor features. */ 752 #define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24 753 /** VM entry with invalid VM-execution control fields in executive VMCS. */ 754 #define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25 755 /** VM entry with events blocked by MOV SS. */ 756 #define VMX_ERROR_VMENTRY_MOV_SS 26 757 /** Invalid operand to INVEPT/INVVPID. */ 758 #define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28 759 759 760 760 /** @} */ … … 817 817 * @{ 818 818 */ 819 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY 820 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY 821 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY 822 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS 823 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS 824 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS 825 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS 826 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS 827 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC 828 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC 829 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT 830 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP 831 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB 832 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS 833 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS 834 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS 835 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS 836 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT 837 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT 838 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS 839 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID 840 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR 841 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT 842 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS 843 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS 819 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0) 820 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1) 821 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2) 822 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3) 823 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4) 824 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5) 825 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6) 826 #define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7) 827 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8) 828 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9) 829 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12) 830 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13) 831 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14) 832 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16) 833 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17) 834 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18) 835 #define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19) 836 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20) 837 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25) 838 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26) 839 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32) 840 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40) 841 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41) 842 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42) 843 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43) 844 844 845 845 /** @} */ … … 849 849 */ 850 850 /** Uncachable EPT paging structure memory type. */ 851 #define VMX_EPT_MEMTYPE_UC 0851 #define VMX_EPT_MEMTYPE_UC 0 852 852 /** Write-back EPT paging structure memory type. */ 853 #define VMX_EPT_MEMTYPE_WB 6853 #define VMX_EPT_MEMTYPE_WB 6 854 854 /** Shift value to get the EPT page walk length (bits 5-3) */ 855 #define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3855 #define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3 856 856 /** Mask value to get the EPT page walk length (bits 5-3) */ 857 #define VMX_EPT_PAGE_WALK_LENGTH_MASK 7857 #define VMX_EPT_PAGE_WALK_LENGTH_MASK 7 858 858 /** Default EPT page-walk length (1 less than the actual EPT page-walk 859 859 * length) */ 860 #define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3860 #define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3 861 861 /** @} */ 862 862 … … 865 865 * @{ 866 866 */ 867 #define VMX_VMCS16_GUEST_FIELD_VPID 868 #define VMX_VMCS16_GUEST_FIELD_ES 869 #define VMX_VMCS16_GUEST_FIELD_CS 870 #define VMX_VMCS16_GUEST_FIELD_SS 871 #define VMX_VMCS16_GUEST_FIELD_DS 872 #define VMX_VMCS16_GUEST_FIELD_FS 873 #define VMX_VMCS16_GUEST_FIELD_GS 874 #define VMX_VMCS16_GUEST_FIELD_LDTR 875 #define VMX_VMCS16_GUEST_FIELD_TR 867 #define VMX_VMCS16_GUEST_FIELD_VPID 0x0 868 #define VMX_VMCS16_GUEST_FIELD_ES 0x800 869 #define VMX_VMCS16_GUEST_FIELD_CS 0x802 870 #define VMX_VMCS16_GUEST_FIELD_SS 0x804 871 #define VMX_VMCS16_GUEST_FIELD_DS 0x806 872 #define VMX_VMCS16_GUEST_FIELD_FS 0x808 873 #define VMX_VMCS16_GUEST_FIELD_GS 0x80A 874 #define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C 875 #define VMX_VMCS16_GUEST_FIELD_TR 0x80E 876 876 /** @} */ 877 877 … … 879 879 * @{ 880 880 */ 881 #define VMX_VMCS16_HOST_FIELD_ES 882 #define VMX_VMCS16_HOST_FIELD_CS 883 #define VMX_VMCS16_HOST_FIELD_SS 884 #define VMX_VMCS16_HOST_FIELD_DS 885 #define VMX_VMCS16_HOST_FIELD_FS 886 #define VMX_VMCS16_HOST_FIELD_GS 887 #define VMX_VMCS16_HOST_FIELD_TR 881 #define VMX_VMCS16_HOST_FIELD_ES 0xC00 882 #define VMX_VMCS16_HOST_FIELD_CS 0xC02 883 #define VMX_VMCS16_HOST_FIELD_SS 0xC04 884 #define VMX_VMCS16_HOST_FIELD_DS 0xC06 885 #define VMX_VMCS16_HOST_FIELD_FS 0xC08 886 #define VMX_VMCS16_HOST_FIELD_GS 0xC0A 887 #define VMX_VMCS16_HOST_FIELD_TR 0xC0C 888 888 /** @} */ 889 889 … … 891 891 * @{ 892 892 */ 893 #define VMX_VMCS64_HOST_FIELD_PAT_FULL 894 #define VMX_VMCS64_HOST_FIELD_PAT_HIGH 895 #define VMX_VMCS64_HOST_FIELD_EFER_FULL 896 #define VMX_VMCS64_HOST_FIELD_EFER_HIGH 897 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 898 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 893 #define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00 894 #define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01 895 #define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02 896 #define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03 897 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */ 898 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */ 899 899 /** @} */ 900 900 … … 903 903 * @{ 904 904 */ 905 #define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 906 #define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 907 #define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 908 #define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 905 #define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000 906 #define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001 907 #define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002 908 #define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003 909 909 910 910 /* Optional */ 911 #define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 912 #define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 913 914 #define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 915 #define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 916 #define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 917 #define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 918 919 #define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 920 #define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 921 922 #define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 923 #define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 924 925 #define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 926 #define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 911 #define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004 912 #define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005 913 914 #define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006 915 #define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007 916 #define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008 917 #define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009 918 919 #define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A 920 #define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B 921 922 #define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C 923 #define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D 924 925 #define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010 926 #define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011 927 927 928 928 /** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */ 929 #define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 930 #define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 929 #define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012 930 #define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013 931 931 932 932 /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */ 933 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 934 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 933 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014 934 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015 935 935 936 936 /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */ 937 #define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 938 #define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 937 #define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018 938 #define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019 939 939 940 940 /** Extended page table pointer. */ 941 #define VMX_VMCS64_CTRL_EPTP_FULL 942 #define VMX_VMCS64_CTRL_EPTP_HIGH 941 #define VMX_VMCS64_CTRL_EPTP_FULL 0x201a 942 #define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b 943 943 944 944 /** Extended page table pointer lists. */ 945 #define VMX_VMCS64_CTRL_EPTP_LIST_FULL 946 #define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 945 #define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024 946 #define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025 947 947 948 948 /** VM-exit guest phyiscal address. */ 949 #define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 950 #define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 949 #define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400 950 #define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401 951 951 /** @} */ 952 952 … … 1002 1002 */ 1003 1003 /** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */ 1004 #define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)1004 #define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0) 1005 1005 /** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */ 1006 #define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)1006 #define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3) 1007 1007 /** Virtual NMIs. */ 1008 #define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)1008 #define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5) 1009 1009 /** Activate VMX preemption timer. */ 1010 #define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)1010 #define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6) 1011 1011 /* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */ 1012 1012 /** @} */ … … 1016 1016 */ 1017 1017 /** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */ 1018 #define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)1018 #define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2) 1019 1019 /** Use timestamp counter offset. */ 1020 #define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)1020 #define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3) 1021 1021 /** VM Exit when executing the HLT instruction. */ 1022 #define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)1022 #define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7) 1023 1023 /** VM Exit when executing the INVLPG instruction. */ 1024 #define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)1024 #define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9) 1025 1025 /** VM Exit when executing the MWAIT instruction. */ 1026 #define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)1026 #define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10) 1027 1027 /** VM Exit when executing the RDPMC instruction. */ 1028 #define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)1028 #define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11) 1029 1029 /** VM Exit when executing the RDTSC/RDTSCP instruction. */ 1030 #define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)1030 #define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12) 1031 1031 /** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ 1032 #define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)1032 #define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15) 1033 1033 /** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ 1034 #define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)1034 #define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16) 1035 1035 /** VM Exit on CR8 loads. */ 1036 #define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)1036 #define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19) 1037 1037 /** VM Exit on CR8 stores. */ 1038 #define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)1038 #define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20) 1039 1039 /** Use TPR shadow. */ 1040 #define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)1040 #define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21) 1041 1041 /** VM Exit when virtual nmi blocking is disabled. */ 1042 #define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)1042 #define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22) 1043 1043 /** VM Exit when executing a MOV DRx instruction. */ 1044 #define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)1044 #define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23) 1045 1045 /** VM Exit when executing IO instructions. */ 1046 #define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)1046 #define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24) 1047 1047 /** Use IO bitmaps. */ 1048 #define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)1048 #define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25) 1049 1049 /** Monitor trap flag. */ 1050 #define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)1050 #define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27) 1051 1051 /** Use MSR bitmaps. */ 1052 #define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)1052 #define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28) 1053 1053 /** VM Exit when executing the MONITOR instruction. */ 1054 #define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)1054 #define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29) 1055 1055 /** VM Exit when executing the PAUSE instruction. */ 1056 #define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)1056 #define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30) 1057 1057 /** Determines whether the secondary processor based VM-execution controls are used. */ 1058 1058 #define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31) … … 1093 1093 */ 1094 1094 /** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ 1095 #define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)1095 #define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2) 1096 1096 /** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */ 1097 #define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)1097 #define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9) 1098 1098 /** In SMM mode after VM-entry. */ 1099 #define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)1099 #define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10) 1100 1100 /** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */ 1101 #define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)1102 /** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */1103 #define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)1104 /** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */1105 #define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)1106 /** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */1107 #define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)1101 #define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11) 1102 /** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */ 1103 #define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13) 1104 /** Whether the guest IA32_PAT MSR is loaded on VM entry. */ 1105 #define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14) 1106 /** Whether the guest IA32_EFER MSR is loaded on VM entry. */ 1107 #define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15) 1108 1108 /** @} */ 1109 1109 … … 1113 1113 */ 1114 1114 /** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ 1115 #define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)1115 #define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2) 1116 1116 /** Return to long mode after a VM-exit. */ 1117 #define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)1118 /** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */1119 #define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)1117 #define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9) 1118 /** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */ 1119 #define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12) 1120 1120 /** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */ 1121 #define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15) 1122 /** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */ 1123 #define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18) 1124 /** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */ 1125 #define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19) 1126 /** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */ 1127 #define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20) 1128 /** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */ 1129 #define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21) 1130 /** This control determines whether the value of the VMX preemption timer is 1131 * saved on every VM exit. */ 1132 #define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22) 1121 #define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15) 1122 /** Whether the guest IA32_PAT MSR is saved on VM exit. */ 1123 #define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18) 1124 /** Whether the host IA32_PAT MSR is loaded on VM exit. */ 1125 #define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19) 1126 /** Whether the guest IA32_EFER MSR is saved on VM exit. */ 1127 #define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20) 1128 /** Whether the host IA32_EFER MSR is loaded on VM exit. */ 1129 #define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21) 1130 /** Whether the value of the VMX preemption timer is saved on every VM exit. */ 1131 #define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22) 1133 1132 /** @} */ 1134 1133 … … 1256 1255 /** The logical processor is inactive, because executed a HLT instruction. */ 1257 1256 #define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1 1258 /** The logical processor is inactive, because of a triple fault or other 1259 * serious error. */ 1257 /** The logical processor is inactive, because of a triple fault or other serious error. */ 1260 1258 #define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2 1261 1259 /** The logical processor is inactive, because it's waiting for a startup-IPI */ … … 1310 1308 */ 1311 1309 /** 0-2: Debug register number */ 1312 #define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)1310 #define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7) 1313 1311 /** 3: Reserved; cleared to 0. */ 1314 #define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)1312 #define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1) 1315 1313 /** 4: Direction of move (0 = write, 1 = read) */ 1316 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)1314 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1) 1317 1315 /** 5-7: Reserved; cleared to 0. */ 1318 #define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)1316 #define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7) 1319 1317 /** 8-11: General purpose register number. */ 1320 #define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)1318 #define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF) 1321 1319 /** Rest: reserved. */ 1322 1320 /** @} */ … … 1325 1323 * @{ 1326 1324 */ 1327 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 01328 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 11325 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0 1326 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1 1329 1327 /** @} */ 1330 1328 … … 1335 1333 */ 1336 1334 /** 0-3: Control register number (0 for CLTS & LMSW) */ 1337 #define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)1335 #define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF) 1338 1336 /** 4-5: Access type. */ 1339 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)1337 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3) 1340 1338 /** 6: LMSW operand type */ 1341 #define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)1339 #define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1) 1342 1340 /** 7: Reserved; cleared to 0. */ 1343 #define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)1341 #define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1) 1344 1342 /** 8-11: General purpose register number (0 for CLTS & LMSW). */ 1345 #define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)1343 #define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF) 1346 1344 /** 12-15: Reserved; cleared to 0. */ 1347 #define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)1345 #define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF) 1348 1346 /** 16-31: LMSW source data (else 0). */ 1349 #define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)1347 #define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF) 1350 1348 /** Rest: reserved. */ 1351 1349 /** @} */ … … 1354 1352 * @{ 1355 1353 */ 1356 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 01357 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 11358 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 21359 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 31354 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0 1355 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1 1356 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2 1357 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3 1360 1358 /** @} */ 1361 1359 … … 1363 1361 * @{ 1364 1362 */ 1365 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)1366 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)1363 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff) 1364 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3) 1367 1365 /** Task switch caused by a call instruction. */ 1368 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 01366 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0 1369 1367 /** Task switch caused by an iret instruction. */ 1370 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 11368 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1 1371 1369 /** Task switch caused by a jmp instruction. */ 1372 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 21370 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2 1373 1371 /** Task switch caused by an interrupt gate. */ 1374 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 31372 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3 1375 1373 /** @} */ 1376 1374 … … 1380 1378 */ 1381 1379 /** Set if the violation was caused by a data read. */ 1382 #define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)1380 #define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0) 1383 1381 /** Set if the violation was caused by a data write. */ 1384 #define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)1382 #define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1) 1385 1383 /** Set if the violation was caused by an insruction fetch. */ 1386 #define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)1384 #define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2) 1387 1385 /** AND of the present bit of all EPT structures. */ 1388 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)1386 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3) 1389 1387 /** AND of the write bit of all EPT structures. */ 1390 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)1388 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4) 1391 1389 /** AND of the execute bit of all EPT structures. */ 1392 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)1390 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5) 1393 1391 /** Set if the guest linear address field contains the faulting address. */ 1394 #define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)1392 #define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7) 1395 1393 /** If bit 7 is one: (reserved otherwise) 1396 1394 * 1 - violation due to physical address access. 1397 1395 * 0 - violation caused by page walk or access/dirty bit updates 1398 1396 */ 1399 #define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)1397 #define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8) 1400 1398 /** @} */ 1401 1399 … … 1405 1403 */ 1406 1404 /** 0-2: IO operation width. */ 1407 #define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)1405 #define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7) 1408 1406 /** 3: IO operation direction. */ 1409 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)1407 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1) 1410 1408 /** 4: String IO operation. */ 1411 #define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)1409 #define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1) 1412 1410 /** 5: Repeated IO operation. */ 1413 #define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)1411 #define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1) 1414 1412 /** 6: Operand encoding. */ 1415 #define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)1413 #define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1) 1416 1414 /** 16-31: IO Port (0-0xffff). */ 1417 #define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)1415 #define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff) 1418 1416 /* Rest reserved. */ 1419 1417 /** @} */ … … 1422 1420 * @{ 1423 1421 */ 1424 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 01425 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 11422 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0 1423 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1 1426 1424 /** @} */ 1427 1425 … … 1430 1428 * @{ 1431 1429 */ 1432 #define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 01433 #define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 11430 #define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0 1431 #define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1 1434 1432 /** @} */ 1435 1433 … … 1438 1436 */ 1439 1437 /** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */ 1440 #define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)1438 #define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff) 1441 1439 /** 12-15: Access type. */ 1442 #define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)1440 #define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000) 1443 1441 /* Rest reserved. */ 1444 1442 /** @} */ … … 1449 1447 */ 1450 1448 /** Linear read access. */ 1451 #define VMX_APIC_ACCESS_TYPE_LINEAR_READ 01449 #define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0 1452 1450 /** Linear write access. */ 1453 #define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 11451 #define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1 1454 1452 /** Linear instruction fetch access. */ 1455 #define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 21453 #define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2 1456 1454 /** Linear read/write access during event delivery. */ 1457 #define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 31455 #define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3 1458 1456 /** Physical read/write access during event delivery. */ 1459 #define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 101457 #define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10 1460 1458 /** Physical access for an instruction fetch or during instruction execution. */ 1461 #define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 151459 #define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15 1462 1460 /** @} */ 1463 1461
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