Changeset 47328 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Jul 22, 2013 10:50:49 PM (12 years ago)

Author:

vboxsync

Message:

CPUM,++: Fix DR6 and DR7 read-as-1 (RA1) and read-as-zero (RAZ) values on load since REM didn't set them right for years. Introduced constants for these values.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• CPUMAllRegs.cpp (modified) (1 diff)
• DBGFAll.cpp (modified) (1 diff)
• IEMAll.cpp (modified) (1 diff)
• IEMAllCImpl.cpp.h (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -2202 +2202 @@
          * Straight forward code, not optimized/minimized in any way.
          */
-        RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
+        RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
 
         /* bp 0 */

trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp

@@ -35 +35 @@
 VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
 {
-    RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
+    RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
     PDBGFBP     pBp = &pVM->dbgf.s.aHwBreakpoints[0];
     unsigned    cLeft = RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints);

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -8460 +8460 @@
         CHECK_FIELD(dr[3]);
         CHECK_FIELD(dr[6]);
-        if ((pOrgCtx->dr[7] & ~X86_DR7_MB1_MASK) != (pDebugCtx->dr[7] & ~X86_DR7_MB1_MASK)) /* REM 'mov drX,greg' bug.*/
+        if ((pOrgCtx->dr[7] & ~X86_DR7_RA1_MASK) != (pDebugCtx->dr[7] & ~X86_DR7_RA1_MASK)) /* REM 'mov drX,greg' bug.*/
             CHECK_FIELD(dr[7]);
         CHECK_FIELD(gdtr.cbGdt);

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -3836 +3836 @@
         case 4:
             drX = pCtx->dr[6];
-            drX &= ~RT_BIT_32(12);
-            drX |= UINT32_C(0xffff0ff0);
+            drX |= X86_DR6_RA1_MASK;
+            drX &= ~X86_DR6_RAZ_MASK;
             break;
         case 7:
         case 5:
             drX = pCtx->dr[7];
-            drX &= ~(RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(14) | RT_BIT_32(15));
-            drX |= RT_BIT_32(10);
+            drX |=X86_DR7_RA1_MASK;
+            drX &= ~X86_DR7_RAZ_MASK;
             break;
         IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
@@ -3875 +3875 @@
     Assert(!pCtx->eflags.Bits.u1VM);
 
-    if (   (iDrReg == 4 || iDrReg == 5)
-        && (pCtx->cr4 & X86_CR4_DE) )
-    {
-        Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
-        return iemRaiseGeneralProtectionFault0(pIemCpu);
+    if (iDrReg == 4 || iDrReg == 5)
+    {
+        if (pCtx->cr4 & X86_CR4_DE)
+        {
+            Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
+            return iemRaiseGeneralProtectionFault0(pIemCpu);
+        }
+        iDrReg += 2;
     }
 
@@ -3913 +3916 @@
 
         case 6:
-        case 4:
-            if (uNewDrX & UINT64_C(0xffffffff00000000))
+            if (uNewDrX & X86_DR6_MBZ_MASK)
             {
                 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
                 return iemRaiseGeneralProtectionFault0(pIemCpu);
             }
-            uNewDrX &= ~RT_BIT_32(12);
-            uNewDrX |= UINT32_C(0xffff0ff0);
+            uNewDrX |= X86_DR6_RA1_MASK;
+            uNewDrX &= ~X86_DR6_RAZ_MASK;
             break;
 
         case 7:
-        case 5:
-            if (uNewDrX & UINT64_C(0xffffffff00000000))
+            if (uNewDrX & X86_DR7_MBZ_MASK)
             {
                 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
                 return iemRaiseGeneralProtectionFault0(pIemCpu);
             }
-            uNewDrX &= ~(RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(14) | RT_BIT_32(15));
-            uNewDrX |= RT_BIT_32(10);
+            uNewDrX |= X86_DR7_RA1_MASK;
+            uNewDrX &= ~X86_DR7_RAZ_MASK;
             break;