VirtualBox

Changeset 47583 in vbox


Ignore:
Timestamp:
Aug 7, 2013 11:56:08 AM (11 years ago)
Author:
vboxsync
Message:

VMM/HM: Fix logging inconsistencies with hex prefixes.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r47512 r47583  
    978978    LogRel(("HM: Using VT-x implementation 2.0!\n"));
    979979#endif
    980     LogRel(("HM: Host CR4                      = %08X\n", pVM->hm.s.vmx.hostCR4));
    981     LogRel(("HM: MSR_IA32_FEATURE_CONTROL      = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
    982     LogRel(("HM: MSR_IA32_VMX_BASIC_INFO       = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
    983     LogRel(("HM: VMCS id                       = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
    984     LogRel(("HM: VMCS size                     = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
     980    LogRel(("HM: Host CR4                      = %#RX64\n", pVM->hm.s.vmx.hostCR4));
     981    LogRel(("HM: MSR_IA32_FEATURE_CONTROL      = %#RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
     982    LogRel(("HM: MSR_IA32_VMX_BASIC_INFO       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
     983    LogRel(("HM: VMCS id                       = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
     984    LogRel(("HM: VMCS size                     = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
    985985    LogRel(("HM: VMCS physical address limit   = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
    986     LogRel(("HM: VMCS memory type              = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
    987     LogRel(("HM: Dual-monitor treatment        = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
    988     LogRel(("HM: OUTS & INS instruction-info   = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.vmx_basic_info)));
    989     LogRel(("HM: Max resume loops              = %RX32\n", pVM->hm.s.cMaxResumeLoops));
    990 
    991     LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS    = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
     986    LogRel(("HM: VMCS memory type              = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
     987    LogRel(("HM: Dual-monitor treatment        = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
     988    LogRel(("HM: OUTS & INS instruction-info   = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.vmx_basic_info)));
     989    LogRel(("HM: Max resume loops              = %u\n", pVM->hm.s.cMaxResumeLoops));
     990
     991    LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS    = %#RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
    992992    val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
    993993    zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
    … …  
    997997    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
    998998
    999     LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS   = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
     999    LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS   = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
    10001000    val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
    10011001    zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
    … …  
    10231023    if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    10241024    {
    1025         LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2  = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
     1025        LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2  = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
    10261026        val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
    10271027        zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
    … …  
    10401040    }
    10411041
    1042     LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS       = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
     1042    LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
    10431043    val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
    10441044    zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
    … …  
    10511051    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
    10521052
    1053     LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS        = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
     1053    LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS        = %#RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
    10541054    val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
    10551055    zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
    … …  
    10671067    {
    10681068        val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
    1069         LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP     = %RX64\n", val));
     1069        LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP     = %#RX64\n", val));
    10701070        HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
    10711071        HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
    … …  
    10951095    }
    10961096
    1097     LogRel(("HM: MSR_IA32_VMX_MISC             = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
     1097    LogRel(("HM: MSR_IA32_VMX_MISC             = %#RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
    10981098    if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
    10991099    {
    1100         LogRel(("HM:    MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT        = %x\n",
     1100        LogRel(("HM:    MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT        = %#x\n",
    11011101                MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
    11021102    }
    11031103    else
    11041104    {
    1105         LogRel(("HM:    MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT        = %x - erratum detected, using %x instead\n",
     1105        LogRel(("HM:    MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT        = %#x - erratum detected, using %#x instead\n",
    11061106                MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
    11071107    }
    11081108
    1109     LogRel(("HM:    MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT   = %x\n", MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(pVM->hm.s.vmx.msr.vmx_misc)));
    1110     LogRel(("HM:    MSR_IA32_VMX_MISC_ACTIVITY_STATES        = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
    1111     LogRel(("HM:    MSR_IA32_VMX_MISC_CR3_TARGET             = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
    1112     LogRel(("HM:    MSR_IA32_VMX_MISC_MAX_MSR                = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
    1113     LogRel(("HM:    MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM   = %x\n", MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(pVM->hm.s.vmx.msr.vmx_misc)));
    1114     LogRel(("HM:    MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2     = %x\n", MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(pVM->hm.s.vmx.msr.vmx_misc)));
    1115     LogRel(("HM:    MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO    = %x\n", MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(pVM->hm.s.vmx.msr.vmx_misc)));
    1116     LogRel(("HM:    MSR_IA32_VMX_MISC_MSEG_ID                = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
     1109    LogRel(("HM:    MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT   = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(pVM->hm.s.vmx.msr.vmx_misc)));
     1110    LogRel(("HM:    MSR_IA32_VMX_MISC_ACTIVITY_STATES        = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
     1111    LogRel(("HM:    MSR_IA32_VMX_MISC_CR3_TARGET             = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
     1112    LogRel(("HM:    MSR_IA32_VMX_MISC_MAX_MSR                = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
     1113    LogRel(("HM:    MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM   = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(pVM->hm.s.vmx.msr.vmx_misc)));
     1114    LogRel(("HM:    MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2     = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(pVM->hm.s.vmx.msr.vmx_misc)));
     1115    LogRel(("HM:    MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO    = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(pVM->hm.s.vmx.msr.vmx_misc)));
     1116    LogRel(("HM:    MSR_IA32_VMX_MISC_MSEG_ID                = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
    11171117
    11181118    /* Paranoia */
    11191119    AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
    11201120
    1121     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0       = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
    1122     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1       = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
    1123     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0       = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
    1124     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1       = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
    1125     LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM        = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
    1126     LogRel(("HM:    MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX     = %x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(pVM->hm.s.vmx.msr.vmx_vmcs_enum)));
     1121    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
     1122    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
     1123    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
     1124    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
     1125    LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM        = %#RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
     1126    LogRel(("HM:    MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX     = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(pVM->hm.s.vmx.msr.vmx_vmcs_enum)));
    11271127
    11281128    val = pVM->hm.s.vmx.msr.vmx_vmfunc;
    11291129    if (val)
    11301130    {
    1131         LogRel(("HM: MSR_A32_VMX_VMFUNC            = %RX64\n", val));
     1131        LogRel(("HM: MSR_A32_VMX_VMFUNC            = %#RX64\n", val));
    11321132        HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
    11331133    }
    11341134
    1135     LogRel(("HM: APIC-access page physaddr     = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
     1135    LogRel(("HM: APIC-access page physaddr     = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
    11361136
    11371137    for (VMCPUID i = 0; i < pVM->cCpus; i++)
    11381138    {
    1139         LogRel(("HM: VCPU%3d: MSR bitmap physaddr  = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
    1140         LogRel(("HM: VCPU%3d: VMCS physaddr        = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
     1139        LogRel(("HM: VCPU%3d: MSR bitmap physaddr  = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
     1140        LogRel(("HM: VCPU%3d: VMCS physaddr        = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
    11411141    }
    11421142
    … …  
    12071207            rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
    12081208            AssertRCReturn(rc, rc);
    1209             LogRel(("HM: Real Mode TSS guest physaddr  = %RGp\n", GCPhys));
     1209            LogRel(("HM: Real Mode TSS guest physaddr  = %#RGp\n", GCPhys));
    12101210
    12111211            rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
    12121212            AssertRCReturn(rc, rc);
    1213             LogRel(("HM: Non-Paging Mode EPT CR3       = %RGp\n", GCPhys));
     1213            LogRel(("HM: Non-Paging Mode EPT CR3       = %#RGp\n", GCPhys));
    12141214        }
    12151215        else
    … …  
    12331233        LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
    12341234        for (VMCPUID i = 0; i < pVM->cCpus; i++)
    1235             LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError));
     1235            LogRel(("HM: CPU[%RU32] Last instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError));
    12361236        return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
    12371237    }
    … …  
    12791279    {
    12801280        LogRel(("HM: Nested paging enabled!\n"));
    1281         LogRel(("HM:    EPT root page physaddr     = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
     1281        LogRel(("HM:    EPT root page physaddr     = %#RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
    12821282        if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
    12831283            LogRel(("HM:    EPT flush type             = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
    … …  
    13901390    if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
    13911391        LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
    1392     LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
    1393     LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
    1394     LogRel(("HM: AMD HWCR MSR                      = %RX64\n", pVM->hm.s.svm.msrHwcr));
    1395     LogRel(("HM: AMD-V revision                    = %X\n", pVM->hm.s.svm.u32Rev));
    1396     LogRel(("HM: AMD-V max ASID                    = %RU32\n", pVM->hm.s.uMaxAsid));
    1397     LogRel(("HM: AMD-V features                    = %X\n", pVM->hm.s.svm.u32Features));
     1392    LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
     1393    LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
     1394    LogRel(("HM: AMD HWCR MSR                      = %#RX64\n", pVM->hm.s.svm.msrHwcr));
     1395    LogRel(("HM: AMD-V revision                    = %#x\n",    pVM->hm.s.svm.u32Rev));
     1396    LogRel(("HM: AMD-V max ASID                    = %RU32\n",  pVM->hm.s.uMaxAsid));
     1397    LogRel(("HM: AMD-V features                    = %#x\n",    pVM->hm.s.svm.u32Features));
    13981398
    13991399    /*
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