Changeset 47680 in vbox for trunk/src/VBox
- Timestamp:
- Aug 12, 2013 5:09:40 PM (11 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r47677 r47680 7598 7598 * Segment registers. 7599 7599 */ 7600 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);7601 7600 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE) 7602 7601 || !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID); … … 7706 7705 if (HMVMX_IS_64BIT_HOST_MODE()) 7707 7706 { 7708 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);7709 7707 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL); 7710 7708 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL); … … 7768 7766 if (HMVMX_IS_64BIT_HOST_MODE()) 7769 7767 { 7770 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);7771 7768 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL); 7772 7769 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL); … … 7785 7782 7786 7783 /* 7784 * TR. 7785 */ 7786 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID); 7787 /* 64-bit capable CPUs. */ 7788 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) 7789 if (HMVMX_IS_64BIT_HOST_MODE()) 7790 { 7791 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL); 7792 } 7793 #endif 7794 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST) 7795 { 7796 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */ 7797 VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID); 7798 } 7799 else 7800 { 7801 HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */ 7802 || pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/ 7803 VMX_IGS_TR_ATTR_TYPE_INVALID); 7804 } 7805 HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID); 7806 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID); 7807 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11-8 MBZ. */ 7808 HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff 7809 || !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID); 7810 HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000) 7811 || (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID); 7812 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE); 7813 7814 /* 7787 7815 * GDTR and IDTR. 7788 7816 */ … … 7819 7847 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */ 7820 7848 if ( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST) 7821 || !pCtx->cs.Attr.n.u1Long 7849 || !pCtx->cs.Attr.n.u1Long) 7822 7850 { 7823 7851 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
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