VirtualBox

Changeset 47705 in vbox


Ignore:
Timestamp:
Aug 13, 2013 6:10:30 PM (11 years ago)
Author:
vboxsync
Message:

VMM/HM: Log alignment.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r47681 r47705  
    976976
    977977    LogRel(("HM: Using VT-x implementation 2.0!\n"));
    978     LogRel(("HM: Host CR4                      = %#RX64\n", pVM->hm.s.vmx.hostCR4));
    979     LogRel(("HM: MSR_IA32_FEATURE_CONTROL      = %#RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
    980     LogRel(("HM: MSR_IA32_VMX_BASIC_INFO       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
    981     LogRel(("HM: VMCS id                       = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
    982     LogRel(("HM: VMCS size                     = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
    983     LogRel(("HM: VMCS physical address limit   = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
    984     LogRel(("HM: VMCS memory type              = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
    985     LogRel(("HM: Dual-monitor treatment        = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
    986     LogRel(("HM: OUTS & INS instruction-info   = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.vmx_basic_info)));
    987     LogRel(("HM: Max resume loops              = %u\n", pVM->hm.s.cMaxResumeLoops));
    988 
    989     LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS    = %#RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
     978    LogRel(("HM: Host CR4                        = %#RX64\n", pVM->hm.s.vmx.hostCR4));
     979    LogRel(("HM: MSR_IA32_FEATURE_CONTROL        = %#RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
     980    LogRel(("HM: MSR_IA32_VMX_BASIC_INFO         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
     981    LogRel(("HM: VMCS id                         = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
     982    LogRel(("HM: VMCS size                       = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
     983    LogRel(("HM: VMCS physical address limit     = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
     984    LogRel(("HM: VMCS memory type                = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
     985    LogRel(("HM: Dual-monitor treatment support  = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
     986    LogRel(("HM: OUTS & INS instruction-info     = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.vmx_basic_info)));
     987    LogRel(("HM: Max resume loops                = %u\n", pVM->hm.s.cMaxResumeLoops));
     988
     989    LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS      = %#RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
    990990    val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
    991991    zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
    … …  
    995995    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
    996996
    997     LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS   = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
     997    LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS     = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
    998998    val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
    999999    zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
    … …  
    10211021    if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    10221022    {
    1023         LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2  = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
     1023        LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2    = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
    10241024        val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
    10251025        zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
    … …  
    10381038    }
    10391039
    1040     LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
     1040    LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
    10411041    val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
    10421042    zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
    … …  
    10491049    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
    10501050
    1051     LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS        = %#RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
     1051    LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS          = %#RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
    10521052    val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
    10531053    zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
    … …  
    10651065    {
    10661066        val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
    1067         LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP     = %#RX64\n", val));
     1067        LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP       = %#RX64\n", val));
    10681068        HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
    10691069        HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
    … …  
    10931093    }
    10941094
    1095     LogRel(("HM: MSR_IA32_VMX_MISC             = %#RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
     1095    LogRel(("HM: MSR_IA32_VMX_MISC               = %#RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
    10961096    if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
    10971097    {
    … …  
    11171117    AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
    11181118
    1119     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
    1120     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
    1121     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
    1122     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1       = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
    1123     LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM        = %#RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
     1119    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
     1120    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
     1121    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
     1122    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
     1123    LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM          = %#RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
    11241124    LogRel(("HM:    MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX     = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(pVM->hm.s.vmx.msr.vmx_vmcs_enum)));
    11251125
    … …  
    11271127    if (val)
    11281128    {
    1129         LogRel(("HM: MSR_A32_VMX_VMFUNC            = %#RX64\n", val));
     1129        LogRel(("HM: MSR_A32_VMX_VMFUNC              = %#RX64\n", val));
    11301130        HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
    11311131    }
    11321132
    1133     LogRel(("HM: APIC-access page physaddr     = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
     1133    LogRel(("HM: APIC-access page physaddr       = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
    11341134
    11351135    for (VMCPUID i = 0; i < pVM->cCpus; i++)
    11361136    {
    1137         LogRel(("HM: VCPU%3d: MSR bitmap physaddr  = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
    1138         LogRel(("HM: VCPU%3d: VMCS physaddr        = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
     1137        LogRel(("HM: VCPU%3d: MSR bitmap physaddr    = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
     1138        LogRel(("HM: VCPU%3d: VMCS physaddr          = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
    11391139    }
    11401140
    … …  
    12051205            rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
    12061206            AssertRCReturn(rc, rc);
    1207             LogRel(("HM: Real Mode TSS guest physaddr  = %#RGp\n", GCPhys));
     1207            LogRel(("HM: Real Mode TSS guest physaddr    = %#RGp\n", GCPhys));
    12081208
    12091209            rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
    12101210            AssertRCReturn(rc, rc);
    1211             LogRel(("HM: Non-Paging Mode EPT CR3       = %#RGp\n", GCPhys));
     1211            LogRel(("HM: Non-Paging Mode EPT CR3         = %#RGp\n", GCPhys));
    12121212        }
    12131213        else
    … …  
    12771277    {
    12781278        LogRel(("HM: Nested paging enabled!\n"));
    1279         LogRel(("HM:    EPT root page physaddr     = %#RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
     1279        LogRel(("HM:    EPT root page physaddr       = %#RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
    12801280        if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
    1281             LogRel(("HM:    EPT flush type             = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
     1281            LogRel(("HM:    EPT flush type               = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
    12821282        else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
    1283             LogRel(("HM:    EPT flush type             = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
     1283            LogRel(("HM:    EPT flush type              = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
    12841284        else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
    1285             LogRel(("HM:    EPT flush type             = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
     1285            LogRel(("HM:    EPT flush type              = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
    12861286        else
    1287             LogRel(("HM:    EPT flush type             = %d\n", pVM->hm.s.vmx.enmFlushEpt));
     1287            LogRel(("HM:    EPT flush type              = %d\n", pVM->hm.s.vmx.enmFlushEpt));
    12881288
    12891289        if (pVM->hm.s.vmx.fUnrestrictedGuest)
    … …  
    13061306        LogRel(("HM: VPID enabled!\n"));
    13071307        if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
    1308             LogRel(("HM:    VPID flush type            = VMX_FLUSH_VPID_INDIV_ADDR\n"));
     1308            LogRel(("HM:    VPID flush type              = VMX_FLUSH_VPID_INDIV_ADDR\n"));
    13091309        else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
    1310             LogRel(("HM:    VPID flush type            = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
     1310            LogRel(("HM:    VPID flush type              = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
    13111311        else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
    1312             LogRel(("HM:    VPID flush type            = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
     1312            LogRel(("HM:    VPID flush type              = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
    13131313        else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
    1314             LogRel(("HM:    VPID flush type            = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
     1314            LogRel(("HM:    VPID flush type              = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
    13151315        else
    1316             LogRel(("HM:    VPID flush type            = %d\n", pVM->hm.s.vmx.enmFlushVpid));
     1316            LogRel(("HM:    VPID flush type              = %d\n", pVM->hm.s.vmx.enmFlushVpid));
    13171317    }
    13181318    else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
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