Changeset 47773 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Aug 15, 2013 2:53:40 PM (11 years ago)

Author:

vboxsync

Message:

VMM/HM: RunGuestCodeStep() Load should be Save, and some typos, cosmetics.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMR0.cpp (modified) (3 diffs)
• HMVMXR0.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMR0/HMR0.cpp

@@ -82 +82 @@
 {
     /** Per CPU globals. */
-    HMGLOBALCPUINFO                  aCpuInfo[RTCPUSET_MAX_CPUS];
+    HMGLOBALCPUINFO                 aCpuInfo[RTCPUSET_MAX_CPUS];
 
     /** @name Ring-0 method table for AMD-V and VT-x specific operations.
@@ -344 +344 @@
         || u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92  - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
         || u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86  - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
-        || u == UINT32_C(0x000106A0) /*?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
-        || u == UINT32_C(0x000106A1) /*?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
+        || u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
+        || u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
         || u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
         || u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
@@ -1644 +1644 @@
 VMMR0_INT_DECL(int)   HMR0TestSwitcher3264(PVM pVM)
 {
-    PVMCPU   pVCpu = &pVM->aCpus[0];
-    PCPUMCTX pCtx  = CPUMQueryGuestCtxPtr(pVCpu);
+    PVMCPU   pVCpu     = &pVM->aCpus[0];
+    PCPUMCTX pCtx      = CPUMQueryGuestCtxPtr(pVCpu);
     uint32_t aParam[5] = {0, 1, 2, 3, 4};
     int      rc;

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -5507 +5507 @@
      * If VT-x marks the segment as unusable, most other bits remain undefined:
      *    - For CS the L, D and G bits have meaning.
-     *    - For SS the DPL have meaning (it -is- the CPL for Intel and VBox).
+     *    - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
      *    - For the remaining data segments no bits are defined.
      *
-     * The present bit and the unused bit has been observed to be set at the
+     * The present bit and the unusable bit has been observed to be set at the
      * same time (the selector was supposed to invalid as we started executing
      * a V8086 interrupt in ring-0).
@@ -5517 +5517 @@
      * cleared.  Some of the other VBox code recognizes the unusable bit, but
      * AMD-V certainly don't, and REM doesn't really either.  So, to be on the
-     * safe side here we'll strip off P and other bits we don't care about.  If
-     * any code breaks because attr.u != 0 when Sel < 4, it should be fixed.
+     * safe side here, we'll strip off P and other bits we don't care about.  If
+     * any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
      *
      * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
@@ -5529 +5529 @@
         pSelReg->Attr.u &= X86DESCATTR_UNUSABLE | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
                          | X86DESCATTR_DPL | X86DESCATTR_TYPE | X86DESCATTR_DT;
+
         Log4(("hmR0VmxReadSegmentReg: Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Val, pSelReg->Attr.u));
 #ifdef DEBUG_bird
@@ -6193 +6194 @@
         pVCpu->hm.s.fClearTrapFlag = false;
     }
-/** @todo there seems to be issues with the resume flag when the monitor trap
- *        flag is pending without being used. Seen early in bios init when
- *        accessing APIC page in prot mode. */
+    /** @todo there seems to be issues with the resume flag when the monitor trap
+     *        flag is pending without being used. Seen early in bios init when
+     *        accessing APIC page in prot mode. */
 
     /* On our way back from ring-3 the following needs to be done. */
@@ -7491 +7492 @@
          * Otherwise, make sure one of the TFs gets set.
          */
-        int rc2 = hmR0VmxLoadGuestRip(pVCpu, pCtx);
-        rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pCtx);
+        int rc2 = hmR0VmxSaveGuestRip(pVCpu, pCtx);
+        rc2    |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pCtx);
         AssertRCReturn(rc2, rc2);
         if (   pCtx->rip    != uRipStart
@@ -7751 +7752 @@
         Assert(u32Val == pVCpu->hm.s.vmx.u32ProcCtls);
 #endif
-        const bool fLongModeGuest = !!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
+        bool const fLongModeGuest = !!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
 
         /*