Changeset 47788 in vbox
- Timestamp:
- Aug 16, 2013 9:00:23 AM (12 years ago)
- svn:sync-xref-src-repo-rev:
- 88049
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
-
VMMR3/EM.cpp (modified) (1 diff)
-
VMMR3/EMHM.cpp (modified) (12 diffs)
-
VMMR3/EMRaw.cpp (modified) (25 diffs)
-
include/EMHandleRCTmpl.h (modified) (2 diffs)
-
include/EMInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/EM.cpp
r47712 r47788 416 416 417 417 /* these should be considered for release statistics. */ 418 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction."); 419 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged."); 420 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead."); 421 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution."); 422 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution."); 423 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution."); 424 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing."); 425 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead."); 426 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution."); 427 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead."); 418 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction."); 419 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged."); 420 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead."); 421 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution."); 422 EM_REG_PROFILE(&pVCpu->em.s.StatIEMEmu, "/PROF/CPU%d/EM/IEMEmuSingle", "Profiling single instruction IEM execution."); 423 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution."); 424 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution."); 425 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing."); 426 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead."); 427 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution."); 428 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead."); 428 429 429 430 #endif /* VBOX_WITH_STATISTICS */ -
trunk/src/VBox/VMM/VMMR3/EMHM.cpp
r47671 r47788 61 61 * Internal Functions * 62 62 *******************************************************************************/ 63 DECLINLINE(int) emR3 ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);64 static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);65 static int emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);63 DECLINLINE(int) emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS); 64 static int emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu); 65 static int emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 66 66 67 67 #define EMHANDLERC_WITH_HM 68 #define emR3ExecuteInstruction emR3HmExecuteInstruction 69 #define emR3ExecuteIOInstruction emR3HmExecuteIOInstruction 68 70 #include "EMHandleRCTmpl.h" 69 70 71 #if defined(DEBUG) && defined(SOME_UNUSED_FUNCTIONS)72 73 /**74 * Steps hardware accelerated mode.75 *76 * @returns VBox status code.77 * @param pVM Pointer to the VM.78 * @param pVCpu Pointer to the VMCPU.79 */80 static int emR3HmStep(PVM pVM, PVMCPU pVCpu)81 {82 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM);83 84 int rc;85 PCPUMCTX pCtx = pVCpu->em.s.pCtx;86 # ifdef VBOX_WITH_RAW_MODE87 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));88 # endif89 90 /*91 * Check vital forced actions, but ignore pending interrupts and timers.92 */93 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)94 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))95 {96 rc = emR3HmForcedActions(pVM, pVCpu, pCtx);97 if (rc != VINF_SUCCESS)98 return rc;99 }100 /*101 * Set flags for single stepping.102 */103 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);104 105 /*106 * Single step.107 * We do not start time or anything, if anything we should just do a few nanoseconds.108 */109 do110 {111 rc = VMMR3HmRunGC(pVM, pVCpu);112 } while ( rc == VINF_SUCCESS113 || rc == VINF_EM_RAW_INTERRUPT);114 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);115 116 /*117 * Make sure the trap flag is cleared.118 * (Too bad if the guest is trying to single step too.)119 */120 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);121 122 /*123 * Deal with the return codes.124 */125 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);126 rc = emR3HmHandleRC(pVM, pVCpu, pCtx, rc);127 return rc;128 }129 130 131 static int emR3SingleStepExecHm(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)132 {133 int rc = VINF_SUCCESS;134 EMSTATE enmOldState = pVCpu->em.s.enmState;135 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HM;136 137 Log(("Single step BEGIN:\n"));138 for (uint32_t i = 0; i < cIterations; i++)139 {140 DBGFR3PrgStep(pVCpu);141 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");142 rc = emR3HmStep(pVM, pVCpu);143 if ( rc != VINF_SUCCESS144 || !HMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))145 break;146 }147 Log(("Single step END: rc=%Rrc\n", rc));148 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);149 pVCpu->em.s.enmState = enmOldState;150 return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;151 }152 153 #endif /* DEBUG */154 71 155 72 … … 249 166 */ 250 167 #ifdef LOG_ENABLED 251 static int emR3 ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix)168 static int emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix) 252 169 #else 253 static int emR3 ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)170 static int emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC) 254 171 #endif 255 172 { … … 260 177 NOREF(rcRC); 261 178 262 /*263 *264 * The simple solution is to use the recompiler.265 * The better solution is to disassemble the current instruction and266 * try handle as many as possible without using REM.267 *268 */269 270 179 #ifdef LOG_ENABLED 271 180 /* 272 * Disassemble the instruction if requested. 273 */ 181 * Log it. 182 */ 183 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp)); 274 184 if (pszPrefix) 275 185 { … … 277 187 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix); 278 188 } 279 #endif /* LOG_ENABLED */ 280 281 #if 0 282 /* Try our own instruction emulator before falling back to the recompiler. */ 283 DISCPUSTATE Cpu; 284 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU"); 285 if (RT_SUCCESS(rc)) 286 { 287 switch (Cpu.pCurInstr->uOpcode) 288 { 289 /* @todo we can do more now */ 290 case OP_MOV: 291 case OP_AND: 292 case OP_OR: 293 case OP_XOR: 294 case OP_POP: 295 case OP_INC: 296 case OP_DEC: 297 case OP_XCHG: 298 STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a); 299 rc = EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0); 300 if (RT_SUCCESS(rc)) 301 { 302 #ifdef EM_NOTIFY_HM 303 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM) 304 HMR3NotifyEmulated(pVCpu); 305 #endif 306 STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a); 307 return rc; 308 } 309 if (rc != VERR_EM_INTERPRETER) 310 AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc); 311 STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a); 312 break; 313 } 314 } 315 #endif /* 0 */ 316 STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a); 317 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp)); 189 #endif 190 191 /* 192 * Use IEM and fallback on REM if the functionality is missing. 193 * Once IEM gets mature enough, nothing should ever fall back. 194 */ 195 #if defined(VBOX_WITH_FIRST_IEM_STEP) || !defined(VBOX_WITH_REM) 196 STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a); 197 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); 198 STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a); 199 200 if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED 201 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED) 202 #endif 203 { 318 204 #ifdef VBOX_WITH_REM 319 EMRemLock(pVM); 320 /* Flush the recompiler TLB if the VCPU has changed. */ 321 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu) 322 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL); 323 pVM->em.s.idLastRemCpu = pVCpu->idCpu; 324 325 rc = REMR3EmulateInstruction(pVM, pVCpu); 326 EMRemUnlock(pVM); 327 #else 328 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM); 329 #endif 330 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a); 205 STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a); 206 # ifndef VBOX_WITH_FIRST_IEM_STEP 207 Log(("EMINS[rem]: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp)); 208 # elif defined(DEBUG_bird) 209 AssertFailed(); 210 # endif 211 EMRemLock(pVM); 212 /* Flush the recompiler TLB if the VCPU has changed. */ 213 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu) 214 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL); 215 pVM->em.s.idLastRemCpu = pVCpu->idCpu; 216 217 rc = REMR3EmulateInstruction(pVM, pVCpu); 218 EMRemUnlock(pVM); 219 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a); 220 #else /* !VBOX_WITH_REM */ 221 NOREF(pVM); 222 #endif /* !VBOX_WITH_REM */ 223 } 331 224 332 225 #ifdef EM_NOTIFY_HM … … 349 242 * @param rcGC GC return code 350 243 */ 351 DECLINLINE(int) emR3 ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)244 DECLINLINE(int) emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC) 352 245 { 353 246 #ifdef LOG_ENABLED 354 return emR3 ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);247 return emR3HmExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix); 355 248 #else 356 return emR3 ExecuteInstructionWorker(pVM, pVCpu, rcGC);249 return emR3HmExecuteInstructionWorker(pVM, pVCpu, rcGC); 357 250 #endif 358 251 } … … 365 258 * @param pVCpu Pointer to the VMCPU. 366 259 */ 367 static int emR3 ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)260 static int emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu) 368 261 { 369 262 PCPUMCTX pCtx = pVCpu->em.s.pCtx; … … 371 264 STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a); 372 265 373 /* Try to restart the io instruction that was refused in ring-0. */ 266 /* 267 * Try to restart the io instruction that was refused in ring-0. 268 */ 374 269 VBOXSTRICTRC rcStrict = HMR3RestartPendingIOInstr(pVM, pVCpu, pCtx); 375 270 if (IOM_SUCCESS(rcStrict)) … … 383 278 384 279 #ifdef VBOX_WITH_FIRST_IEM_STEP 385 /* Hand it over to the interpreter. */ 280 /* 281 * Hand it over to the interpreter. 282 */ 386 283 rcStrict = IEMExecOne(pVCpu); 387 LogFlow(("emR3 ExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));284 LogFlow(("emR3HmExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 388 285 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem); 389 286 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); … … 449 346 pCtx->rip += Cpu.cbInstr; 450 347 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); 451 LogFlow(("emR3 ExecuteIOInstruction: %Rrc 1\n", VBOXSTRICTRC_VAL(rcStrict)));348 LogFlow(("emR3HmExecuteIOInstruction: %Rrc 1\n", VBOXSTRICTRC_VAL(rcStrict))); 452 349 return VBOXSTRICTRC_TODO(rcStrict); 453 350 } … … 458 355 Assert(TRPMHasTrap(pVCpu)); 459 356 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); 460 LogFlow(("emR3 ExecuteIOInstruction: VINF_SUCCESS 2\n"));357 LogFlow(("emR3HmExecuteIOInstruction: VINF_SUCCESS 2\n")); 461 358 return VINF_SUCCESS; 462 359 } … … 466 363 { 467 364 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); 468 LogFlow(("emR3 ExecuteIOInstruction: %Rrc 3\n", VBOXSTRICTRC_VAL(rcStrict)));365 LogFlow(("emR3HmExecuteIOInstruction: %Rrc 3\n", VBOXSTRICTRC_VAL(rcStrict))); 469 366 return VBOXSTRICTRC_TODO(rcStrict); 470 367 } … … 473 370 474 371 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); 475 int rc3 = emR3 ExecuteInstruction(pVM, pVCpu, "IO: ");476 LogFlow(("emR3 ExecuteIOInstruction: %Rrc 4 (rc2=%Rrc, rc3=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict), rc2, rc3));372 int rc3 = emR3HmExecuteInstruction(pVM, pVCpu, "IO: "); 373 LogFlow(("emR3HmExecuteIOInstruction: %Rrc 4 (rc2=%Rrc, rc3=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict), rc2, rc3)); 477 374 return rc3; 478 375 #endif -
trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
r47421 r47788 59 59 * Internal Functions * 60 60 *******************************************************************************/ 61 static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);62 DECLINLINE(int) emR3 ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);63 static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);64 static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);65 static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);66 static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);67 static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);61 static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); 62 DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS); 63 static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu); 64 static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret); 65 static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu); 66 static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu); 67 static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu); 68 68 69 69 #define EMHANDLERC_WITH_PATM 70 #define emR3ExecuteInstruction emR3RawExecuteInstruction 71 #define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction 70 72 #include "EMHandleRCTmpl.h" 71 73 … … 264 266 */ 265 267 #ifdef LOG_ENABLED 266 static int emR3 ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)268 static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix) 267 269 #else 268 static int emR3 ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)270 static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC) 269 271 #endif 270 272 { … … 299 301 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) 300 302 { 301 Log(("emR3 ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));303 Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip)); 302 304 303 305 RTGCPTR pNewEip; … … 310 312 */ 311 313 case VINF_SUCCESS: 312 Log(("emR3 ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",314 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n", 313 315 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags)); 314 316 pCtx->eip = pNewEip; … … 321 323 */ 322 324 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n")); 323 return emR3 ExecuteInstruction(pVM, pVCpu, "PATCHIR");325 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR"); 324 326 } 325 327 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET) 326 328 { 327 329 /* special case: iret, that sets IF, detected a pending irq/event */ 328 return emR3 ExecuteInstruction(pVM, pVCpu, "PATCHIRET");330 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET"); 329 331 } 330 332 return VINF_EM_RESCHEDULE_REM; … … 334 336 */ 335 337 case VINF_PATCH_EMULATE_INSTR: 336 Log(("emR3 ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",338 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n", 337 339 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags)); 338 340 pCtx->eip = pNewEip; 339 return emR3 ExecuteInstruction(pVM, pVCpu, "PATCHIR");341 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR"); 340 342 341 343 /* … … 343 345 */ 344 346 case VERR_PATCH_DISABLED: 345 Log(("emR3 ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",347 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n", 346 348 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags)); 347 349 pCtx->eip = pNewEip; … … 352 354 */ 353 355 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n")); 354 return emR3 ExecuteInstruction(pVM, pVCpu, "PATCHIR");356 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR"); 355 357 } 356 358 return VINF_EM_RESCHEDULE_REM; … … 397 399 * @param rcGC GC return code 398 400 */ 399 DECLINLINE(int) emR3 ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)401 DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC) 400 402 { 401 403 #ifdef LOG_ENABLED 402 return emR3 ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);404 return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix); 403 405 #else 404 return emR3 ExecuteInstructionWorker(pVM, pVCpu, rcGC);406 return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC); 405 407 #endif 406 408 } … … 413 415 * @param pVCpu Pointer to the VMCPU. 414 416 */ 415 static int emR3 ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)417 static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu) 416 418 { 417 419 #ifdef VBOX_WITH_FIRST_IEM_STEP … … 420 422 /* Hand it over to the interpreter. */ 421 423 VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu); 422 LogFlow(("emR3 ExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));424 LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 423 425 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem); 424 426 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); … … 507 509 } 508 510 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); 509 return emR3 ExecuteInstruction(pVM, pVCpu, "IO: ");511 return emR3RawExecuteInstruction(pVM, pVCpu, "IO: "); 510 512 #endif 511 513 } … … 551 553 { 552 554 LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip)); 553 return emR3 PatchTrap(pVM, pVCpu, pCtx, rc);555 return emR3RawPatchTrap(pVM, pVCpu, pCtx, rc); 554 556 } 555 557 #endif … … 620 622 if (RT_SUCCESS(rc)) 621 623 return rc; 622 return emR3 ExecuteInstruction(pVM, pVCpu, "Monitor: ");624 return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: "); 623 625 } 624 626 } … … 642 644 rc = TRPMResetTrap(pVCpu); 643 645 AssertRC(rc); 644 return emR3 ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");646 return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: "); 645 647 } 646 648 } … … 728 730 729 731 /* go to the REM to emulate a single instruction */ 730 return emR3 ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");732 return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: "); 731 733 } 732 734 … … 741 743 * @param gcret GC return code. 742 744 */ 743 static int emR3 PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)745 static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret) 744 746 { 745 747 uint8_t u8TrapNo; … … 769 771 if (RT_FAILURE(rc)) 770 772 { 771 AssertReleaseMsgFailed(("emR3 PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));773 AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret)); 772 774 return rc; 773 775 } … … 828 830 } 829 831 #endif /* LOG_ENABLED */ 830 Log(("emR3 PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",832 Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n", 831 833 pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0)); 832 834 … … 841 843 { 842 844 /** @todo execute a whole block */ 843 Log(("emR3 PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));845 Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip)); 844 846 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF)) 845 Log(("emR3 PatchTrap: Virtual IF flag disabled!!\n"));847 Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n")); 846 848 847 849 pCtx->eip = pNewEip; … … 864 866 /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */ 865 867 866 return emR3 ExecuteInstruction(pVM, pVCpu, "PATCHIR");868 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR"); 867 869 /* Interrupts are enabled; just go back to the original instruction. 868 870 return VINF_SUCCESS; */ … … 875 877 */ 876 878 case VINF_PATCH_EMULATE_INSTR: 877 Log(("emR3 PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",879 Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n", 878 880 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags)); 879 881 pCtx->eip = pNewEip; 880 882 AssertRelease(pCtx->eip); 881 return emR3 ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");883 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: "); 882 884 883 885 /* … … 886 888 case VERR_PATCH_DISABLED: 887 889 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF)) 888 Log(("emR3 PatchTrap: Virtual IF flag disabled!!\n"));890 Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n")); 889 891 pCtx->eip = pNewEip; 890 892 AssertRelease(pCtx->eip); … … 896 898 */ 897 899 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n")); 898 return emR3 ExecuteInstruction(pVM, pVCpu, "PATCHIR");900 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR"); 899 901 } 900 902 return VINF_EM_RESCHEDULE_REM; … … 1153 1155 1154 1156 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) 1155 return emR3 PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);1156 1157 return emR3 ExecuteInstruction(pVM, pVCpu, "PRIV");1157 return emR3RawPatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP); 1158 1159 return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV"); 1158 1160 } 1159 1161 -
trunk/src/VBox/VMM/include/EMHandleRCTmpl.h
r47089 r47788 18 18 #ifndef ___EMHandleRCTmpl_h 19 19 #define ___EMHandleRCTmpl_h 20 21 #if defined(EMHANDLERC_WITH_PATM) && defined(EMHANDLERC_WITH_HM) 22 # error "Only one define" 23 #endif 24 20 25 21 26 /** … … 82 87 case VINF_PATM_PATCH_TRAP_PF: 83 88 case VINF_PATM_PATCH_INT3: 84 rc = emR3 PatchTrap(pVM, pVCpu, pCtx, rc);89 rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc); 85 90 break; 86 91 -
trunk/src/VBox/VMM/include/EMInternal.h
r47421 r47788 412 412 STAMPROFILEADV StatHmEntry; 413 413 STAMPROFILE StatHmExec; 414 STAMPROFILE StatIEMEmu; 414 415 STAMPROFILE StatREMEmu; 415 416 STAMPROFILE StatREMExec;
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