Changeset 47876 in vbox

Timestamp:

Aug 20, 2013 8:02:48 AM (12 years ago)

Author:

vboxsync

Message:

kmk incs

Location:

trunk/include

Files:

• VBox/apic.mac (modified) (1 diff)
• VBox/err.mac (modified) (4 diffs)
• iprt/x86.mac (modified) (4 diffs)

trunk/include/VBox/apic.mac

@@ -17 +17 @@
 %define APIC_REG_LVT_LEVEL_TRIGGER              RT_BIT(15)
 %define APIC_REG_LVT_MASKED                     RT_BIT(16)
+%ifdef ___iprt_asm_amd64_x86_h
 %endif
+%endif

trunk/include/VBox/err.mac

@@ -71 +71 @@
 %define VERR_EM_UNEXPECTED_MAPPING_CONFLICT    (-1154)
 %define VINF_EM_TRIPLE_FAULT    1155
+%define VERR_EM_CANNOT_EXEC_GUEST    (-1156)
 %define VERR_DBGF_NOT_ATTACHED    (-1200)
 %define VERR_DBGF_ALREADY_ATTACHED    (-1201)
@@ -207 +208 @@
 %define VERR_PGM_PHYS_NULL_PAGE_PARAM    (-1681)
 %define VERR_PGM_PCI_PASSTHRU_MISCONFIG    (-1682)
+%define VERR_PGM_TOO_MANY_MMIO2_RANGES    (-1683)
+%define VERR_PGM_PHYS_PAGE_MAP_MMIO2_IPE    (-1684)
 %define VERR_MM_RAM_CONFLICT    (-1700)
 %define VERR_MM_HYPER_NO_MEMORY    (-1701)
@@ -709 +712 @@
 %define VERR_VMX_VMPTRLD_FAILED    (-4021)
 %define VERR_VMX_INVALID_VMCS_PTR_TO_START_VM    (-4022)
+%define VERR_HMVMX_IPE_1    (-4023)
+%define VERR_HMVMX_IPE_2    (-4024)
+%define VERR_HMVMX_IPE_3    (-4025)
+%define VERR_HMVMX_IPE_4    (-4026)
+%define VERR_HMVMX_IPE_5    (-4027)
 %define VERR_SVM_UNABLE_TO_START_VM    (-4050)
 %define VERR_SVM_ILLEGAL_EFER_MSR    (-4051)
@@ -786 +794 @@
 %define VERR_GVMM_IPE_2    (-5204)
 %define VERR_IEM_INSTR_NOT_IMPLEMENTED    (-5300)
+%define VERR_IEM_INVALID_OPERAND_SIZE    (-5301)
+%define VERR_IEM_INVALID_ADDRESS_MODE    (-5302)
+%define VERR_IEM_INVALID_EFF_SEG    (-5303)
+%define VERR_IEM_INVALID_INSTR_LENGTH    (-5304)
+%define VINF_IEM_SELECTOR_NOT_OK    (5305)
 %define VERR_IEM_ASPECT_NOT_IMPLEMENTED    (-5391)
 %define VERR_IEM_IPE_1    (-5392)

trunk/include/iprt/x86.mac

@@ -30 +30 @@
 %define X86_EFL_VIP         RT_BIT(20)
 %define X86_EFL_ID          RT_BIT(21)
+%define X86_EFL_LIVE_MASK   0x003f7fd5
+%define X86_EFL_RA1_MASK    RT_BIT_32(1)
 %define X86_EFL_IOPL_SHIFT  12
 %define X86_EFL_GET_IOPL(efl)   (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
@@ -224 +226 @@
 %define X86_DR7_LE                          RT_BIT(8)
 %define X86_DR7_GE                          RT_BIT(9)
+%define X86_DR7_LE_ALL                      0x0000000000000055
+%define X86_DR7_GE_ALL                      0x00000000000000aa
 %define X86_DR7_GD                          RT_BIT(13)
 %define X86_DR7_RW0_MASK                    (3 << 16)
@@ -255 +259 @@
 %define X86_DR7_GET_LEN(uDR7, iBp)          ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
 %define X86_DR7_ENABLED_MASK                0x000000ff
+%define X86_DR7_LEN_ALL_MASKS               0xcccc0000
+%define X86_DR7_RW_LEN_ALL_MASKS            0xffff0000
 %define X86_DR7_INIT_VAL                    0x400
 %define MSR_IA32_TSC                        0x10
 %define MSR_IA32_PLATFORM_ID                0x17
 %ifndef MSR_IA32_APICBASE
-%define MSR_IA32_APICBASE                   0x1b
+ %define MSR_IA32_APICBASE                  0x1b
+ %define MSR_IA32_APICBASE_EN               RT_BIT_64(11)
+ %define MSR_IA32_APICBASE_EXTD             RT_BIT_64(10)
+ %define MSR_IA32_APICBASE_BSP              RT_BIT_64(8)
+ %define MSR_IA32_APICBASE_BASE_MIN         0x0000000ffffff000
 %endif
 %define MSR_IA32_FEATURE_CONTROL            0x3A
@@ -584 +594 @@
 %define X86DESCATTR_DPL             0x00000060
 %define X86DESCATTR_DPL_SHIFT       5
-%define X86DESCATTR_P               0x00000800
+%define X86DESCATTR_P               0x00000080
 %define X86DESCATTR_LIMIT_HIGH      0x00000f00
 %define X86DESCATTR_AVL             0x00001000