Changeset 48127 in vbox for trunk/src/VBox

Timestamp:

Aug 28, 2013 2:48:16 PM (11 years ago)

Author:

vboxsync

Message:

IEM: Started on 64-bit ops on 32-bit hosts.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllAImpl.asm (modified) (15 diffs)
• IEMAllAImplC.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -355 +355 @@
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
- %else ; stub it for now - later, replace with hand coded stuff.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
-        int3
-        ret
-ENDPROC iemAImpl_ %+ %1 %+ _u64
-  %endif ; !RT_ARCH_AMD64
+  %endif ; RT_ARCH_AMD64
 
  %if %2 != 0 ; locked versions requested?
@@ -396 +391 @@
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
-  %else ; stub it for now - later, replace with hand coded stuff.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
-        int3
-        ret 8
-ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
-  %endif ; !RT_ARCH_AMD64
+  %endif ; RT_ARCH_AMD64
  %endif ; locked
 %endmacro
@@ -458 +448 @@
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
- %else ; stub it for now - later, replace with hand coded stuff.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
-        int3
-        ret 8
-ENDPROC iemAImpl_ %+ %1 %+ _u64
-  %endif ; !RT_ARCH_AMD64
+  %endif ; RT_ARCH_AMD64
 
  %if %2 != 0 ; locked versions requested?
@@ -491 +476 @@
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
-  %else ; stub it for now - later, replace with hand coded stuff.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
-        int3
-        ret 8
-ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
-  %endif ; !RT_ARCH_AMD64
+  %endif ; RT_ARCH_AMD64
  %endif ; locked
 %endmacro
@@ -552 +532 @@
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
- %else ; stub it for now - later, replace with hand coded stuff.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
-        int3
-        ret 8
-ENDPROC iemAImpl_ %+ %1 %+ _u64
- %endif ; !RT_ARCH_AMD64
+ %endif ; RT_ARCH_AMD64
 %endmacro
 IEMIMPL_BIT_OP bsf, (X86_EFL_ZF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF)
@@ -586 +561 @@
 ENDPROC iemAImpl_imul_two_u32
 
+%ifdef RT_ARCH_AMD64
 BEGINPROC_FASTCALL iemAImpl_imul_two_u64, 16
         PROLOGUE_3_ARGS
-%ifdef RT_ARCH_AMD64
         IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
         imul    A1, qword [A0]
         mov     [A0], A1
         IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
-%else
-        int3 ;; @todo implement me
-%endif
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_imul_two_u64
+%endif ; RT_ARCH_AMD64
 
 
@@ -631 +604 @@
 ENDPROC iemAImpl_xchg_u32
 
+%ifdef RT_ARCH_AMD64
 BEGINPROC_FASTCALL iemAImpl_xchg_u64, 8
-%ifdef RT_ARCH_AMD64
         PROLOGUE_2_ARGS
         mov     T0, [A1]
@@ -638 +611 @@
         mov     [A1], T0
         EPILOGUE_2_ARGS
-%else
-        int3
-        ret 0
+ENDPROC iemAImpl_xchg_u64
 %endif
-ENDPROC iemAImpl_xchg_u64
 
 
@@ -683 +653 @@
 ENDPROC iemAImpl_xadd_u32
 
+%ifdef RT_ARCH_AMD64
 BEGINPROC_FASTCALL iemAImpl_xadd_u64, 12
-%ifdef RT_ARCH_AMD64
         PROLOGUE_3_ARGS
         IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
@@ -692 +662 @@
         IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
         EPILOGUE_3_ARGS
-%else
-        int3
-        ret 4
-%endif
 ENDPROC iemAImpl_xadd_u64
+%endif ; RT_ARCH_AMD64
 
 BEGINPROC_FASTCALL iemAImpl_xadd_u8_locked, 12
@@ -728 +695 @@
 ENDPROC iemAImpl_xadd_u32_locked
 
+%ifdef RT_ARCH_AMD64
 BEGINPROC_FASTCALL iemAImpl_xadd_u64_locked, 12
-%ifdef RT_ARCH_AMD64
         PROLOGUE_3_ARGS
         IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
@@ -737 +704 @@
         IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
         EPILOGUE_3_ARGS
-%else
-        int3
-        ret 4
-%endif
 ENDPROC iemAImpl_xadd_u64_locked
+%endif ; RT_ARCH_AMD64
 
 
@@ -1017 +981 @@
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
- %else
-        ; stub them for now.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 8
-        int3
-        ret 0
-ENDPROC iemAImpl_ %+ %1 %+ _u64
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 8
-        int3
-        ret 0
-ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
- %endif
+ %endif ; RT_ARCH_AMD64
 
 %endmacro
@@ -1141 +1095 @@
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u64
- %else ; stub it for now - later, replace with hand coded stuff.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
-        int3
-        ret 4
-ENDPROC iemAImpl_ %+ %1 %+ _u64
-  %endif ; !RT_ARCH_AMD64
+ %endif ; RT_ARCH_AMD64
 
 %endmacro
@@ -1221 +1170 @@
         EPILOGUE_4_ARGS_EX 12
 ENDPROC iemAImpl_ %+ %1 %+ _u64
- %else ; stub it for now - later, replace with hand coded stuff.
-BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
-        int3
-        ret 12
-ENDPROC iemAImpl_ %+ %1 %+ _u64
-  %endif ; !RT_ARCH_AMD64
+ %endif ; RT_ARCH_AMD64
 
 %endmacro

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -26 +26 @@
 #ifdef RT_ARCH_X86
 /*
- * There are a few 64-bit on 32-bit things we'd rather do in C.
+ * There are a few 64-bit on 32-bit things we'd rather do in C.  Actually, doing
+ * it all in C is probably safer atm., optimize what's necessary later, maybe.
  */
 
 
-IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Factor, uint32_t *pEFlags))
+/* Binary ops */
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+/** 64-bit locked binary operand operation. */
+# define DO_LOCKED_BIN_OP_U64(a_Mnemonic) \
+    do { \
+        uint64_t uOld = ASMAtomicReadU64(puDst); \
+        uint64_t uTmp; \
+        uint32_t fEflTmp; \
+        do \
+        { \
+            uTmp = uOld; \
+            fEflTmp = *pfEFlags; \
+            iemAImpl_ ## a_Mnemonic ## _u64(&uTmp, uSrc, &fEflTmp); \
+        } while (ASMAtomicCmpXchgExU64(puDst, uTmp, uOld, &uOld)); \
+        *pfEFlags = fEflTmp; \
+    } while (0)
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(adc);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(adc);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(sub);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(sbb);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(or);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(xor);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(and);
+}
+
+
+/* Bit operations (same signature as above). */
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    /* Note! "undefined" flags: OF, SF, ZF, AF, PF. */
+    Assert(uSrc < 64);
+    if (*puDst & RT_BIT_64(uSrc))
+        *pfEFlags |= X86_EFL_CF;
+    else
+        *pfEFlags &= ~X86_EFL_CF;
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    /* Note! "undefined" flags: OF, SF, ZF, AF, PF. */
+    Assert(uSrc < 64);
+    uint64_t fMask = RT_BIT_64(uSrc);
+    if (*puDst & fMask)
+    {
+        *puDst    &= ~fMask;
+        *pfEFlags |= X86_EFL_CF;
+    }
+    else
+    {
+        *puDst    |= ~fMask;
+        *pfEFlags &= ~X86_EFL_CF;
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    /* Note! "undefined" flags: OF, SF, ZF, AF, PF. */
+    uint64_t fMask = RT_BIT_64(uSrc);
+    if (*puDst & fMask)
+        *pfEFlags |= X86_EFL_CF;
+    else
+        *pfEFlags &= ~X86_EFL_CF;
+    *puDst &= ~fMask;
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    /* Note! "undefined" flags: OF, SF, ZF, AF, PF. */
+    uint64_t fMask = RT_BIT_64(uSrc);
+    if (*puDst & fMask)
+        *pfEFlags |= X86_EFL_CF;
+    else
+        *pfEFlags &= ~X86_EFL_CF;
+    *puDst |= fMask;
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(btc);
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(btr);
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64_locked,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    DO_LOCKED_BIN_OP_U64(bts);
+}
+
+
+/* bit scan */
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
+    if (uSrc)
+    {
+        uint8_t  iBit;
+        uint32_t u32Src;
+        if (uSrc & UINT32_MAX)
+        {
+            iBit = 0;
+            u32Src = uSrc;
+        }
+        else
+        {
+            iBit = 32;
+            u32Src = uSrc >> 32;
+        }
+        if (!(u32Src & UINT16_MAX))
+        {
+            iBit += 16;
+            u32Src >>= 16;
+        }
+        if (!(u32Src & UINT8_MAX))
+        {
+            iBit += 8;
+            u32Src >>= 8;
+        }
+        if (!(u32Src & 0xf))
+        {
+            iBit += 4;
+            u32Src >>= 4;
+        }
+        if (!(u32Src & 0x3))
+        {
+            iBit += 2;
+            u32Src >>= 2;
+        }
+        if (!(u32Src & 1))
+        {
+            iBit += 1;
+            Assert(u32Src & 2);
+        }
+
+        *puDst     = iBit;
+        *pfEFlags &= ~X86_EFL_ZF;
+    }
+    else
+        *pfEFlags |= X86_EFL_ZF;
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
+    if (uSrc)
+    {
+        uint8_t  iBit;
+        uint32_t u32Src;
+        if (uSrc & UINT64_C(0xffffffff00000000))
+        {
+            iBit = 64;
+            u32Src = uSrc >> 32;
+        }
+        else
+        {
+            iBit = 32;
+            u32Src = uSrc;
+        }
+        if (!(u32Src & UINT32_C(0xffff0000)))
+        {
+            iBit -= 16;
+            u32Src <<= 16;
+        }
+        if (!(u32Src & UINT32_C(0xff000000)))
+        {
+            iBit -= 8;
+            u32Src <<= 8;
+        }
+        if (!(u32Src & UINT32_C(0xf0000000)))
+        {
+            iBit -= 4;
+            u32Src <<= 4;
+        }
+        if (!(u32Src & UINT32_C(0xc0000000)))
+        {
+            iBit -= 2;
+            u32Src <<= 2;
+        }
+        if (!(u32Src & UINT32_C(0x10000000)))
+        {
+            iBit -= 1;
+            u32Src <<= 1;
+            Assert(u32Src & RT_BIT_64(63));
+        }
+
+        *puDst     = iBit;
+        *pfEFlags &= ~X86_EFL_ZF;
+    }
+    else
+        *pfEFlags |= X86_EFL_ZF;
+}
+
+
+/* Unary operands. */
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64,(uint64_t  *puDst,  uint32_t *pEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64,(uint64_t  *puDst,  uint32_t *pEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64,(uint64_t  *puDst,  uint32_t *pEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64,(uint64_t  *puDst,  uint32_t *pEFlags))
+{
+    AssertFailed();
+}
+
+
+/** 64-bit locked unary operand operation. */
+# define DO_LOCKED_UNARY_OP_U64(a_Mnemonic) \
+    do { \
+        uint64_t uOld = ASMAtomicReadU64(puDst); \
+        uint64_t uTmp; \
+        uint32_t fEflTmp; \
+        do \
+        { \
+            uTmp = uOld; \
+            fEflTmp = *pfEFlags; \
+            iemAImpl_ ## a_Mnemonic ## _u64(&uTmp, &fEflTmp); \
+        } while (ASMAtomicCmpXchgExU64(puDst, uTmp, uOld, &uOld)); \
+        *pfEFlags = fEflTmp; \
+    } while (0)
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64_locked,(uint64_t  *puDst,  uint32_t *pfEFlags))
+{
+    DO_LOCKED_UNARY_OP_U64(inc);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64_locked,(uint64_t  *puDst,  uint32_t *pfEFlags))
+{
+    DO_LOCKED_UNARY_OP_U64(dec);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64_locked,(uint64_t  *puDst,  uint32_t *pfEFlags))
+{
+    DO_LOCKED_UNARY_OP_U64(not);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64_locked,(uint64_t  *puDst,  uint32_t *pfEFlags))
+{
+    DO_LOCKED_UNARY_OP_U64(neg);
+}
+
+
+/* Shift and rotate. */
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_rcl_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_rcr_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_shl_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_shr_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_sar_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_shld_u64,(uint64_t *puDst, uint64_t uSrc, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_shrd_u64,(uint64_t *puDst, uint64_t uSrc, uint8_t cShift, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+/* multiplication and division */
+
+IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Factor, uint32_t *pfEFlags))
 {
     AssertFailed();
@@ -37 +447 @@
 
 
-IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Factor, uint32_t *pEFlags))
+IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Factor, uint32_t *pfEFlags))
 {
     AssertFailed();
@@ -44 +454 @@
 
 
-IEM_DECL_IMPL_DEF(int, iemAImpl_div_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Divisor, uint32_t *pEFlags))
+IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+
+IEM_DECL_IMPL_DEF(int, iemAImpl_div_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Divisor, uint32_t *pfEFlags))
 {
     AssertFailed();
@@ -51 +468 @@
 
 
-IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Divisor, uint32_t *pEFlags))
+IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64Divisor, uint32_t *pfEFlags))
 {
     AssertFailed();
     return -1;
 }
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t *puMem, uint64_t *puReg))
+{
+    /* XCHG implies LOCK. */
+    uint64_t uOldMem = *puMem;
+    while (!ASMAtomicCmpXchgExU64(puMem, *puReg, uOldMem, &uOldMem))
+        ASMNopPause();
+    *puReg = uOldMem;
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *puDst, uint64_t *puReg, uint32_t *pfEFlags))
+{
+    AssertFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *puDst, uint64_t *puReg, uint32_t *pfEFlags))
+{
+    uint64_t uOld = ASMAtomicReadU64(puDst);
+    uint64_t uTmpDst;
+    uint64_t uTmpReg;
+    uint32_t fEflTmp;
+    do
+    {
+        uTmpDst = uOld;
+        uTmpReg = *puReg;
+        fEflTmp = *pfEFlags;
+        iemAImpl_xadd_u64(&uTmpDst, &uTmpReg, &fEflTmp);
+    } while (ASMAtomicCmpXchgExU64(puDst, uTmpDst, uOld, &uOld));
+    *puReg    = uTmpReg;
+    *pfEFlags = fEflTmp;
+}
+
 
 #endif /* RT_ARCH_X86 */