Changeset 48141 in vbox for trunk/src/VBox

Timestamp:

Aug 29, 2013 9:42:59 AM (11 years ago)

Author:

vboxsync

Message:

QNX doesn't believe our MTRR_CAP report and messes with the variable MTRR ranges. Fake 6 of them for now.

File:

• trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -958 +958 @@
         }
 
+        case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
+        case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
+        case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
+        case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
+        case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
+        case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
+            /** @todo implement variable MTRRs. */
+            *puValue = 0;
+            break;
+#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
+        case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
+        case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
+        case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
+        case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
+            *puValue = 0;
+            break;
+#endif
+
         case MSR_IA32_MTRR_DEF_TYPE:
             *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
@@ -1266 +1284 @@
             pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
             break;
+
+        case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
+        case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
+        case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
+        case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
+        case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
+        case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
+            /** @todo implement variable MTRRs. */
+            break;
+#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
+        case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
+        case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
+        case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
+        case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
+            break;
+#endif
 
         case IA32_MTRR_FIX64K_00000: