VirtualBox

Changeset 48216 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
Aug 31, 2013 6:47:14 PM (11 years ago)
Author:
vboxsync
Message:

VMM/HM: Cleanup.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r48213 r48216  
    896896    {
    897897        LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
    898         LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl));
     898        LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
    899899        switch (pVM->hm.s.lLastError)
    900900        {
    … …  
    969969
    970970    Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
    971     AssertLogRelReturn(pVM->hm.s.vmx.msr.u64FeatureCtrl != 0, VERR_HM_IPE_4);
     971    AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
    972972
    973973    uint64_t    val;
    … …  
    977977    LogRel(("HM: Using VT-x implementation 2.0!\n"));
    978978    LogRel(("HM: Host CR4                        = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
    979     LogRel(("HM: MSR_IA32_FEATURE_CONTROL        = %#RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl));
    980     LogRel(("HM: MSR_IA32_VMX_BASIC_INFO         = %#RX64\n", pVM->hm.s.vmx.msr.u64BasicInfo));
    981     LogRel(("HM:   VMCS id                             = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo)));
    982     LogRel(("HM:   VMCS size                           = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.u64BasicInfo)));
    983     LogRel(("HM:   VMCS physical address limit         = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.u64BasicInfo) ? "< 4 GB" : "None"));
    984     LogRel(("HM:   VMCS memory type                    = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.u64BasicInfo)));
    985     LogRel(("HM:   Dual-monitor treatment support      = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.u64BasicInfo)));
    986     LogRel(("HM:   OUTS & INS instruction-info         = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.u64BasicInfo)));
     979    LogRel(("HM: MSR_IA32_FEATURE_CONTROL        = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
     980    LogRel(("HM: MSR_IA32_VMX_BASIC_INFO         = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
     981    LogRel(("HM:   VMCS id                             = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     982    LogRel(("HM:   VMCS size                           = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     983    LogRel(("HM:   VMCS physical address limit         = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
     984    LogRel(("HM:   VMCS memory type                    = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     985    LogRel(("HM:   Dual-monitor treatment support      = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     986    LogRel(("HM:   OUTS & INS instruction-info         = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
    987987    LogRel(("HM: Max resume loops                = %u\n", pVM->hm.s.cMaxResumeLoops));
    988988
    989     LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS      = %#RX64\n", pVM->hm.s.vmx.msr.VmxPinCtls.u));
    990     val = pVM->hm.s.vmx.msr.VmxPinCtls.n.allowed1;
    991     zap = pVM->hm.s.vmx.msr.VmxPinCtls.n.disallowed0;
     989    LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS      = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
     990    val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
     991    zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
    992992    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
    993993    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
    … …  
    995995    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
    996996
    997     LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS     = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls.u));
    998     val = pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1;
    999     zap = pVM->hm.s.vmx.msr.VmxProcCtls.n.disallowed0;
     997    LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS     = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
     998    val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
     999    zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
    10001000    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
    10011001    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
    … …  
    10191019    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
    10201020    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
    1021     if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    1022     {
    1023         LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2    = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls2.u));
    1024         val = pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1;
    1025         zap = pVM->hm.s.vmx.msr.VmxProcCtls2.n.disallowed0;
     1021    if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
     1022    {
     1023        LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2    = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
     1024        val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
     1025        zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
    10261026        HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
    10271027        HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
    … …  
    10381038    }
    10391039
    1040     LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS         = %#RX64\n", pVM->hm.s.vmx.msr.VmxEntry.u));
    1041     val = pVM->hm.s.vmx.msr.VmxEntry.n.allowed1;
    1042     zap = pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0;
     1040    LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS         = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
     1041    val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
     1042    zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
    10431043    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
    10441044    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
    … …  
    10491049    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
    10501050
    1051     LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS          = %#RX64\n", pVM->hm.s.vmx.msr.VmxExit.u));
    1052     val = pVM->hm.s.vmx.msr.VmxExit.n.allowed1;
    1053     zap = pVM->hm.s.vmx.msr.VmxExit.n.disallowed0;
     1051    LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS          = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
     1052    val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
     1053    zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
    10541054    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
    10551055    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
    … …  
    10621062    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
    10631063
    1064     if (pVM->hm.s.vmx.msr.u64EptVpidCaps)
    1065     {
    1066         val = pVM->hm.s.vmx.msr.u64EptVpidCaps;
     1064    if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
     1065    {
     1066        val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
    10671067        LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP       = %#RX64\n", val));
    10681068        HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
    … …  
    10931093    }
    10941094
    1095     val = pVM->hm.s.vmx.msr.u64Misc;
     1095    val = pVM->hm.s.vmx.Msrs.u64Misc;
    10961096    LogRel(("HM: MSR_IA32_VMX_MISC               = %#RX64\n", val));
    10971097    if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
    … …  
    11131113
    11141114    /* Paranoia */
    1115     AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.u64Misc) >= 512);
    1116 
    1117     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed0));
    1118     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed1));
    1119     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed0));
    1120     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed1));
    1121 
    1122     val = pVM->hm.s.vmx.msr.u64VmcsEnum;
     1115    AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
     1116
     1117    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0         = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
     1118    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1         = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
     1119    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0         = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
     1120    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1         = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
     1121
     1122    val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
    11231123    LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM          = %#RX64\n", val));
    11241124    LogRel(("HM:   MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX   = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
    11251125
    1126     val = pVM->hm.s.vmx.msr.u64Vmfunc;
     1126    val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
    11271127    if (val)
    11281128    {
    … …  
    11391139    }
    11401140
    1141     if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
     1141    if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
    11421142        pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
    11431143
    1144     if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
     1144    if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
    11451145        pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
    11461146
    … …  
    11501150     * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
    11511151     */
    1152     if (   !(pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
     1152    if (   !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    11531153        && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
    11541154    {
    … …  
    11601160    if (    pVM->hm.s.vmx.fAllowUnrestricted
    11611161        &&  pVM->hm.s.fNestedPaging
    1162         &&  (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
     1162        &&  (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
    11631163    {
    11641164        pVM->hm.s.vmx.fUnrestrictedGuest = true;
    … …  
    25632563
    25642564        /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
    2565         mask = (uint32_t)pVM->hm.s.vmx.msr.u64Cr0Fixed0;
     2565        mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
    25662566        /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
    25672567        mask &= ~X86_CR0_NE;
    … …  
    25812581
    25822582        /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
    2583         mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr0Fixed1;
     2583        mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
    25842584        if ((pCtx->cr0 & mask) != 0)
    25852585            return false;
    25862586
    25872587        /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
    2588         mask  = (uint32_t)pVM->hm.s.vmx.msr.u64Cr4Fixed0;
     2588        mask  = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
    25892589        mask &= ~X86_CR4_VMXE;
    25902590        if ((pCtx->cr4 & mask) != mask)
    … …  
    25922592
    25932593        /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
    2594         mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr4Fixed1;
     2594        mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
    25952595        if ((pCtx->cr4 & mask) != 0)
    25962596            return false;
    … …  
    29442944    if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
    29452945    {
    2946         LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed    %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.allowed1));
    2947         LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0));
     2946        LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed    %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
     2947        LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
    29482948    }
    29492949}
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