Changeset 48453 in vbox for trunk/src/VBox
- Timestamp:
- Sep 12, 2013 4:03:43 PM (11 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r48443 r48453 6741 6741 uint32_t u32IntrInfo = (uint32_t)u64IntrInfo; 6742 6742 6743 const uint32_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(u32IntrInfo);6743 const uint32_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(u32IntrInfo); 6744 6744 const uint32_t uIntrType = VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntrInfo); 6745 6745 … … 6924 6924 { 6925 6925 int rc; 6926 Log4Func(("vcpu[%d]\n", pVCpu->idCpu)); 6926 6927 6927 6928 /* Clear interrupt-window exiting control. */ … … 8013 8014 * CR0. 8014 8015 */ 8016 uint32_t u32GuestCR0; 8015 8017 uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1); 8016 8018 uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1); … … 8020 8022 uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG); 8021 8023 8022 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32 Val);8024 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32GuestCR0); 8023 8025 AssertRCBreak(rc); 8024 8026 HMVMX_CHECK_BREAK((u32Val & uSetCR0) == uSetCR0, VMX_IGS_CR0_FIXED1); 8025 8027 HMVMX_CHECK_BREAK(!(u32Val & ~uZapCR0), VMX_IGS_CR0_FIXED0); 8026 8028 if ( !fUnrestrictedGuest 8027 && (u32 Val& X86_CR0_PG)8028 && !(u32 Val& X86_CR0_PE))8029 && (u32GuestCR0 & X86_CR0_PG) 8030 && !(u32GuestCR0 & X86_CR0_PE)) 8029 8031 { 8030 8032 HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO); … … 8034 8036 * CR4. 8035 8037 */ 8038 uint32_t u32GuestCR4; 8036 8039 uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1); 8037 8040 uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1); 8038 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32 Val);8041 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCR4); 8039 8042 AssertRCBreak(rc); 8040 HMVMX_CHECK_BREAK((u32 Val& uSetCR4) == uSetCR4, VMX_IGS_CR4_FIXED1);8041 HMVMX_CHECK_BREAK(!(u32 Val& ~uZapCR4), VMX_IGS_CR4_FIXED0);8043 HMVMX_CHECK_BREAK((u32GuestCR4 & uSetCR4) == uSetCR4, VMX_IGS_CR4_FIXED1); 8044 HMVMX_CHECK_BREAK(!(u32GuestCR4 & ~uZapCR4), VMX_IGS_CR4_FIXED0); 8042 8045 8043 8046 /* … … 8098 8101 8099 8102 if ( fLongModeGuest 8100 || !( pCtx->cr0 & X86_CR0_PE))8103 || !(u32GuestCR0 & X86_CR0_PE)) 8101 8104 { 8102 8105 HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID); … … 8121 8124 && !fUnrestrictedGuest) 8122 8125 { 8123 HMVMX_CHECK_BREAK( CPUMIsGuestPagingEnabledEx(pCtx), VMX_IGS_CR0_PG_LONGMODE);8124 HMVMX_CHECK_BREAK( (pCtx->cr4 & X86_CR4_PAE), VMX_IGS_CR4_PAE_LONGMODE);8126 HMVMX_CHECK_BREAK(u32GuestCR0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE); 8127 HMVMX_CHECK_BREAK(u32GuestCR4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE); 8125 8128 } 8126 8129 8127 8130 if ( !fLongModeGuest 8128 && ( pCtx->cr4 & X86_CR4_PCIDE))8131 && (u32GuestCR4 & X86_CR4_PCIDE)) 8129 8132 { 8130 8133 HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE); … … 8197 8200 VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH); 8198 8201 HMVMX_CHECK_BREAK( fUnrestrictedGuest 8199 || (u64Val & MSR_K6_EFER_LMA) == ( pCtx->cr0 & X86_CR0_PG), VMX_IGS_EFER_LMA_PG_MISMATCH);8202 || (u64Val & MSR_K6_EFER_LMA) == (u32GuestCR0 & X86_CR0_PG), VMX_IGS_EFER_LMA_PG_MISMATCH); 8200 8203 } 8201 8204
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