Changeset 48624 in vbox

Timestamp:

Sep 23, 2013 7:50:17 AM (11 years ago)

Author:

vboxsync

Message:

VMM/HMVMXR0, HMSVMR0: Use HMCF macros.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMSVMR0.cpp (modified) (37 diffs)
• HMVMXR0.cpp (modified) (88 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -1103 +1103 @@
      */
     PVM pVM = pVCpu->CTX_SUFF(pVM);
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
     {
         uint64_t u64GuestCR0 = pCtx->cr0;
@@ -1156 +1156 @@
         pVmcb->guest.u64CR0 = u64GuestCR0;
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
     }
 }
@@ -1178 +1178 @@
      * Guest CR2.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
     {
         pVmcb->guest.u64CR2 = pCtx->cr2;
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
     }
 
@@ -1188 +1188 @@
      * Guest CR3.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
     {
         if (pVM->hm.s.fNestedPaging)
@@ -1209 +1209 @@
 
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
     }
 
@@ -1215 +1215 @@
      * Guest CR4.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
     {
         uint64_t u64GuestCR4 = pCtx->cr4;
@@ -1254 +1254 @@
         pVmcb->guest.u64CR4 = u64GuestCR4;
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
     }
 
@@ -1274 +1274 @@
 {
     /* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
     {
         HMSVM_LOAD_SEG_REG(CS, cs);
@@ -1284 +1284 @@
 
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
     }
 
     /* Guest TR. */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
     {
         HMSVM_LOAD_SEG_REG(TR, tr);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
     }
 
     /* Guest LDTR. */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
     {
         HMSVM_LOAD_SEG_REG(LDTR, ldtr);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
     }
 
     /* Guest GDTR. */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
     {
         pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
         pVmcb->guest.GDTR.u64Base  = pCtx->gdtr.pGdt;
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
     }
 
     /* Guest IDTR. */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
     {
         pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
         pVmcb->guest.IDTR.u64Base  = pCtx->idtr.pIdt;
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
     }
 }
@@ -1342 +1342 @@
      * See AMD spec. 15.5.1 "Basic Operation" | "Canonicalization and Consistency Checks".
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_EFER_MSR))
     {
         pVmcb->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_EFER_MSR);
     }
 
@@ -1389 +1389 @@
 static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
 {
-    if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
+    if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
         return;
     Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
@@ -1539 +1539 @@
     }
 
-    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
+    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
 }
 
@@ -1553 +1553 @@
 static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
 {
-    if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
+    if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
         return VINF_SUCCESS;
 
@@ -1597 +1597 @@
     }
 
-    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
+    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
     return rc;
 }
@@ -1653 +1653 @@
 
     LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
-    Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
+    Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
 
     pVCpu->hm.s.fLeaveDone = false;
@@ -1714 +1714 @@
             int rc = HMR0EnterCpu(pVCpu);
             AssertRC(rc); NOREF(rc);
-            Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
+            Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
 
             pVCpu->hm.s.fLeaveDone = false;
@@ -1743 +1743 @@
     NOREF(pVCpu);
     /* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
-    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
+    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
     return VINF_SUCCESS;
 }
@@ -1752 +1752 @@
  * fields on every successful VM-entry.
  *
- * Sets up the appropriate VMRUN function to execute guest code based
- * on the guest CPU mode.
+ * Also sets up the appropriate VMRUN function to execute guest code based on
+ * the guest CPU mode.
  *
  * @returns VBox status code.
@@ -1788 +1788 @@
 
     /* Clear any unused and reserved bits. */
-    pVCpu->hm.s.fContextUseFlags &= ~(  HM_CHANGED_GUEST_RIP                /* Unused (loaded unconditionally). */
-                                      | HM_CHANGED_GUEST_RSP
-                                      | HM_CHANGED_GUEST_RFLAGS
-                                      | HM_CHANGED_GUEST_SYSENTER_CS_MSR
-                                      | HM_CHANGED_GUEST_SYSENTER_EIP_MSR
-                                      | HM_CHANGED_GUEST_SYSENTER_ESP_MSR
-                                      | HM_CHANGED_SVM_RESERVED1            /* Reserved. */
-                                      | HM_CHANGED_SVM_RESERVED2
-                                      | HM_CHANGED_SVM_RESERVED3);
-
-    /* All the guest state bits should be loaded except maybe the host context and shared host/guest bits. */
-    AssertMsg(   !(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_ALL_GUEST)
-              || !(pVCpu->hm.s.fContextUseFlags & ~(HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE)),
-               ("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
-                pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
+    VMCPU_HMCF_CLEAR(pVCpu,   HM_CHANGED_GUEST_RIP                /* Unused (loaded unconditionally). */
+                            | HM_CHANGED_GUEST_RSP
+                            | HM_CHANGED_GUEST_RFLAGS
+                            | HM_CHANGED_GUEST_SYSENTER_CS_MSR
+                            | HM_CHANGED_GUEST_SYSENTER_EIP_MSR
+                            | HM_CHANGED_GUEST_SYSENTER_ESP_MSR
+                            | HM_CHANGED_SVM_RESERVED1            /* Reserved. */
+                            | HM_CHANGED_SVM_RESERVED2
+                            | HM_CHANGED_SVM_RESERVED3);
+
+    /* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
+    AssertMsg(   !VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
+              ||  VMCPU_HMCF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE),
+               ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 
     Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
-
     STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
     return rc;
@@ -1826 +1824 @@
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
 
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
         hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
 
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
         hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
 
-    AssertMsg(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE), ("fContextUseFlags=%#x\n",
-                                                                                     pVCpu->hm.s.fContextUseFlags));
+    AssertMsg(!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
+              ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 }
 
@@ -1995 +1993 @@
         CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
         Assert(!CPUMIsGuestFPUStateActive(pVCpu));
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
     }
 
@@ -2010 +2008 @@
 #endif
     if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
 
     Assert(!CPUMIsHyperDebugStateActive(pVCpu));
@@ -2167 +2165 @@
     /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
     if (rcExit != VINF_EM_RAW_INTERRUPT)
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
 
     STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
@@ -2836 +2834 @@
 
 #ifdef HMSVM_SYNC_FULL_GUEST_STATE
-    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
+    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
 #endif
 
@@ -2920 +2918 @@
     /* Load the state shared between host and guest (FPU, debug). */
     PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
         hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
-    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;       /* Preemption might set this, nothing to do on AMD-V. */
-    AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags=%#x\n", pVCpu->hm.s.fContextUseFlags));
+    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);           /* Preemption might set this, nothing to do on AMD-V. */
+    AssertMsg(!VMCPU_HMCF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 
     /* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
@@ -3075 +3073 @@
                 int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
                 AssertRC(rc);
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
             }
             else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
@@ -3081 +3079 @@
                 int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
                 AssertRC(rc);
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
             }
         }
@@ -3553 +3551 @@
     {
         pCtx->cr2 = uFaultAddress;
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR2;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
     }
 
@@ -3664 +3662 @@
                 int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
                 AssertRC(rc2);
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
 
                 pCtx->rip += pPatch->cbOp;
@@ -4144 +4142 @@
         {
             case 0:     /* CR0. */
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
                 break;
 
             case 3:     /* CR3. */
                 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR3;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
                 break;
 
             case 4:     /* CR4. */
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR4;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
                 break;
 
             case 8:     /* CR8 (TPR). */
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
                 break;
 
@@ -4208 +4206 @@
                 int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
                 AssertRC(rc2);
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
             }
             hmR0SvmUpdateRip(pVCpu, pCtx, 2);
@@ -4243 +4241 @@
              * virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
                EMInterpretWrmsr() changes it. */
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
         }
         else if (pCtx->ecx == MSR_K6_EFER)
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_EFER_MSR;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_EFER_MSR);
         else if (pCtx->ecx == MSR_IA32_TSC)
             pSvmTransient->fUpdateTscOffsetting = true;
@@ -4336 +4334 @@
         /* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
         /** @todo CPUM should set this flag! */
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
         HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
     }
@@ -4590 +4588 @@
         {
             /* Successfully handled MMIO operation. */
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
             rc = VINF_SUCCESS;
         }
@@ -4774 +4772 @@
         TRPMResetTrap(pVCpu);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_SVM_GUEST_APIC_STATE;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
         return rc;
     }
@@ -4825 +4823 @@
     {
         rc = VINF_EM_RAW_GUEST_TRAP;
-        Assert(CPUMIsGuestFPUStateActive(pVCpu) || (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0));
+        Assert(CPUMIsGuestFPUStateActive(pVCpu) || VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
     }
     else
@@ -4842 +4840 @@
     if (rc == VINF_SUCCESS)
     {
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
     }

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -1229 +1229 @@
     LogFlowFunc(("pVM=%p pVCpu=%p GCVirt=%RGv\n", pVM, pVCpu, GCVirt));
 
-    bool fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
+    bool fFlushPending = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
     if (!fFlushPending)
     {
@@ -2630 +2630 @@
 {
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_ENTRY_CTLS)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS))
     {
         PVM pVM      = pVCpu->CTX_SUFF(pVM);
@@ -2668 +2668 @@
         /* Update VCPU with the currently set VM-exit controls. */
         pVCpu->hm.s.vmx.u32EntryCtls = val;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_ENTRY_CTLS;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS);
     }
     return rc;
@@ -2689 +2689 @@
 {
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_EXIT_CTLS)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_EXIT_CTLS))
     {
         PVM pVM      = pVCpu->CTX_SUFF(pVM);
@@ -2739 +2739 @@
         /* Update VCPU with the currently set VM-exit controls. */
         pVCpu->hm.s.vmx.u32ExitCtls = val;
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_EXIT_CTLS;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_EXIT_CTLS);
     }
     return rc;
@@ -2758 +2758 @@
 {
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_GUEST_APIC_STATE)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE))
     {
         /* Setup TPR shadowing. Also setup TPR patching for 32-bit guests. */
@@ -2795 +2795 @@
         }
 
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_GUEST_APIC_STATE;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
     }
     return rc;
@@ -2820 +2820 @@
      */
     uint32_t uIntrState = 0;
-    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
+    if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     {
         /* If inhibition is active, RIP & RFLAGS should've been accessed (i.e. read previously from the VMCS or from ring-3). */
@@ -2874 +2874 @@
 {
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RIP)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP))
     {
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pMixedCtx->rip);
         AssertRCReturn(rc, rc);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_RIP;
-        Log4(("Load: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#x\n", pMixedCtx->rip, pVCpu->hm.s.fContextUseFlags));
+
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP);
+        Log4(("Load: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#RX32\n", pMixedCtx->rip, VMCPU_HMCF_VALUE(pVCpu)));
     }
     return rc;
@@ -2899 +2900 @@
 {
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RSP)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP))
     {
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pMixedCtx->rsp);
         AssertRCReturn(rc, rc);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_RSP;
+
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_RSP);
         Log4(("Load: VMX_VMCS_GUEST_RSP=%#RX64\n", pMixedCtx->rsp));
     }
@@ -2924 +2926 @@
 {
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RFLAGS)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
     {
         /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
@@ -2949 +2951 @@
         AssertRCReturn(rc, rc);
 
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_RFLAGS;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_RFLAGS);
         Log4(("Load: VMX_VMCS_GUEST_RFLAGS=%#RX32\n", Eflags.u32));
     }
@@ -2999 +3001 @@
      */
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
     {
         Assert(!(pMixedCtx->cr0 >> 32));
@@ -3160 +3162 @@
         Log4(("Load: VMX_VMCS_CTRL_CR0_MASK=%#RX32\n", u32CR0Mask));
 
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
     }
     return rc;
@@ -3192 +3194 @@
      * Guest CR3.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
     {
         RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
@@ -3265 +3267 @@
         AssertRCReturn(rc, rc);
 
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
     }
 
@@ -3271 +3273 @@
      * Guest CR4.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
     {
         Assert(!(pMixedCtx->cr4 >> 32));
@@ -3362 +3364 @@
         AssertRCReturn(rc, rc);
 
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
     }
     return rc;
@@ -3384 +3386 @@
 static int hmR0VmxLoadSharedDebugState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
 {
-    if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
+    if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
         return VINF_SUCCESS;
 
@@ -3415 +3417 @@
             pMixedCtx->eflags.u32 |= X86_EFL_TF;
             pVCpu->hm.s.fClearTrapFlag = true;
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RFLAGS;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
             fInterceptDB = true;
         }
@@ -3528 +3530 @@
     AssertRCReturn(rc, rc);
 
-    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
+    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
     return VINF_SUCCESS;
 }
@@ -3779 +3781 @@
      * Guest Segment registers: CS, SS, DS, ES, FS, GS.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
     {
         /* Save the segment attributes for real-on-v86 mode hack, so we can restore them on VM-exit. */
@@ -3827 +3829 @@
         AssertRCReturn(rc, rc);
 
+#ifdef VBOX_STRICT
+        /* Validate. */
+        hmR0VmxValidateSegmentRegs(pVM, pVCpu, pMixedCtx);
+#endif
+
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
         Log4(("Load: CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pMixedCtx->cs.Sel, pMixedCtx->cs.u64Base,
              pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
-#ifdef VBOX_STRICT
-        hmR0VmxValidateSegmentRegs(pVM, pVCpu, pMixedCtx);
-#endif
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
     }
 
@@ -3838 +3842 @@
      * Guest TR.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
     {
         /*
@@ -3897 +3901 @@
         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);       AssertRCReturn(rc, rc);
 
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
         Log4(("Load: VMX_VMCS_GUEST_TR_BASE=%#RX64\n", u64Base));
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
     }
 
@@ -3904 +3908 @@
      * Guest GDTR.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
     {
         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt);        AssertRCReturn(rc, rc);
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE,  pMixedCtx->gdtr.pGdt);         AssertRCReturn(rc, rc);
 
+        /* Validate. */
         Assert(!(pMixedCtx->gdtr.cbGdt & 0xffff0000));          /* Bits 31:16 MBZ. */
+
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
         Log4(("Load: VMX_VMCS_GUEST_GDTR_BASE=%#RX64\n", pMixedCtx->gdtr.pGdt));
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
     }
 
@@ -3917 +3923 @@
      * Guest LDTR.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
     {
         /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
@@ -3946 +3952 @@
         }
 
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
         Log4(("Load: VMX_VMCS_GUEST_LDTR_BASE=%#RX64\n",  pMixedCtx->ldtr.u64Base));
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
     }
 
@@ -3953 +3959 @@
      * Guest IDTR.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
     {
         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt);         AssertRCReturn(rc, rc);
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE,  pMixedCtx->idtr.pIdt);          AssertRCReturn(rc, rc);
 
+        /* Validate. */
         Assert(!(pMixedCtx->idtr.cbIdt & 0xffff0000));          /* Bits 31:16 MBZ. */
+
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
         Log4(("Load: VMX_VMCS_GUEST_IDTR_BASE=%#RX64\n", pMixedCtx->idtr.pIdt));
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
     }
 
@@ -3990 +3998 @@
      */
     int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_GUEST_AUTO_MSRS)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS))
     {
 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
@@ -4049 +4057 @@
 #endif  /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
 
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_GUEST_AUTO_MSRS;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
     }
 
@@ -4057 +4065 @@
      * VM-exits on WRMSRs for these MSRs.
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR))
     {
         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pMixedCtx->SysEnter.cs);      AssertRCReturn(rc, rc);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_CS_MSR;
-    }
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
+    }
+
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR))
     {
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip);    AssertRCReturn(rc, rc);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR;
-    }
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
+    }
+
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR))
     {
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp);    AssertRCReturn(rc, rc);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR;
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
     }
 
@@ -4092 +4102 @@
     /** @todo See if we can make use of other states, e.g.
      *        VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN or HLT.  */
-    int rc = VINF_SUCCESS;
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_GUEST_ACTIVITY_STATE)
-    {
-        rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE))
+    {
+        int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
         AssertRCReturn(rc, rc);
-        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_GUEST_ACTIVITY_STATE;
-    }
-    return rc;
+
+        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE);
+    }
+    return VINF_SUCCESS;
 }
 
@@ -4127 +4137 @@
         {
             pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS);
         }
 #else
@@ -4141 +4151 @@
         {
             pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS);
         }
 #else
@@ -5336 +5346 @@
 
         EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
-        Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
+        Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
     }
 }
@@ -5964 +5974 @@
         {
             int rc2 = PGMSyncCR3(pVCpu, pMixedCtx->cr0, pMixedCtx->cr3, pMixedCtx->cr4,
-                                 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
+                                 VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
             if (rc2 != VINF_SUCCESS)
             {
@@ -6179 +6189 @@
     if (CPUMIsGuestFPUStateActive(pVCpu))
     {
+        /* We shouldn't reload CR0 without saving it first. */
         if (!fSaveGuestState)
         {
@@ -6186 +6197 @@
         CPUMR0SaveGuestFPU(pVM, pVCpu, pMixedCtx);
         Assert(!CPUMIsGuestFPUStateActive(pVCpu));
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
     }
 
@@ -6195 +6206 @@
 #endif
     if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */))
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
     Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
     Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
@@ -6380 +6391 @@
     /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
     if (rcExit != VINF_EM_RAW_INTERRUPT)
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
 
     STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
@@ -6503 +6514 @@
     Assert(!TRPMHasTrap(pVCpu));
 
-                                                           /** @todo SMI. SMIs take priority over NMIs. */
-    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))    /* NMI. NMIs take priority over regular interrupts . */
+                                                               /** @todo SMI. SMIs take priority over NMIs. */
+    if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))    /* NMI. NMIs take priority over regular interrupts . */
     {
         /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
@@ -6948 +6959 @@
                 /* If any other guest-state bits are changed here, make sure to update
                    hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
-                pVCpu->hm.s.fContextUseFlags |=   HM_CHANGED_GUEST_SEGMENT_REGS
-                                                | HM_CHANGED_GUEST_RIP
-                                                | HM_CHANGED_GUEST_RFLAGS
-                                                | HM_CHANGED_GUEST_RSP;
+                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_SEGMENT_REGS
+                                      | HM_CHANGED_GUEST_RIP
+                                      | HM_CHANGED_GUEST_RFLAGS
+                                      | HM_CHANGED_GUEST_RSP);
 
                 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
@@ -7066 +7077 @@
 
     LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
-    Assert((pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE))
-                                        == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
+    Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
 
 #ifdef VBOX_STRICT
@@ -7155 +7165 @@
             int rc = HMR0EnterCpu(pVCpu);
             AssertRC(rc);
-            Assert((pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE))
-                                                == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
+            Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
 
             /* Load the active VMCS as the current one. */
@@ -7195 +7204 @@
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
 
-    if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT))
+    if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
         return VINF_SUCCESS;
 
@@ -7207 +7216 @@
     AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostMsrs failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
 
-    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
+    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
     return rc;
 }
@@ -7323 +7332 @@
 
     /* Clear any unused and reserved bits. */
-    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
+    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
 
 #ifdef LOG_ENABLED
@@ -7350 +7359 @@
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
 
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
     {
         int rc = hmR0VmxLoadSharedCR0(pVCpu, pCtx);
@@ -7356 +7365 @@
     }
 
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
     {
         int rc = hmR0VmxLoadSharedDebugState(pVCpu, pCtx);
@@ -7362 +7371 @@
 
         /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
-        if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RFLAGS)
+        if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
         {
             rc = hmR0VmxLoadGuestRflags(pVCpu, pCtx);
@@ -7369 +7378 @@
     }
 
-    AssertMsg(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE), ("fContextUseFlags=%#x\n",
-                                                                                     pVCpu->hm.s.fContextUseFlags));
+    AssertMsg(!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
+              ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 }
 
@@ -7387 +7396 @@
     HMVMX_ASSERT_PREEMPT_SAFE();
 
-    Log5(("LoadFlags=%#RX32\n", pVCpu->hm.s.fContextUseFlags));
+    Log5(("LoadFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 #ifdef HMVMX_SYNC_FULL_GUEST_STATE
-    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
-#endif
-
-    if (pVCpu->hm.s.fContextUseFlags == HM_CHANGED_GUEST_RIP)
+    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
+#endif
+
+    if (VMCPU_HMCF_IS_SET_ONLY(pVCpu, HM_CHANGED_GUEST_RIP))
     {
         int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
@@ -7398 +7407 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadMinimal);
     }
-    else if (pVCpu->hm.s.fContextUseFlags)
+    else if (VMCPU_HMCF_VALUE(pVCpu))
     {
         int rc = hmR0VmxLoadGuestState(pVM, pVCpu, pMixedCtx);
@@ -7405 +7414 @@
     }
 
-    /* All the guest state bits should be loaded except maybe the host context and shared host/guest bits. */
-    AssertMsg(   !(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_ALL_GUEST)
-              || !(pVCpu->hm.s.fContextUseFlags & ~(HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE)),
-              ("fContextUseFlags=%#x\n", pVCpu->hm.s.fContextUseFlags));
+    /* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
+    AssertMsg(   !VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
+              ||  VMCPU_HMCF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE),
+              ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 
 #ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
@@ -7588 +7597 @@
     if (!CPUMIsGuestFPUStateActive(pVCpu))
         CPUMR0LoadGuestFPU(pVM, pVCpu, pMixedCtx);
-    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
 #endif
 
@@ -7595 +7604 @@
      * thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
     {
         /* This ASSUMES that pfnStartVM has been set up already. */
@@ -7602 +7611 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptSaveHostState);
     }
-    Assert(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT));
+    Assert(!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT));
 
     /*
      * Load the state shared between host and guest (FPU, debug).
      */
-    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE)
+    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
         hmR0VmxLoadSharedState(pVM, pVCpu, pMixedCtx);
-    AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags=%#x\n", pVCpu->hm.s.fContextUseFlags));
+    AssertMsg(!VMCPU_HMCF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 
     /* Store status of the shared guest-host state at the time of VM-entry. */
@@ -7718 +7727 @@
         hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
         CPUMR0SaveGuestFPU(pVM, pVCpu, pMixedCtx);
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
     }
 #endif
@@ -7762 +7771 @@
             rc = PDMApicSetTPR(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[0x80]);
             AssertRC(rc);
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
         }
     }
@@ -7924 +7933 @@
             break;
         }
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
     }
 
@@ -8102 +8111 @@
 
     pMixedCtx->rip += pVmxTransient->cbInstr;
-    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
+    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
     return rc;
 }
@@ -9222 +9231 @@
 
     pMixedCtx->rip++;
-    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
+    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
     if (EMShouldContinueAfterHalt(pVCpu, pMixedCtx))    /* Requires eflags. */
         rc = VINF_SUCCESS;
@@ -9467 +9476 @@
              * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before
                EMInterpretWrmsr() changes it. */
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
         }
         else if (pMixedCtx->ecx == MSR_K6_EFER)         /* EFER is the only MSR we auto-load but don't allow write-passthrough. */
@@ -9473 +9482 @@
             rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
             AssertRCReturn(rc, rc);
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_AUTO_MSRS;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
         }
         else if (pMixedCtx->ecx == MSR_IA32_TSC)        /* Windows 7 does this during bootup. See @bugref{6398}. */
@@ -9483 +9492 @@
             switch (pMixedCtx->ecx)
             {
-                case MSR_IA32_SYSENTER_CS:  pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_CS_MSR;  break;
-                case MSR_IA32_SYSENTER_EIP: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_EIP_MSR; break;
-                case MSR_IA32_SYSENTER_ESP: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_ESP_MSR; break;
+                case MSR_IA32_SYSENTER_CS:  VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);  break;
+                case MSR_IA32_SYSENTER_EIP: VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
+                case MSR_IA32_SYSENTER_ESP: VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
                 case MSR_K8_FS_BASE:        /* no break */
-                case MSR_K8_GS_BASE:        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SEGMENT_REGS;     break;
-                case MSR_K8_KERNEL_GS_BASE: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_AUTO_MSRS;    break;
+                case MSR_K8_GS_BASE:        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);     break;
+                case MSR_K8_KERNEL_GS_BASE: VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);    break;
             }
         }
@@ -9555 +9564 @@
      * resume guest execution.
      */
-    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
+    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
     return VINF_SUCCESS;
@@ -9603 +9612 @@
             {
                 case 0: /* CR0 */
+                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
                     Log4(("CRX CR0 write rc=%d CR0=%#RX64\n", rc, pMixedCtx->cr0));
-                    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
                     break;
                 case 2: /* C2 **/
@@ -9611 +9620 @@
                 case 3: /* CR3 */
                     Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx));
+                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
                     Log4(("CRX CR3 write rc=%d CR3=%#RX64\n", rc, pMixedCtx->cr3));
-                    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR3;
                     break;
                 case 4: /* CR4 */
+                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
                     Log4(("CRX CR4 write rc=%d CR4=%#RX64\n", rc, pMixedCtx->cr4));
-                    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR4;
                     break;
                 case 8: /* CR8 */
                     Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
                     /* CR8 contains the APIC TPR. Was updated by EMInterpretCRxWrite(). */
-                    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
+                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
                     break;
                 default:
@@ -9660 +9669 @@
             rc = EMInterpretCLTS(pVM, pVCpu);
             AssertRCReturn(rc, rc);
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
             STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
             Log4(("CRX CLTS write rc=%d\n", rc));
@@ -9672 +9681 @@
             rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification));
             if (RT_LIKELY(rc == VINF_SUCCESS))
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
             STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
             Log4(("CRX LMSW write rc=%d\n", rc));
@@ -9781 +9790 @@
         }
         /** @todo IEM needs to be setting these flags somehow. */
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
         fUpdateRipAlready = true;
 #else
@@ -9843 +9852 @@
         {
             pMixedCtx->rip += cbInstr;
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
         }
 
@@ -9877 +9886 @@
                     ASMSetDR6(pMixedCtx->dr[6]);
                 if (pMixedCtx->dr[7] != uDr7)
-                    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
+                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
 
                 hmR0VmxSetPendingXcptDB(pVCpu, pMixedCtx);
@@ -10041 +10050 @@
                 || rc == VERR_PAGE_NOT_PRESENT)
             {
-                pVCpu->hm.s.fContextUseFlags |=   HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
-                                                | HM_CHANGED_VMX_GUEST_APIC_STATE;
+                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                                      | HM_CHANGED_GUEST_RSP
+                                      | HM_CHANGED_GUEST_RFLAGS
+                                      | HM_CHANGED_VMX_GUEST_APIC_STATE);
                 rc = VINF_SUCCESS;
             }
@@ -10133 +10144 @@
                                  VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification));
         if (RT_SUCCESS(rc))
-            pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
+            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
     }
@@ -10199 +10210 @@
     {
         /* Successfully handled MMIO operation. */
-        pVCpu->hm.s.fContextUseFlags |=   HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
-                                        | HM_CHANGED_VMX_GUEST_APIC_STATE;
+        VMCPU_HMCF_SET(pVCpu,  HM_CHANGED_GUEST_RIP
+                             | HM_CHANGED_GUEST_RSP
+                             | HM_CHANGED_GUEST_RFLAGS
+                             | HM_CHANGED_VMX_GUEST_APIC_STATE);
         rc = VINF_SUCCESS;
     }
@@ -10264 +10277 @@
         /* Successfully synced our nested page tables. */
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS;
+        VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                              | HM_CHANGED_GUEST_RSP
+                              | HM_CHANGED_GUEST_RFLAGS);
         return VINF_SUCCESS;
     }
@@ -10434 +10449 @@
     {
         rc = VINF_EM_RAW_GUEST_TRAP;
-        Assert(CPUMIsGuestFPUStateActive(pVCpu) || (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0));
+        Assert(CPUMIsGuestFPUStateActive(pVCpu) || VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
     }
     else
@@ -10451 +10466 @@
     if (rc == VINF_SUCCESS)
     {
-        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
+        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
     }
@@ -10523 +10538 @@
                 pMixedCtx->eflags.Bits.u1IF = 0;
                 pMixedCtx->rip += pDis->cbInstr;
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
                 break;
@@ -10533 +10548 @@
                 pMixedCtx->rip += pDis->cbInstr;
                 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
-                Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS;
+                Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
                 break;
@@ -10543 +10558 @@
                 rc = VINF_EM_HALT;
                 pMixedCtx->rip += pDis->cbInstr;
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
                 break;
@@ -10583 +10598 @@
                 pMixedCtx->eflags.u32 =   (pMixedCtx->eflags.u32 & ~(X86_EFL_POPF_BITS & uMask))
                                         | (Eflags.u32 & X86_EFL_POPF_BITS & uMask);
-                /* The RF bit is always cleared by POPF; see Intel Instruction reference for POPF. */
-                pMixedCtx->eflags.Bits.u1RF   = 0;
-                pMixedCtx->esp               += cbParm;
-                pMixedCtx->esp               &= uMask;
-                pMixedCtx->rip               += pDis->cbInstr;
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS;
+                pMixedCtx->eflags.Bits.u1RF  = 0;    /* The RF bit is always cleared by POPF; see Intel Instruction reference. */
+                pMixedCtx->esp              += cbParm;
+                pMixedCtx->esp              &= uMask;
+                pMixedCtx->rip              += pDis->cbInstr;
+
+                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                                      | HM_CHANGED_GUEST_RSP
+                                      | HM_CHANGED_GUEST_RFLAGS);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPopf);
                 break;
@@ -10632 +10649 @@
                 pMixedCtx->esp               &= uMask;
                 pMixedCtx->rip               += pDis->cbInstr;
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPushf);
                 break;
@@ -10666 +10683 @@
                                                 | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
                 pMixedCtx->sp                += sizeof(aIretFrame);
-                pVCpu->hm.s.fContextUseFlags |=   HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_SEGMENT_REGS | HM_CHANGED_GUEST_RSP
-                                                | HM_CHANGED_GUEST_RFLAGS;
+                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                                      | HM_CHANGED_GUEST_SEGMENT_REGS
+                                      | HM_CHANGED_GUEST_RSP
+                                      | HM_CHANGED_GUEST_RFLAGS);
                 Log4(("IRET %#RX32 to %04x:%x\n", GCPtrStack, pMixedCtx->cs.Sel, pMixedCtx->ip));
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIret);
@@ -10696 +10715 @@
                                                                     EMCODETYPE_SUPERVISOR);
                 rc = VBOXSTRICTRC_VAL(rc2);
-                pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
+                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
                 Log4(("#GP rc=%Rrc\n", rc));
                 break;
@@ -10786 +10805 @@
         /** @todo this isn't quite right, what if guest does lgdt with some MMIO
          *        memory? We don't update the whole state here... */
-        pVCpu->hm.s.fContextUseFlags |=   HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
-                                        | HM_CHANGED_VMX_GUEST_APIC_STATE;
+        VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                              | HM_CHANGED_GUEST_RSP
+                              | HM_CHANGED_GUEST_RFLAGS
+                              | HM_CHANGED_VMX_GUEST_APIC_STATE);
         TRPMResetTrap(pVCpu);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);