Changeset 48695 in vbox

Timestamp:

Sep 26, 2013 12:20:56 AM (11 years ago)

Author:

vboxsync

Message:

CPUM: MSR_CORE_THREAD_COUNT and MSR_FLEX_RATIO for snow leopard.

Location:

trunk

Files:

• include/iprt/x86.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (modified) (4 diffs)

trunk/include/iprt/x86.h

@@ -947 +947 @@
 #endif
 
+/** Undocumented intel MSR for reporting thread and core counts.
+ * Judging from the XNU sources, it seems to be introduced in Nehalem. The
+ * first 16 bits is the thread count. The next 16 bits the core count, except
+ * on westmer where it seems it's only the next 4 bits for some reason. */
+#define MSR_CORE_THREAD_COUNT               0x35
+
 /** CPU Feature control. */
 #define MSR_IA32_FEATURE_CONTROL            0x3A
@@ -1014 +1020 @@
 #define MSR_IA32_PERFEVTSEL0                0x186
 #define MSR_IA32_PERFEVTSEL1                0x187
-#define MSR_IA32_FLEX_RATIO                 0x194
+/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
+ * The 16th bit whether flex ratio is being used, in which case bits 15:8
+ * holds a ratio that Apple takes for TSC granularity.
+ *
+ * @note This MSR conflics the P4 MSR_MCG_R12 register. */
+#define MSR_FLEX_RATIO                      0x194
+/** Performance state value and starting with Intel core more.
+ * Apple uses the >=core features to determine TSC granularity on older CPUs. */
 #define MSR_IA32_PERF_STATUS                0x198
 #define MSR_IA32_PERF_CTL                   0x199

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -1044 +1044 @@
 
         case MSR_IA32_PERF_STATUS:
-            /** @todo could really be not exactly correct, maybe use host's values */
+            /** @todo could really be not exactly correct, maybe use host's values
+             * Apple code indicates that we should use CPU Hz / 1.333MHz here. */
+            /** @todo Where are the specs implemented here found? */
             *puValue = UINT64_C(1000)                 /* TSC increment by tick */
                      | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
@@ -1063 +1065 @@
 
         case MSR_IA32_PLATFORM_INFO:
-            *puValue = (u8Multiplier << 8)            /* Flex ratio max */
+            *puValue = ((uint32_t)u8Multiplier << 8)  /* Flex ratio max */
                      | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
             break;
@@ -1142 +1144 @@
         case MSR_RAPL_POWER_UNIT:
         case MSR_BBL_CR_CTL3:               /* ca. core arch? */
-        case MSR_PKG_CST_CONFIG_CONTROL:   /* Nahalem, Sandy Bridge */
+        case MSR_PKG_CST_CONFIG_CONTROL:    /* Nahalem, Sandy Bridge */
+        case MSR_CORE_THREAD_COUNT:         /* Apple queries this. */
+        case MSR_FLEX_RATIO:                /* Apple queries this. */
             *puValue = 0;
             if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
@@ -1169 +1173 @@
                     *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
                     break;
+                case MSR_CORE_THREAD_COUNT:
+                {
+                    /** @todo restrict this to nehalem.  */
+                    PVM pVM = pVCpu->CTX_SUFF(pVM); /* Note! Not sweating the 4-bit core count limit on westmere. */
+                    *puValue = pVM->cCpus & 0xffff | ((pVM->cCpus & 0xffff) << 16);
+                    break;
+                }
+
+                case MSR_FLEX_RATIO:
+                {
+                    /** @todo Check for P4, it's different there. Try find accurate specs. */
+                    *puValue = (uint32_t)u8Multiplier << 8;
+                    break;
+                }
             }
             break;