Changeset 49225 in vbox

Timestamp:

Oct 22, 2013 9:01:37 AM (11 years ago)

Author:

vboxsync

Message:

VMM/HMSVMR0: Fix TSC Aux MSR passthru.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -2920 +2920 @@
     AssertMsg(!VMCPU_HMCF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
 
-    /* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
-    if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
-        pVmcb->ctrl.u64VmcbCleanBits = 0;
-
     /* Setup TSC offsetting. */
     if (   pSvmTransient->fUpdateTscOffsetting
@@ -2967 +2963 @@
         && !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
     {
+        hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
         pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
         uint64_t u64GuestTscAux = 0;
@@ -2972 +2969 @@
         AssertRC(rc2);
         if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
-        {
             ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
-            pSvmTransient->fRestoreTscAuxMsr = true;
-        }
-    }
+        pSvmTransient->fRestoreTscAuxMsr = true;
+    }
+    else
+        hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
+
+    /* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
+    if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
+        pVmcb->ctrl.u64VmcbCleanBits = 0;
 }
 
@@ -4359 +4360 @@
             && pCtx->ecx <= MSR_IA32_X2APIC_END)
         {
-            /* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
+            /*
+             * We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
              * virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
-               EMInterpretWrmsr() changes it. */
+             * EMInterpretWrmsr() changes it.
+             */
             VMCPU_HMCF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
         }