Changeset 49478 in vbox for trunk

Timestamp:

Nov 14, 2013 12:56:30 PM (11 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

90629

Message:

VMM/HMVMXR0: Fixed single-stepping in the guest to generate #DB correctly.

File:

• trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -6870 +6870 @@
 
     /* Delivery pending debug exception if the guest is single-stepping. Evaluate and set the BS bit. */
-    int rc2 = VINF_SUCCESS;
-    if (   fBlockSti
-        || fBlockMovSS)
-    {
-        if (   !pVCpu->hm.s.fSingleInstruction
-            && !DBGFIsStepping(pVCpu))
-        {
-            Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS);
-            if (pMixedCtx->eflags.Bits.u1TF)    /* We don't have any IA32_DEBUGCTL MSR for guests. Treat as all bits 0. */
-            {
-                /*
-                 * The pending-debug exceptions field is cleared on all VM-exits except VMX_EXIT_TPR_BELOW_THRESHOLD,
-                 * VMX_EXIT_MTF, VMX_EXIT_APIC_WRITE and VMX_EXIT_VIRTUALIZED_EOI.
-                 * See Intel spec. 27.3.4 "Saving Non-Register State".
-                 */
-                rc2 = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS);
-                AssertRCReturn(rc, rc);
-            }
-        }
-        else
-        {
-            /* We are single-stepping in the hypervisor debugger, clear interrupt inhibition as setting the BS bit would mean
-               delivering a #DB to the guest upon VM-entry when it shouldn't be. */
-            uIntrState = 0;
-        }
+    if (   !pVCpu->hm.s.fSingleInstruction
+        && !DBGFIsStepping(pVCpu))
+    {
+        int rc2 = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
+        AssertRCReturn(rc2, rc2);
+        if (pMixedCtx->eflags.Bits.u1TF)    /* We don't have any IA32_DEBUGCTL MSR for guests. Treat as all bits 0. */
+        {
+            /*
+             * The pending-debug exceptions field is cleared on all VM-exits except VMX_EXIT_TPR_BELOW_THRESHOLD,
+             * VMX_EXIT_MTF, VMX_EXIT_APIC_WRITE and VMX_EXIT_VIRTUALIZED_EOI.
+             * See Intel spec. 27.3.4 "Saving Non-Register State".
+             */
+            rc2 = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS);
+            AssertRCReturn(rc2, rc2);
+        }
+    }
+    else
+    {
+        /* We are single-stepping in the hypervisor debugger, clear interrupt inhibition as setting the BS bit would mean
+           delivering a #DB to the guest upon VM-entry when it shouldn't be. */
+        uIntrState = 0;
     }
 
@@ -6901 +6897 @@
      * VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
      */
-    rc2 = hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
+    int rc2 = hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
     AssertRC(rc2);