Changeset 49729 in vbox for trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

Timestamp:

Nov 29, 2013 2:20:44 PM (11 years ago)

Author:

vboxsync

Message:

VMM/HM: VMCPU_HMCF -> HMCPU_CF macro renaming.

File:

• trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (89 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -3069 +3069 @@
 {
     int rc = VINF_SUCCESS;
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS))
     {
         PVM pVM      = pVCpu->CTX_SUFF(pVM);
@@ -3107 +3107 @@
         /* Update VCPU with the currently set VM-exit controls. */
         pVCpu->hm.s.vmx.u32EntryCtls = val;
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS);
     }
     return rc;
@@ -3130 +3130 @@
 
     int rc = VINF_SUCCESS;
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_EXIT_CTLS))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_EXIT_CTLS))
     {
         PVM pVM      = pVCpu->CTX_SUFF(pVM);
@@ -3180 +3180 @@
         /* Update VCPU with the currently set VM-exit controls. */
         pVCpu->hm.s.vmx.u32ExitCtls = val;
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_EXIT_CTLS);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_EXIT_CTLS);
     }
     return rc;
@@ -3201 +3201 @@
 
     int rc = VINF_SUCCESS;
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE))
     {
         /* Setup TPR shadowing. Also setup TPR patching for 32-bit guests. */
@@ -3238 +3238 @@
         }
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
     }
     return rc;
@@ -3318 +3318 @@
 {
     int rc = VINF_SUCCESS;
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP))
     {
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pMixedCtx->rip);
         AssertRCReturn(rc, rc);
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP);
-        Log4(("Load: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#RX32\n", pMixedCtx->rip, VMCPU_HMCF_VALUE(pVCpu)));
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP);
+        Log4(("Load: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#RX32\n", pMixedCtx->rip, HMCPU_CF_VALUE(pVCpu)));
     }
     return rc;
@@ -3344 +3344 @@
 {
     int rc = VINF_SUCCESS;
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP))
     {
         rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pMixedCtx->rsp);
         AssertRCReturn(rc, rc);
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_RSP);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RSP);
         Log4(("Load: VMX_VMCS_GUEST_RSP=%#RX64\n", pMixedCtx->rsp));
     }
@@ -3370 +3370 @@
 {
     int rc = VINF_SUCCESS;
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
     {
         /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
@@ -3395 +3395 @@
         AssertRCReturn(rc, rc);
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_RFLAGS);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RFLAGS);
         Log4(("Load: VMX_VMCS_GUEST_RFLAGS=%#RX32\n", Eflags.u32));
     }
@@ -3445 +3445 @@
      */
     int rc = VINF_SUCCESS;
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
     {
         Assert(!(pMixedCtx->cr0 >> 32));
@@ -3606 +3606 @@
         Log4(("Load: VMX_VMCS_CTRL_CR0_MASK=%#RX32\n", u32CR0Mask));
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
     }
     return rc;
@@ -3638 +3638 @@
      * Guest CR3.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
     {
         RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
@@ -3711 +3711 @@
         AssertRCReturn(rc, rc);
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
     }
 
@@ -3717 +3717 @@
      * Guest CR4.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
     {
         Assert(!(pMixedCtx->cr4 >> 32));
@@ -3808 +3808 @@
         AssertRCReturn(rc, rc);
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
     }
     return rc;
@@ -3830 +3830 @@
 static int hmR0VmxLoadSharedDebugState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
 {
-    if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
+    if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
         return VINF_SUCCESS;
 
@@ -3862 +3862 @@
             pMixedCtx->eflags.u32 |= X86_EFL_TF;
             pVCpu->hm.s.fClearTrapFlag = true;
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
             fInterceptDB = true;
         }
@@ -3977 +3977 @@
     AssertRCReturn(rc, rc);
 
-    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
+    HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
     return VINF_SUCCESS;
 }
@@ -4227 +4227 @@
      * Guest Segment registers: CS, SS, DS, ES, FS, GS.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
     {
         /* Save the segment attributes for real-on-v86 mode hack, so we can restore them on VM-exit. */
@@ -4280 +4280 @@
 #endif
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
         Log4(("Load: CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pMixedCtx->cs.Sel, pMixedCtx->cs.u64Base,
              pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
@@ -4288 +4288 @@
      * Guest TR.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
     {
         /*
@@ -4347 +4347 @@
         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);       AssertRCReturn(rc, rc);
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
         Log4(("Load: VMX_VMCS_GUEST_TR_BASE=%#RX64\n", u64Base));
     }
@@ -4354 +4354 @@
      * Guest GDTR.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
     {
         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt);        AssertRCReturn(rc, rc);
@@ -4362 +4362 @@
         Assert(!(pMixedCtx->gdtr.cbGdt & 0xffff0000));          /* Bits 31:16 MBZ. */
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
         Log4(("Load: VMX_VMCS_GUEST_GDTR_BASE=%#RX64\n", pMixedCtx->gdtr.pGdt));
     }
@@ -4369 +4369 @@
      * Guest LDTR.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
     {
         /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
@@ -4398 +4398 @@
         }
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
         Log4(("Load: VMX_VMCS_GUEST_LDTR_BASE=%#RX64\n", pMixedCtx->ldtr.u64Base));
     }
@@ -4405 +4405 @@
      * Guest IDTR.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
     {
         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt);         AssertRCReturn(rc, rc);
@@ -4413 +4413 @@
         Assert(!(pMixedCtx->idtr.cbIdt & 0xffff0000));          /* Bits 31:16 MBZ. */
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
         Log4(("Load: VMX_VMCS_GUEST_IDTR_BASE=%#RX64\n", pMixedCtx->idtr.pIdt));
     }
@@ -4449 +4449 @@
      */
     PVM pVM = pVCpu->CTX_SUFF(pVM);
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS))
     {
         if (pVM->hm.s.fAllow64BitGuests)
@@ -4468 +4468 @@
 #endif
         }
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
     }
 
@@ -4476 +4476 @@
      * VM-exits on WRMSRs for these MSRs.
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR))
     {
         int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pMixedCtx->SysEnter.cs);      AssertRCReturn(rc, rc);
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
-    }
-
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR))
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
+    }
+
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR))
     {
         int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip);    AssertRCReturn(rc, rc);
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
-    }
-
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR))
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
+    }
+
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR))
     {
         int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp);    AssertRCReturn(rc, rc);
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
     }
 
@@ -4514 +4514 @@
     /** @todo See if we can make use of other states, e.g.
      *        VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN or HLT.  */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE))
     {
         int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
         AssertRCReturn(rc, rc);
 
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE);
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE);
     }
     return VINF_SUCCESS;
@@ -4549 +4549 @@
         {
             pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS);
         }
 #else
@@ -4563 +4563 @@
         {
             pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_EXIT_CTLS | HM_CHANGED_VMX_ENTRY_CTLS);
         }
 #else
@@ -6612 +6612 @@
         CPUMR0SaveGuestFPU(pVM, pVCpu, pMixedCtx);
         Assert(!CPUMIsGuestFPUStateActive(pVCpu));
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
     }
 
@@ -6621 +6621 @@
 #endif
     if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */))
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
     Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
     Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
@@ -6813 +6813 @@
     /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
     if (rcExit != VINF_EM_RAW_INTERRUPT)
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
 
     STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
@@ -7398 +7398 @@
                 /* If any other guest-state bits are changed here, make sure to update
                    hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
-                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_SEGMENT_REGS
-                                      | HM_CHANGED_GUEST_RIP
-                                      | HM_CHANGED_GUEST_RFLAGS
-                                      | HM_CHANGED_GUEST_RSP);
+                HMCPU_CF_SET(pVCpu,   HM_CHANGED_GUEST_SEGMENT_REGS
+                                    | HM_CHANGED_GUEST_RIP
+                                    | HM_CHANGED_GUEST_RFLAGS
+                                    | HM_CHANGED_GUEST_RSP);
 
                 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
@@ -7516 +7516 @@
 
     LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
-    Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
+    Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
 
 #ifdef VBOX_STRICT
@@ -7606 +7606 @@
             int rc = HMR0EnterCpu(pVCpu);
             AssertRC(rc);
-            Assert(VMCPU_HMCF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
+            Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
 
             /* Load the active VMCS as the current one. */
@@ -7645 +7645 @@
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
 
-    if (!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
+    if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
         return VINF_SUCCESS;
 
@@ -7657 +7657 @@
     AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostMsrs failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
 
-    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
+    HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
     return rc;
 }
@@ -7773 +7773 @@
 
     /* Clear any unused and reserved bits. */
-    VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
+    HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
 
 #ifdef LOG_ENABLED
@@ -7802 +7802 @@
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
 
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
     {
         int rc = hmR0VmxLoadSharedCR0(pVCpu, pCtx);
@@ -7808 +7808 @@
     }
 
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
     {
         int rc = hmR0VmxLoadSharedDebugState(pVCpu, pCtx);
@@ -7814 +7814 @@
 
         /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
-        if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
+        if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
         {
             rc = hmR0VmxLoadGuestRflags(pVCpu, pCtx);
@@ -7821 +7821 @@
     }
 
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS))
     {
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
@@ -7830 +7830 @@
         }
 #endif
-        VMCPU_HMCF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
-    }
-
-    AssertMsg(!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
-              ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
+        HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
+    }
+
+    AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
+              ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
 }
 
@@ -7851 +7851 @@
     HMVMX_ASSERT_PREEMPT_SAFE();
 
-    Log5(("LoadFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
+    Log5(("LoadFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
 #ifdef HMVMX_SYNC_FULL_GUEST_STATE
-    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
-#endif
-
-    if (VMCPU_HMCF_IS_SET_ONLY(pVCpu, HM_CHANGED_GUEST_RIP))
+    HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
+#endif
+
+    if (HMCPU_CF_IS_SET_ONLY(pVCpu, HM_CHANGED_GUEST_RIP))
     {
         int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
@@ -7862 +7862 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadMinimal);
     }
-    else if (VMCPU_HMCF_VALUE(pVCpu))
+    else if (HMCPU_CF_VALUE(pVCpu))
     {
         int rc = hmR0VmxLoadGuestState(pVM, pVCpu, pMixedCtx);
@@ -7870 +7870 @@
 
     /* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
-    AssertMsg(   !VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
-              ||  VMCPU_HMCF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE),
-              ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
+    AssertMsg(   !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
+              ||  HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE),
+              ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
 
 #ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
@@ -8049 +8049 @@
     if (!CPUMIsGuestFPUStateActive(pVCpu))
         CPUMR0LoadGuestFPU(pVM, pVCpu, pMixedCtx);
-    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+    HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
 #endif
 
@@ -8057 +8057 @@
         CPUMR0LoadGuestFPU(pVM, pVCpu, pMixedCtx);
         Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR0);
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
     }
 
@@ -8067 +8067 @@
         && pVCpu->hm.s.vmx.cMsrs > 0)
     {
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
     }
 
@@ -8074 +8074 @@
      * thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
     {
         /* This ASSUMES that pfnStartVM has been set up already. */
@@ -8081 +8081 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptSaveHostState);
     }
-    Assert(!VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT));
+    Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT));
 
     /*
      * Load the state shared between host and guest (FPU, debug, lazy MSRs).
      */
-    if (VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
+    if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
         hmR0VmxLoadSharedState(pVM, pVCpu, pMixedCtx);
-    AssertMsg(!VMCPU_HMCF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", VMCPU_HMCF_VALUE(pVCpu)));
+    AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
 
     /* Store status of the shared guest-host state at the time of VM-entry. */
@@ -8200 +8200 @@
         hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
         CPUMR0SaveGuestFPU(pVM, pVCpu, pMixedCtx);
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
     }
 #endif
@@ -8244 +8244 @@
             rc = PDMApicSetTPR(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[0x80]);
             AssertRC(rc);
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
         }
     }
@@ -8404 +8404 @@
             break;
         }
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
     }
 
@@ -8469 +8469 @@
 #ifdef DEBUG_ramshankar
 # define SVVMCS()       do { int rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx); AssertRC(rc2); } while (0)
-# define LDVMCS()       do { VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST); } while (0)
+# define LDVMCS()       do { HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); } while (0)
 #endif
     int rc;
@@ -8602 +8602 @@
 
     pMixedCtx->rip += pVmxTransient->cbInstr;
-    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
+    HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
     return rc;
 }
@@ -9714 +9714 @@
 
     pMixedCtx->rip++;
-    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
+    HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
     if (EMShouldContinueAfterHalt(pVCpu, pMixedCtx))    /* Requires eflags. */
         rc = VINF_SUCCESS;
@@ -9992 +9992 @@
              * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before
                EMInterpretWrmsr() changes it. */
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
         }
         else if (pMixedCtx->ecx == MSR_IA32_TSC)        /* Windows 7 does this during bootup. See @bugref{6398}. */
@@ -10002 +10002 @@
             switch (pMixedCtx->ecx)
             {
-                case MSR_IA32_SYSENTER_CS:  VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);  break;
-                case MSR_IA32_SYSENTER_EIP: VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
-                case MSR_IA32_SYSENTER_ESP: VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
+                case MSR_IA32_SYSENTER_CS:  HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);  break;
+                case MSR_IA32_SYSENTER_EIP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
+                case MSR_IA32_SYSENTER_ESP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
                 case MSR_K8_FS_BASE:        /* no break */
-                case MSR_K8_GS_BASE:        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);     break;
+                case MSR_K8_GS_BASE:        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);     break;
                 default:
                 {
                     if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
-                        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
+                        HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
                     else if (   HMVMX_IS_64BIT_HOST_MODE()
                              && hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
                     {
-                        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
+                        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
                     }
 #endif
@@ -10096 +10096 @@
      * resume guest execution.
      */
-    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
+    HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
     return VINF_SUCCESS;
@@ -10144 +10144 @@
             {
                 case 0: /* CR0 */
-                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+                    HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
                     Log4(("CRX CR0 write rc=%d CR0=%#RX64\n", rc, pMixedCtx->cr0));
                     break;
@@ -10152 +10152 @@
                 case 3: /* CR3 */
                     Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx));
-                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
+                    HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
                     Log4(("CRX CR3 write rc=%d CR3=%#RX64\n", rc, pMixedCtx->cr3));
                     break;
                 case 4: /* CR4 */
-                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
+                    HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
                     Log4(("CRX CR4 write rc=%d CR4=%#RX64\n", rc, pMixedCtx->cr4));
                     break;
@@ -10162 +10162 @@
                     Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
                     /* CR8 contains the APIC TPR. Was updated by EMInterpretCRxWrite(). */
-                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
+                    HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
                     break;
                 default:
@@ -10201 +10201 @@
             rc = EMInterpretCLTS(pVM, pVCpu);
             AssertRCReturn(rc, rc);
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
             STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
             Log4(("CRX CLTS write rc=%d\n", rc));
@@ -10213 +10213 @@
             rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification));
             if (RT_LIKELY(rc == VINF_SUCCESS))
-                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
             STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
             Log4(("CRX LMSW write rc=%d\n", rc));
@@ -10320 +10320 @@
         }
         /** @todo IEM needs to be setting these flags somehow. */
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
         fUpdateRipAlready = true;
 #else
@@ -10382 +10382 @@
         {
             pMixedCtx->rip += cbInstr;
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
         }
 
@@ -10390 +10390 @@
          */
         if (fIOString)
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
 
         /*
@@ -10423 +10423 @@
                     ASMSetDR6(pMixedCtx->dr[6]);
                 if (pMixedCtx->dr[7] != uDr7)
-                    VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
+                    HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
 
                 hmR0VmxSetPendingXcptDB(pVCpu, pMixedCtx);
@@ -10587 +10587 @@
                 || rc == VERR_PAGE_NOT_PRESENT)
             {
-                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
-                                      | HM_CHANGED_GUEST_RSP
-                                      | HM_CHANGED_GUEST_RFLAGS
-                                      | HM_CHANGED_VMX_GUEST_APIC_STATE);
+                HMCPU_CF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                                    | HM_CHANGED_GUEST_RSP
+                                    | HM_CHANGED_GUEST_RFLAGS
+                                    | HM_CHANGED_VMX_GUEST_APIC_STATE);
                 rc = VINF_SUCCESS;
             }
@@ -10681 +10681 @@
                                  VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification));
         if (RT_SUCCESS(rc))
-            VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
+            HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
     }
@@ -10747 +10747 @@
     {
         /* Successfully handled MMIO operation. */
-        VMCPU_HMCF_SET(pVCpu,  HM_CHANGED_GUEST_RIP
+        HMCPU_CF_SET(pVCpu,  HM_CHANGED_GUEST_RIP
                              | HM_CHANGED_GUEST_RSP
                              | HM_CHANGED_GUEST_RFLAGS
@@ -10814 +10814 @@
         /* Successfully synced our nested page tables. */
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
-        VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
-                              | HM_CHANGED_GUEST_RSP
-                              | HM_CHANGED_GUEST_RFLAGS);
+        HMCPU_CF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                            | HM_CHANGED_GUEST_RSP
+                            | HM_CHANGED_GUEST_RFLAGS);
         return VINF_SUCCESS;
     }
@@ -10988 +10988 @@
     {
         rc = VINF_EM_RAW_GUEST_TRAP;
-        Assert(CPUMIsGuestFPUStateActive(pVCpu) || VMCPU_HMCF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
+        Assert(CPUMIsGuestFPUStateActive(pVCpu) || HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
     }
     else
@@ -11005 +11005 @@
     {
         /* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
-        VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
         pVCpu->hm.s.fUseGuestFpu = true;
@@ -11079 +11079 @@
                 pMixedCtx->eflags.Bits.u1IF = 0;
                 pMixedCtx->rip += pDis->cbInstr;
-                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
                 break;
@@ -11090 +11090 @@
                 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
                 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
-                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
                 break;
@@ -11099 +11099 @@
                 rc = VINF_EM_HALT;
                 pMixedCtx->rip += pDis->cbInstr;
-                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
                 break;
@@ -11144 +11144 @@
                 pMixedCtx->rip              += pDis->cbInstr;
 
-                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                HMCPU_CF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
                                       | HM_CHANGED_GUEST_RSP
                                       | HM_CHANGED_GUEST_RFLAGS);
@@ -11190 +11190 @@
                 pMixedCtx->esp               &= uMask;
                 pMixedCtx->rip               += pDis->cbInstr;
-                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP);
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPushf);
                 break;
@@ -11224 +11224 @@
                                                 | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
                 pMixedCtx->sp                += sizeof(aIretFrame);
-                VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
-                                      | HM_CHANGED_GUEST_SEGMENT_REGS
-                                      | HM_CHANGED_GUEST_RSP
-                                      | HM_CHANGED_GUEST_RFLAGS);
+                HMCPU_CF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                                    | HM_CHANGED_GUEST_SEGMENT_REGS
+                                    | HM_CHANGED_GUEST_RSP
+                                    | HM_CHANGED_GUEST_RFLAGS);
                 Log4(("IRET %#RX32 to %04x:%x\n", GCPtrStack, pMixedCtx->cs.Sel, pMixedCtx->ip));
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIret);
@@ -11256 +11256 @@
                                                                     EMCODETYPE_SUPERVISOR);
                 rc = VBOXSTRICTRC_VAL(rc2);
-                VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
                 Log4(("#GP rc=%Rrc\n", rc));
                 break;
@@ -11349 +11349 @@
         /** @todo this isn't quite right, what if guest does lgdt with some MMIO
          *        memory? We don't update the whole state here... */
-        VMCPU_HMCF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
-                              | HM_CHANGED_GUEST_RSP
-                              | HM_CHANGED_GUEST_RFLAGS
-                              | HM_CHANGED_VMX_GUEST_APIC_STATE);
+        HMCPU_CF_SET(pVCpu,   HM_CHANGED_GUEST_RIP
+                            | HM_CHANGED_GUEST_RSP
+                            | HM_CHANGED_GUEST_RFLAGS
+                            | HM_CHANGED_VMX_GUEST_APIC_STATE);
         TRPMResetTrap(pVCpu);
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);