Changeset 49893 in vbox for trunk/include/VBox/vmm
- Timestamp:
- Dec 13, 2013 12:40:20 AM (11 years ago)
- svn:sync-xref-src-repo-rev:
- 91271
- Location:
- trunk/include/VBox/vmm
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpum.h
r49849 r49893 4 4 5 5 /* 6 * Copyright (C) 2006-201 2Oracle Corporation6 * Copyright (C) 2006-2013 Oracle Corporation 7 7 * 8 8 * This file is part of VirtualBox Open Source Edition (OSE), as … … 78 78 CPUMCPUVENDOR_AMD, 79 79 CPUMCPUVENDOR_VIA, 80 CPUMCPUVENDOR_CYRIX, 80 81 CPUMCPUVENDOR_UNKNOWN, 81 CPUMCPUVENDOR_SYNTHETIC,82 82 /** 32bit hackishness. */ 83 83 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff 84 84 } CPUMCPUVENDOR; 85 86 87 /** 88 * X86 and AMD64 CPU microarchitectures and in processor generations. 89 * 90 * @remarks The separation here is sometimes a little bit too finely grained, 91 * and the differences is more like processor generation than micro 92 * arch. This can be useful, so we'll provide functions for getting at 93 * more coarse grained info. 94 */ 95 typedef enum CPUMMICROARCH 96 { 97 kCpumMicroarch_Invalid = 0, 98 99 kCpumMicroarch_Intel_First, 100 101 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First, 102 kCpumMicroarch_Intel_80186, 103 kCpumMicroarch_Intel_80286, 104 kCpumMicroarch_Intel_80386, 105 kCpumMicroarch_Intel_80486, 106 kCpumMicroarch_Intel_P5, 107 108 kCpumMicroarch_Intel_P6_Core_Atom_First, 109 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First, 110 kCpumMicroarch_Intel_P6_II, 111 kCpumMicroarch_Intel_P6_III, 112 113 kCpumMicroarch_Intel_P6_M_Banias, 114 kCpumMicroarch_Intel_P6_M_Dothan, 115 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */ 116 117 kCpumMicroarch_Intel_Core2_Merom, 118 kCpumMicroarch_Intel_Core2_Penryn, 119 120 kCpumMicroarch_Intel_Core7_First, 121 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First, 122 kCpumMicroarch_Intel_Core7_Westmere, 123 kCpumMicroarch_Intel_Core7_SandyBridge, 124 kCpumMicroarch_Intel_Core7_IvyBridge, 125 kCpumMicroarch_Intel_Core7_Haswell, 126 kCpumMicroarch_Intel_Core7_Broadwell, 127 kCpumMicroarch_Intel_Core7_Skylake, 128 kCpumMicroarch_Intel_Core7_Cannonlake, 129 kCpumMicroarch_Intel_Core7_End, 130 131 kCpumMicroarch_Intel_Atom_First, 132 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First, 133 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */ 134 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */ 135 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */ 136 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */ 137 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */ 138 kCpumMicroarch_Intel_Atom_Unknown, 139 kCpumMicroarch_Intel_Atom_End, 140 141 kCpumMicroarch_Intel_P6_Core_Atom_End, 142 143 kCpumMicroarch_Intel_NB_First, 144 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */ 145 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */ 146 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */ 147 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */ 148 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */ 149 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */ 150 kCpumMicroarch_Intel_NB_Unknown, 151 kCpumMicroarch_Intel_NB_End, 152 153 kCpumMicroarch_Intel_Unknown, 154 kCpumMicroarch_Intel_End, 155 156 kCpumMicroarch_AMD_First, 157 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First, 158 kCpumMicroarch_AMD_Am386, 159 kCpumMicroarch_AMD_Am486, 160 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */ 161 kCpumMicroarch_AMD_K5, 162 kCpumMicroarch_AMD_K6, 163 164 kCpumMicroarch_AMD_K7_First, 165 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First, 166 kCpumMicroarch_AMD_K7_Spitfire, 167 kCpumMicroarch_AMD_K7_Thunderbird, 168 kCpumMicroarch_AMD_K7_Morgan, 169 kCpumMicroarch_AMD_K7_Thoroughbred, 170 kCpumMicroarch_AMD_K7_Barton, 171 kCpumMicroarch_AMD_K7_Unknown, 172 kCpumMicroarch_AMD_K7_End, 173 174 kCpumMicroarch_AMD_K8_First, 175 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */ 176 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */ 177 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */ 178 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */ 179 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */ 180 kCpumMicroarch_AMD_K8_End, 181 182 kCpumMicroarch_AMD_K10, 183 kCpumMicroarch_AMD_K10_Lion, 184 kCpumMicroarch_AMD_K10_Llano, 185 kCpumMicroarch_AMD_Bobcat, 186 kCpumMicroarch_AMD_Jaguar, 187 188 kCpumMicroarch_AMD_15h_First, 189 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First, 190 kCpumMicroarch_AMD_15h_Piledriver, 191 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */ 192 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */ 193 kCpumMicroarch_AMD_15h_Unknown, 194 kCpumMicroarch_AMD_15h_End, 195 196 kCpumMicroarch_AMD_16h_First, 197 kCpumMicroarch_AMD_16h_End, 198 199 kCpumMicroarch_AMD_Unknown, 200 kCpumMicroarch_AMD_End, 201 202 kCpumMicroarch_VIA_First, 203 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First, 204 kCpumMicroarch_Centaur_C2, 205 kCpumMicroarch_Centaur_C3, 206 kCpumMicroarch_VIA_C3_M2, 207 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */ 208 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */ 209 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */ 210 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */ 211 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */ 212 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */ 213 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */ 214 kCpumMicroarch_VIA_Isaiah, 215 kCpumMicroarch_VIA_Unknown, 216 kCpumMicroarch_VIA_End, 217 218 kCpumMicroarch_Cyrix_First, 219 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First, 220 kCpumMicroarch_Cyrix_M1, 221 kCpumMicroarch_Cyrix_MediaGX, 222 kCpumMicroarch_Cyrix_MediaGXm, 223 kCpumMicroarch_Cyrix_M2, 224 kCpumMicroarch_Cyrix_Unknown, 225 kCpumMicroarch_Cyrix_End, 226 227 kCpumMicroarch_Unknown, 228 229 kCpumMicroarch_32BitHack = 0x7fffffff 230 } CPUMMICROARCH; 231 232 233 /** Predicate macro for catching netburst CPUs. */ 234 #define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \ 235 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End) 236 237 /** Predicate macro for catching Core7 CPUs. */ 238 #define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \ 239 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End) 240 241 /** Predicate macro for catching AMD Family 8H CPUs (aka K8). */ 242 #define CPUMMICROARCH_IS_AMD_FAM_8H(a_enmMicroarch) \ 243 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End) 244 245 /** Predicate macro for catching AMD Family 10H CPUs (aka K10). */ 246 #define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10) 247 248 /** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */ 249 #define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion) 250 251 /** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */ 252 #define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano) 253 254 /** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */ 255 #define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat) 256 257 /** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's 258 * decendants). */ 259 #define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \ 260 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End) 261 262 /** Predicate macro for catching AMD Family 16H CPUs. */ 263 #define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \ 264 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End) 265 266 267 268 /** 269 * CPUID leaf. 270 */ 271 typedef struct CPUMCPUIDLEAF 272 { 273 /** The leaf number. */ 274 uint32_t uLeaf; 275 /** The sub-leaf number. */ 276 uint32_t uSubLeaf; 277 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */ 278 uint32_t fSubLeafMask; 279 280 /** The EAX value. */ 281 uint32_t uEax; 282 /** The EBX value. */ 283 uint32_t uEbx; 284 /** The ECX value. */ 285 uint32_t uEcx; 286 /** The EDX value. */ 287 uint32_t uEdx; 288 289 /** Flags. */ 290 uint32_t fFlags; 291 } CPUMCPUIDLEAF; 292 /** Pointer to a CPUID leaf. */ 293 typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF; 294 /** Pointer to a const CPUID leaf. */ 295 typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF; 296 297 /** @name CPUMCPUIDLEAF::fFlags 298 * @{ */ 299 /** Indicates that ECX (the sub-leaf indicator) doesn't change when 300 * requesting the final leaf and all undefined leaves that follows it. 301 * Observed for 0x0000000b on Intel. */ 302 #define CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED RT_BIT_32(0) 303 /** @} */ 304 305 /** 306 * Method used to deal with unknown CPUID leafs. 307 */ 308 typedef enum CPUMUKNOWNCPUID 309 { 310 /** Invalid zero value. */ 311 CPUMUKNOWNCPUID_INVALID = 0, 312 /** Use given default values (DefCpuId). */ 313 CPUMUKNOWNCPUID_DEFAULTS, 314 /** Return the last standard leaf. 315 * Intel Sandy Bridge has been observed doing this. */ 316 CPUMUKNOWNCPUID_LAST_STD_LEAF, 317 /** Return the last standard leaf, with ecx observed. 318 * Intel Sandy Bridge has been observed doing this. */ 319 CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX, 320 /** The register values are passed thru unmodified. */ 321 CPUMUKNOWNCPUID_PASSTHRU, 322 /** End of valid value. */ 323 CPUMUKNOWNCPUID_END, 324 /** Ensure 32-bit type. */ 325 CPUMUKNOWNCPUID_32BIT_HACK = 0x7fffffff 326 } CPUMUKNOWNCPUID; 327 /** Pointer to unknown CPUID leaf method. */ 328 typedef CPUMUKNOWNCPUID *PCPUMUKNOWNCPUID; 329 85 330 86 331 … … 173 418 VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu); 174 419 VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg); 420 VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue); 421 VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu); 175 422 /** @} */ 176 423 … … 443 690 VMMR3DECL(int) CPUMR3Term(PVM pVM); 444 691 VMMR3DECL(void) CPUMR3Reset(PVM pVM); 445 VMMR3DECL(void) CPUMR3ResetCpu(PVM CPU pVCpu);692 VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu); 446 693 VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM); 447 694 VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled); … … 451 698 VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM); 452 699 VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM); 700 701 VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily, 702 uint8_t bModel, uint8_t bStepping); 703 VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch); 704 VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves); 705 VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown); 706 VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod); 707 VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX); 708 VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor); 453 709 454 710 /** @} */ -
trunk/include/VBox/vmm/mm.h
r44528 r49893 59 59 60 60 MM_TAG_CPUM_CTX, 61 MM_TAG_CPUM_CPUID, 62 MM_TAG_CPUM_MSRS, 61 63 62 64 MM_TAG_DBGF, … … 206 208 207 209 VMMDECL(int) MMHyperAlloc(PVM pVM, size_t cb, uint32_t uAlignment, MMTAG enmTag, void **ppv); 210 VMMDECL(int) MMHyperDupMem(PVM pVM, const void *pvSrc, size_t cb, unsigned uAlignment, MMTAG enmTag, void **ppv); 208 211 VMMDECL(int) MMHyperFree(PVM pVM, void *pv); 209 212 VMMDECL(void) MMHyperHeapCheck(PVM pVM);
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