Changeset 49893 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Dec 13, 2013 12:40:20 AM (11 years ago)
- svn:sync-xref-src-repo-rev:
- 91271
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 1 added
- 3 edited
-
CPUMAllMsrs.cpp (added)
-
CPUMAllRegs.cpp (modified) (27 diffs)
-
MMAll.cpp (modified) (1 diff)
-
MMAllHyper.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r49849 r49893 870 870 } 871 871 872 #ifndef VBOX_WITH_NEW_MSR_CODE 872 873 873 874 /** … … 1585 1586 } 1586 1587 1588 #endif /* !VBOX_WITH_NEW_MSR_CODE */ 1589 1587 1590 1588 1591 VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit) … … 1849 1852 { 1850 1853 return pVCpu->cpum.s.Guest.msrEFER; 1854 } 1855 1856 1857 /** 1858 * Looks up a CPUID leaf in the CPUID leaf array. 1859 * 1860 * @returns Pointer to the leaf if found, NULL if not. 1861 * 1862 * @param pVM Pointer to the cross context VM structure. 1863 * @param uLeaf The leaf to get. 1864 * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it 1865 * isn't. 1866 */ 1867 PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf) 1868 { 1869 unsigned iEnd = pVM->cpum.s.GuestInfo.cCpuIdLeaves; 1870 if (iEnd) 1871 { 1872 unsigned iStart = 0; 1873 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves); 1874 for (;;) 1875 { 1876 unsigned i = iStart + (iEnd - iStart) / 2U; 1877 if (uLeaf < paLeaves[i].uLeaf) 1878 { 1879 if (i <= iStart) 1880 return NULL; 1881 iEnd = i; 1882 } 1883 else if (uLeaf > paLeaves[i].uLeaf) 1884 { 1885 i += 1; 1886 if (i >= iEnd) 1887 return NULL; 1888 iStart = i; 1889 } 1890 else 1891 { 1892 uSubLeaf &= paLeaves[i].fSubLeafMask; 1893 if (uSubLeaf != paLeaves[i].uSubLeaf) 1894 { 1895 /* Find the right subleaf. We return the last one before 1896 uSubLeaf if we don't find an exact match. */ 1897 if (uSubLeaf < paLeaves[i].uSubLeaf) 1898 while ( i > 0 1899 && uLeaf == paLeaves[i].uLeaf 1900 && uSubLeaf < paLeaves[i].uSubLeaf) 1901 i--; 1902 else 1903 while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves 1904 && uLeaf == paLeaves[i + 1].uLeaf 1905 && uSubLeaf >= paLeaves[i + 1].uSubLeaf) 1906 i++; 1907 } 1908 return &paLeaves[i]; 1909 } 1910 } 1911 } 1912 1913 return NULL; 1851 1914 } 1852 1915 … … 1895 1958 if ( iLeaf == 4 1896 1959 && cCurrentCacheIndex < 3 1897 && pVM->cpum.s. enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)1960 && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL) 1898 1961 { 1899 1962 uint32_t type, level, sharing, linesize, … … 1997 2060 VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature) 1998 2061 { 2062 PCPUMCPUIDLEAF pLeaf; 2063 1999 2064 switch (enmFeature) 2000 2065 { … … 2003 2068 */ 2004 2069 case CPUMCPUIDFEATURE_APIC: 2005 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2006 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC; 2007 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 2008 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD) 2009 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC; 2070 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2071 if (pLeaf) 2072 pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_APIC; 2073 2074 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2075 if ( pLeaf 2076 && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD) 2077 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_APIC; 2078 2079 pVM->cpum.s.GuestFeatures.fApic = 1; 2010 2080 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled APIC\n")); 2011 2081 break; … … 2015 2085 */ 2016 2086 case CPUMCPUIDFEATURE_X2APIC: 2017 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2018 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC; 2087 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2088 if (pLeaf) 2089 pVM->cpum.s.aGuestCpuIdStd[1].ecx = pLeaf->uEcx |= X86_CPUID_FEATURE_ECX_X2APIC; 2090 pVM->cpum.s.GuestFeatures.fX2Apic = 1; 2019 2091 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n")); 2020 2092 break; … … 2025 2097 */ 2026 2098 case CPUMCPUIDFEATURE_SEP: 2027 { 2028 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP)) 2099 if (!pVM->cpum.s.HostFeatures.fSysEnter) 2029 2100 { 2030 2101 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n")); … … 2032 2103 } 2033 2104 2034 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2035 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP; 2105 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2106 if (pLeaf) 2107 pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_SEP; 2108 pVM->cpum.s.GuestFeatures.fSysEnter = 1; 2036 2109 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n")); 2037 2110 break; 2038 }2039 2111 2040 2112 /* … … 2043 2115 */ 2044 2116 case CPUMCPUIDFEATURE_SYSCALL: 2045 {2046 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x800000012047 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))2117 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2118 if ( !pLeaf 2119 || !pVM->cpum.s.HostFeatures.fSysCall) 2048 2120 { 2049 2121 #if HC_ARCH_BITS == 32 2050 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode. 2051 * Even when the cpu is capable of doing so in 64 bits mode. 2052 */ 2053 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001 2054 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE) 2055 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)) 2122 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit 2123 mode by Intel, even when the cpu is capable of doing so in 2124 64-bit mode. Long mode requires syscall support. */ 2125 if (!pVM->cpum.s.HostFeatures.fLongMode) 2056 2126 #endif 2057 2127 { … … 2060 2130 } 2061 2131 } 2132 2062 2133 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */ 2063 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL; 2134 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL; 2135 pVM->cpum.s.GuestFeatures.fSysCall = 1; 2064 2136 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n")); 2065 2137 break; 2066 }2067 2138 2068 2139 /* … … 2071 2142 */ 2072 2143 case CPUMCPUIDFEATURE_PAE: 2073 { 2074 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE)) 2144 if (!pVM->cpum.s.HostFeatures.fPae) 2075 2145 { 2076 2146 LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n")); … … 2078 2148 } 2079 2149 2080 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2081 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE; 2082 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 2083 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD) 2084 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE; 2150 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2151 if (pLeaf) 2152 pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_PAE; 2153 2154 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2155 if ( pLeaf 2156 && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD) 2157 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_PAE; 2158 2159 pVM->cpum.s.GuestFeatures.fPae = 1; 2085 2160 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n")); 2086 2161 break; 2087 }2088 2162 2089 2163 /* … … 2092 2166 */ 2093 2167 case CPUMCPUIDFEATURE_LONG_MODE: 2094 {2095 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x800000012096 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))2168 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2169 if ( !pLeaf 2170 || !pVM->cpum.s.HostFeatures.fLongMode) 2097 2171 { 2098 2172 LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n")); … … 2101 2175 2102 2176 /* Valid for both Intel and AMD. */ 2103 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE; 2177 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE; 2178 pVM->cpum.s.GuestFeatures.fLongMode = 1; 2104 2179 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n")); 2105 2180 break; 2106 }2107 2181 2108 2182 /* … … 2111 2185 */ 2112 2186 case CPUMCPUIDFEATURE_NX: 2113 {2114 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x800000012115 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))2187 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2188 if ( !pLeaf 2189 || !pVM->cpum.s.HostFeatures.fNoExecute) 2116 2190 { 2117 2191 LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n")); … … 2120 2194 2121 2195 /* Valid for both Intel and AMD. */ 2122 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX; 2196 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_NX; 2197 pVM->cpum.s.GuestFeatures.fNoExecute = 1; 2123 2198 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n")); 2124 2199 break; 2125 } 2200 2126 2201 2127 2202 /* … … 2130 2205 */ 2131 2206 case CPUMCPUIDFEATURE_LAHF: 2132 {2133 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x800000012134 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))2207 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2208 if ( !pLeaf 2209 || !pVM->cpum.s.HostFeatures.fLahfSahf) 2135 2210 { 2136 2211 LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n")); … … 2139 2214 2140 2215 /* Valid for both Intel and AMD. */ 2141 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF; 2216 pVM->cpum.s.aGuestCpuIdExt[1].ecx = pLeaf->uEcx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF; 2217 pVM->cpum.s.GuestFeatures.fLahfSahf = 1; 2142 2218 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n")); 2143 2219 break; 2144 } 2145 2220 2221 /* 2222 * Set the page attribute table bit. This is alternative page level 2223 * cache control that doesn't much matter when everything is 2224 * virtualized, though it may when passing thru device memory. 2225 */ 2146 2226 case CPUMCPUIDFEATURE_PAT: 2147 { 2148 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2149 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT; 2150 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 2151 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD) 2152 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT; 2227 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2228 if (pLeaf) 2229 pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_PAT; 2230 2231 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2232 if ( pLeaf 2233 && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD) 2234 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_PAT; 2235 2236 pVM->cpum.s.GuestFeatures.fPat = 1; 2153 2237 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n")); 2154 2238 break; 2155 }2156 2239 2157 2240 /* … … 2160 2243 */ 2161 2244 case CPUMCPUIDFEATURE_RDTSCP: 2162 {2163 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x800000012164 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)2165 || 2245 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2246 if ( !pLeaf 2247 || !pVM->cpum.s.HostFeatures.fRdTscP 2248 || pVM->cpum.s.u8PortableCpuIdLevel > 0) 2166 2249 { 2167 2250 if (!pVM->cpum.s.u8PortableCpuIdLevel) … … 2171 2254 2172 2255 /* Valid for both Intel and AMD. */ 2173 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP; 2256 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP; 2257 pVM->cpum.s.HostFeatures.fRdTscP = 1; 2174 2258 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n")); 2175 2259 break; 2176 }2177 2260 2178 2261 /* … … 2180 2263 */ 2181 2264 case CPUMCPUIDFEATURE_HVP: 2182 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2265 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2266 if (pLeaf) 2183 2267 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP; 2268 pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1; 2184 2269 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n")); 2185 2270 break; … … 2189 2274 break; 2190 2275 } 2276 2191 2277 for (VMCPUID i = 0; i < pVM->cCpus; i++) 2192 2278 { … … 2208 2294 switch (enmFeature) 2209 2295 { 2296 case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic; 2297 case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic; 2298 case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall; 2299 case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter; 2300 case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae; 2301 case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute; 2302 case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf; 2303 case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode; 2304 case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat; 2305 case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP; 2306 case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent; 2307 2308 case CPUMCPUIDFEATURE_INVALID: 2309 case CPUMCPUIDFEATURE_32BIT_HACK: 2310 break; 2311 } 2312 AssertFailed(); 2313 return false; 2314 } 2315 2316 2317 /** 2318 * Clears a CPUID feature bit. 2319 * 2320 * @param pVM Pointer to the VM. 2321 * @param enmFeature The feature to clear. 2322 */ 2323 VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature) 2324 { 2325 PCPUMCPUIDLEAF pLeaf; 2326 switch (enmFeature) 2327 { 2328 case CPUMCPUIDFEATURE_APIC: 2329 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2330 if (pLeaf) 2331 pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC; 2332 2333 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2334 if ( pLeaf 2335 && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD) 2336 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC; 2337 2338 pVM->cpum.s.GuestFeatures.fApic = 0; 2339 Log(("CPUM: ClearGuestCpuIdFeature: Disabled APIC\n")); 2340 break; 2341 2342 case CPUMCPUIDFEATURE_X2APIC: 2343 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2344 if (pLeaf) 2345 pVM->cpum.s.aGuestCpuIdStd[1].ecx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC; 2346 pVM->cpum.s.GuestFeatures.fX2Apic = 0; 2347 Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n")); 2348 break; 2349 2210 2350 case CPUMCPUIDFEATURE_PAE: 2211 { 2212 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2213 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE); 2214 break; 2215 } 2216 2217 case CPUMCPUIDFEATURE_NX: 2218 { 2219 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001) 2220 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX); 2221 } 2222 2223 case CPUMCPUIDFEATURE_SYSCALL: 2224 { 2225 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001) 2226 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL); 2227 } 2351 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2352 if (pLeaf) 2353 pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE; 2354 2355 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2356 if ( pLeaf 2357 && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD) 2358 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE; 2359 2360 pVM->cpum.s.GuestFeatures.fPae = 0; 2361 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n")); 2362 break; 2363 2364 case CPUMCPUIDFEATURE_PAT: 2365 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2366 if (pLeaf) 2367 pVM->cpum.s.aGuestCpuIdStd[1].edx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT; 2368 2369 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2370 if ( pLeaf 2371 && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD) 2372 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT; 2373 2374 pVM->cpum.s.GuestFeatures.fPat = 0; 2375 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n")); 2376 break; 2377 2378 case CPUMCPUIDFEATURE_LONG_MODE: 2379 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2380 if (pLeaf) 2381 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE; 2382 pVM->cpum.s.GuestFeatures.fLongMode = 0; 2383 break; 2384 2385 case CPUMCPUIDFEATURE_LAHF: 2386 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2387 if (pLeaf) 2388 pVM->cpum.s.aGuestCpuIdExt[1].ecx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF; 2389 pVM->cpum.s.GuestFeatures.fLahfSahf = 0; 2390 break; 2228 2391 2229 2392 case CPUMCPUIDFEATURE_RDTSCP: 2230 { 2231 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001) 2232 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP); 2233 break; 2234 } 2235 2236 case CPUMCPUIDFEATURE_LONG_MODE: 2237 { 2238 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001) 2239 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE); 2240 break; 2241 } 2393 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001), 0); 2394 if (pLeaf) 2395 pVM->cpum.s.aGuestCpuIdExt[1].edx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP; 2396 pVM->cpum.s.GuestFeatures.fRdTscP = 0; 2397 Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n")); 2398 break; 2399 2400 case CPUMCPUIDFEATURE_HVP: 2401 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2402 if (pLeaf) 2403 pVM->cpum.s.aGuestCpuIdStd[1].ecx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP; 2404 pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0; 2405 break; 2242 2406 2243 2407 default: … … 2245 2409 break; 2246 2410 } 2247 return false; 2248 } 2249 2250 2251 /** 2252 * Clears a CPUID feature bit. 2253 * 2254 * @param pVM Pointer to the VM. 2255 * @param enmFeature The feature to clear. 2256 */ 2257 VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature) 2258 { 2259 switch (enmFeature) 2260 { 2261 /* 2262 * Set the APIC bit in both feature masks. 2263 */ 2264 case CPUMCPUIDFEATURE_APIC: 2265 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2266 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC; 2267 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 2268 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD) 2269 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC; 2270 Log(("CPUM: ClearGuestCpuIdFeature: Disabled APIC\n")); 2271 break; 2272 2273 /* 2274 * Clear the x2APIC bit in the standard feature mask. 2275 */ 2276 case CPUMCPUIDFEATURE_X2APIC: 2277 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2278 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC; 2279 Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n")); 2280 break; 2281 2282 case CPUMCPUIDFEATURE_PAE: 2283 { 2284 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2285 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE; 2286 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 2287 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD) 2288 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE; 2289 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n")); 2290 break; 2291 } 2292 2293 case CPUMCPUIDFEATURE_PAT: 2294 { 2295 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2296 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT; 2297 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 2298 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD) 2299 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT; 2300 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n")); 2301 break; 2302 } 2303 2304 case CPUMCPUIDFEATURE_LONG_MODE: 2305 { 2306 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001) 2307 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE; 2308 break; 2309 } 2310 2311 case CPUMCPUIDFEATURE_LAHF: 2312 { 2313 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001) 2314 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF; 2315 break; 2316 } 2317 2318 case CPUMCPUIDFEATURE_RDTSCP: 2319 { 2320 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001) 2321 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP; 2322 Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n")); 2323 break; 2324 } 2325 2326 case CPUMCPUIDFEATURE_HVP: 2327 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1) 2328 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP; 2329 break; 2330 2331 default: 2332 AssertMsgFailed(("enmFeature=%d\n", enmFeature)); 2333 break; 2334 } 2411 2335 2412 for (VMCPUID i = 0; i < pVM->cCpus; i++) 2336 2413 { … … 2349 2426 VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM) 2350 2427 { 2351 return pVM->cpum.s.enmHostCpuVendor;2428 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor; 2352 2429 } 2353 2430 … … 2361 2438 VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM) 2362 2439 { 2363 return pVM->cpum.s.enmGuestCpuVendor;2440 return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor; 2364 2441 } 2365 2442 -
trunk/src/VBox/VMM/VMMAll/MMAll.cpp
r45640 r49893 568 568 TAG2STR(CFGM_USER); 569 569 570 TAG2STR(CPUM_CTX); 571 TAG2STR(CPUM_CPUID); 572 TAG2STR(CPUM_MSRS); 573 570 574 TAG2STR(CSAM); 571 575 TAG2STR(CSAM_PATCH); -
trunk/src/VBox/VMM/VMMAll/MMAllHyper.cpp
r44528 r49893 322 322 } 323 323 324 324 325 /** 325 326 * Wrapper for mmHyperAllocInternal … … 327 328 VMMDECL(int) MMHyperAlloc(PVM pVM, size_t cb, unsigned uAlignment, MMTAG enmTag, void **ppv) 328 329 { 329 int rc; 330 331 rc = mmHyperLock(pVM); 330 int rc = mmHyperLock(pVM); 332 331 AssertRCReturn(rc, rc); 333 332 … … 339 338 return rc; 340 339 } 340 341 342 /** 343 * Duplicates a block of memory. 344 */ 345 VMMDECL(int) MMHyperDupMem(PVM pVM, const void *pvSrc, size_t cb, unsigned uAlignment, MMTAG enmTag, void **ppv) 346 { 347 int rc = MMHyperAlloc(pVM, cb, uAlignment, enmTag, ppv); 348 if (RT_SUCCESS(rc)) 349 memcpy(*ppv, pvSrc, cb); 350 return rc; 351 } 352 341 353 342 354 /**
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