Changeset 49966 in vbox

Timestamp:

Dec 17, 2013 8:43:23 PM (11 years ago)

Author:

vboxsync

Message:

CPUM: Added AMD Athlon64 3200+ (130nm) and Pentium4 (mod 4, w/ 64-bit).

Location:

trunk

Files:

• include/VBox/vmm/cpum.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp (modified) (23 diffs)
• src/VBox/VMM/VMMR3/CPUMR3Db.cpp (modified) (3 diffs)
• src/VBox/VMM/VMMR3/cpus/AMD_Athlon_64_3200.h (added)
• src/VBox/VMM/VMMR3/cpus/Intel_Pentium_4_3_00GHz.h (added)
• src/VBox/VMM/include/CPUMInternal.h (modified) (9 diffs)
• src/VBox/VMM/tools/VBoxCpuReport.cpp (modified) (41 diffs)

trunk/include/VBox/vmm/cpum.h

@@ -240 +240 @@
     ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
 
-/** Predicate macro for catching AMD Family 8H CPUs (aka K8).    */
-#define CPUMMICROARCH_IS_AMD_FAM_8H(a_enmMicroarch) \
+/** Predicate macro for catching AMD Family OFh CPUs (aka K8).    */
+#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
     ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
 

trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp

@@ -221 +221 @@
 
 
+/** @callback_method_impl{FNCPUMRDMSR} */
+static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
+{
+    /** @todo fake microcode update. */
+    *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRMSR} */
+static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
+{
+    return VERR_CPUM_RAISE_GP_0;
+}
+
+
 /** @callback_method_impl{FNCPUMWRMSR} */
 static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
@@ -695 +711 @@
     /** @todo implement IA32_PERFSTATUS. */
     *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRMSR} */
+static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
+{
+    /* Pentium4 allows writing, but all bits are ignored. */
     return VINF_SUCCESS;
 }
@@ -1465 +1489 @@
 
 /** @callback_method_impl{FNCPUMRDMSR} */
+static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
+{
+    /** @todo P4 hard power on config */
+    *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRMSR} */
+static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
+{
+    /** @todo P4 hard power on config */
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMRDMSR} */
+static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
+{
+    /** @todo P4 soft power on config  */
+    *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRMSR} */
+static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
+{
+    /** @todo P4 soft power on config */
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMRDMSR} */
+static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
+{
+    /** @todo P4 bus frequency config  */
+    *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRMSR} */
+static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
+{
+    /** @todo P4 bus frequency config  */
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMRDMSR} */
 static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
@@ -2813 +2888 @@
 
 /** @callback_method_impl{FNCPUMRDMSR} */
+static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
+{
+    /** @todo AMD FIDVID_CTL. */
+    *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRMSR} */
+static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
+{
+    /** @todo AMD FIDVID_CTL. */
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMRDMSR} */
+static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
+{
+    /** @todo AMD FIDVID_STATUS. */
+    *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMRDMSR} */
 static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
@@ -3453 +3554 @@
 {
     /** @todo Changing CPUID leaf 0x80000001. */
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMRDMSR} */
+static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
+{
+    /** @todo Fake AMD microcode patching.  */
+    *puValue = pRange->uInitOrReadValue;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRMSR} */
+static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
+{
+    /** @todo Fake AMD microcode patching.  */
     return VINF_SUCCESS;
 }
@@ -4144 +4262 @@
     cpumMsrRd_Ia32ApicBase,
     cpumMsrRd_Ia32FeatureControl,
+    cpumMsrRd_Ia32BiosSignId,
     cpumMsrRd_Ia32SmmMonitorCtl,
     cpumMsrRd_Ia32PmcN,
@@ -4217 +4336 @@
 
     cpumMsrRd_IntelEblCrPowerOn,
+    cpumMsrRd_IntelP4EbcHardPowerOn,
+    cpumMsrRd_IntelP4EbcSoftPowerOn,
+    cpumMsrRd_IntelP4EbcFrequencyId,
     cpumMsrRd_IntelPlatformInfo100MHz,
     cpumMsrRd_IntelPlatformInfo133MHz,
@@ -4304 +4426 @@
     cpumMsrRd_AmdK8HwThermalCtrl,
     cpumMsrRd_AmdK8SwThermalCtrl,
+    cpumMsrRd_AmdK8FidVidControl,
+    cpumMsrRd_AmdK8FidVidStatus,
     cpumMsrRd_AmdK8McCtlMaskN,
     cpumMsrRd_AmdK8SmiOnIoTrapN,
@@ -4341 +4465 @@
     cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
     cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
+    cpumMsrRd_AmdK8PatchLevel,
     cpumMsrRd_AmdK7DebugStatusMaybe,
     cpumMsrRd_AmdK7BHTraceBaseMaybe,
@@ -4393 +4518 @@
     cpumMsrWr_Ia32ApicBase,
     cpumMsrWr_Ia32FeatureControl,
+    cpumMsrWr_Ia32BiosSignId,
     cpumMsrWr_Ia32BiosUpdateTrigger,
     cpumMsrWr_Ia32SmmMonitorCtl,
@@ -4415 +4541 @@
     cpumMsrWr_Ia32Dca0Cap,
     cpumMsrWr_Ia32PerfEvtSelN,
+    cpumMsrWr_Ia32PerfStatus,
     cpumMsrWr_Ia32PerfCtl,
     cpumMsrWr_Ia32FixedCtrN,
@@ -4446 +4573 @@
 
     cpumMsrWr_IntelEblCrPowerOn,
+    cpumMsrWr_IntelP4EbcHardPowerOn,
+    cpumMsrWr_IntelP4EbcSoftPowerOn,
+    cpumMsrWr_IntelP4EbcFrequencyId,
     cpumMsrWr_IntelPkgCStConfigControl,
     cpumMsrWr_IntelPmgIoCaptureBase,
@@ -4511 +4641 @@
     cpumMsrWr_AmdK8HwThermalCtrl,
     cpumMsrWr_AmdK8SwThermalCtrl,
+    cpumMsrWr_AmdK8FidVidControl,
     cpumMsrWr_AmdK8McCtlMaskN,
     cpumMsrWr_AmdK8SmiOnIoTrapN,
@@ -4547 +4678 @@
     cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
     cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
+    cpumMsrWr_AmdK8PatchLoader,
     cpumMsrWr_AmdK7DebugStatusMaybe,
     cpumMsrWr_AmdK7BHTraceBaseMaybe,
@@ -4785 +4917 @@
     CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
     CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
+    CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
     CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
     CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
@@ -4857 +4990 @@
 
     CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
+    CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
+    CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
+    CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
     CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo100MHz);
     CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo133MHz);
@@ -4944 +5080 @@
     CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
     CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
+    CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
+    CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
     CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
     CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
@@ -4981 +5119 @@
     CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
     CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
+    CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
     CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
     CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
@@ -5023 +5162 @@
     CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
     CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
+    CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
     CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
     CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
@@ -5045 +5185 @@
     CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
     CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
+    CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
     CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
     CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
@@ -5075 +5216 @@
 
     CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
+    CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
+    CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
+    CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
     CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
     CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
@@ -5140 +5284 @@
     CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
     CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
+    CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
     CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
     CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
@@ -5176 +5321 @@
     CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
     CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
+    CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
     CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
     CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);

trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp

@@ -173 +173 @@
 
 
-#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
 #include "cpus/Intel_Core_i7_3960X.h"
 #include "cpus/Intel_Core_i5_3570.h"
 #include "cpus/Intel_Xeon_X5482_3_20GHz.h"
+#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
+#include "cpus/Intel_Pentium_4_3_00GHz.h"
 
 #include "cpus/AMD_FX_8150_Eight_Core.h"
 #include "cpus/AMD_Phenom_II_X6_1100T.h"
 #include "cpus/Quad_Core_AMD_Opteron_2384.h"
+#include "cpus/AMD_Athlon_64_3200.h"
 
 
@@ -204 +206 @@
     &g_Entry_Intel_Xeon_X5482_3_20GHz,
 #endif
+#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
+    &g_Entry_Intel_Pentium_4_3_00GHz,
+#endif
+
 #ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
     &g_Entry_AMD_FX_8150_Eight_Core,
@@ -212 +218 @@
 #ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
     &g_Entry_Quad_Core_AMD_Opteron_2384,
+#endif
+#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
+    &g_Entry_AMD_Athlon_64_3200,
 #endif
 };

trunk/src/VBox/VMM/include/CPUMInternal.h

@@ -132 +132 @@
     kCpumMsrRdFn_Ia32ApicBase,
     kCpumMsrRdFn_Ia32FeatureControl,
+    kCpumMsrRdFn_Ia32BiosSignId,            /**< Range value returned. */
     kCpumMsrRdFn_Ia32SmmMonitorCtl,
     kCpumMsrRdFn_Ia32PmcN,
@@ -205 +206 @@
 
     kCpumMsrRdFn_IntelEblCrPowerOn,
+    kCpumMsrRdFn_IntelP4EbcHardPowerOn,
+    kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
+    kCpumMsrRdFn_IntelP4EbcFrequencyId,
     kCpumMsrRdFn_IntelPlatformInfo100MHz,
     kCpumMsrRdFn_IntelPlatformInfo133MHz,
@@ -292 +296 @@
     kCpumMsrRdFn_AmdK8HwThermalCtrl,        /**< Range value returned. */
     kCpumMsrRdFn_AmdK8SwThermalCtrl,
+    kCpumMsrRdFn_AmdK8FidVidControl,        /**< Range value returned. */
+    kCpumMsrRdFn_AmdK8FidVidStatus,         /**< Range value returned. */
     kCpumMsrRdFn_AmdK8McCtlMaskN,
     kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
@@ -329 +335 @@
     kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
     kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
+    kCpumMsrRdFn_AmdK8PatchLevel,           /**< Returns range value. */
     kCpumMsrRdFn_AmdK7DebugStatusMaybe,
     kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
@@ -390 +397 @@
     kCpumMsrWrFn_Ia32ApicBase,
     kCpumMsrWrFn_Ia32FeatureControl,
+    kCpumMsrWrFn_Ia32BiosSignId,
     kCpumMsrWrFn_Ia32BiosUpdateTrigger,
     kCpumMsrWrFn_Ia32SmmMonitorCtl,
@@ -412 +420 @@
     kCpumMsrWrFn_Ia32Dca0Cap,
     kCpumMsrWrFn_Ia32PerfEvtSelN,           /**< Range value indicates the register number. */
+    kCpumMsrWrFn_Ia32PerfStatus,
     kCpumMsrWrFn_Ia32PerfCtl,
     kCpumMsrWrFn_Ia32FixedCtrN,             /**< Takes register number of start of range. */
@@ -442 +451 @@
     kCpumMsrWrFn_Amd64TscAux,
     kCpumMsrWrFn_IntelEblCrPowerOn,
+    kCpumMsrWrFn_IntelP4EbcHardPowerOn,
+    kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
+    kCpumMsrWrFn_IntelP4EbcFrequencyId,
     kCpumMsrWrFn_IntelPkgCStConfigControl,
     kCpumMsrWrFn_IntelPmgIoCaptureBase,
@@ -507 +519 @@
     kCpumMsrWrFn_AmdK8HwThermalCtrl,
     kCpumMsrWrFn_AmdK8SwThermalCtrl,
+    kCpumMsrWrFn_AmdK8FidVidControl,
     kCpumMsrWrFn_AmdK8McCtlMaskN,
     kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
@@ -543 +556 @@
     kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
     kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
+    kCpumMsrWrFn_AmdK8PatchLoader,
     kCpumMsrWrFn_AmdK7DebugStatusMaybe,
     kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,

trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp

@@ -67 +67 @@
 /** Set if g_enmMicroarch indicates an Intel NetBurst CPU. */
 static bool             g_fIntelNetBurst = false;
-/** The report stream. */
+/** The alternative report stream. */
 static PRTSTREAM        g_pReportOut;
-/** The debug stream. */
+/** The alternative debug stream. */
 static PRTSTREAM        g_pDebugOut;
 
@@ -75 +75 @@
 static void vbCpuRepDebug(const char *pszMsg, ...)
 {
+    va_list va;
+
+    /* Always print a copy of the report to standard error. */
+    va_start(va, pszMsg);
+    RTStrmPrintfV(g_pStdErr, pszMsg, va);
+    va_end(va);
+    RTStrmFlush(g_pStdErr);
+
+    /* Alternatively, also print to a log file. */
     if (g_pDebugOut)
     {
-        va_list va;
         va_start(va, pszMsg);
         RTStrmPrintfV(g_pDebugOut, pszMsg, va);
         va_end(va);
         RTStrmFlush(g_pDebugOut);
-        RTThreadSleep(1);
-    }
+    }
+
+    /* Give the output device a chance to write / display it. */
+    RTThreadSleep(1);
 }
 
@@ -537 +547 @@
                      * Tweaks.  On Intel CPUs we've got trouble detecting
                      * IA32_BIOS_UPDT_TRIG (0x00000079), so we have to add it manually here.
+                     * Ditto on AMD with PATCH_LOADER (0xc0010020).
                      */
                     if (   uMsr == 0x00000079
@@ -542 +553 @@
                         && g_enmMicroarch >= kCpumMicroarch_Intel_P6_Core_Atom_First
                         && g_enmMicroarch <= kCpumMicroarch_Intel_End)
+                        fGp = false;
+                    if (   uMsr == 0xc0010020
+                        && fGp
+                        && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First
+                        && g_enmMicroarch <= kCpumMicroarch_AMD_End)
                         fGp = false;
                 }
@@ -588 +604 @@
         case 0x0000001b: return "IA32_APIC_BASE";
         case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */
-        case 0x0000002a: return "EBL_CR_POWERON";
+        case 0x0000002a: return g_fIntelNetBurst ? "P4_EBC_HARD_POWERON" : "EBL_CR_POWERON";
+        case 0x0000002b: return g_fIntelNetBurst ? "P4_EBC_SOFT_POWERON" : NULL;
+        case 0x0000002c: return g_fIntelNetBurst ? "P4_EBC_FREQUENCY_ID" : NULL;
         case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */
         case 0x0000002f: return "P6_UNK_0000_002f"; /* P6_M_Dothan. */
@@ -635 +653 @@
         case 0x0000006f: return "P6_UNK_0000_006f"; /* P6_M_Dothan. */
         case 0x00000079: return "IA32_BIOS_UPDT_TRIG";
+        case 0x00000080: return "P4_UNK_0000_0080";
         case 0x00000088: return "BBL_CR_D0";
         case 0x00000089: return "BBL_CR_D1";
         case 0x0000008a: return "BBL_CR_D2";
-        case 0x0000008b: return "BBL_CR_D3|BIOS_SIGN";
+        case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AMD_K8_PATCH_LEVEL"
+                              : g_fIntelNetBurst ? "IA32_BIOS_SIGN_ID" : "BBL_CR_D3|BIOS_SIGN";
         case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
         case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
@@ -748 +768 @@
         case 0x0000019f: return "P6_UNK_0000_019f"; /* P6_M_Dothan. */
         case 0x000001a0: return "IA32_MISC_ENABLE";
-        case 0x000001a1: return "P6_UNK_0000_01a1"; /* P6_M_Dothan. */
-        case 0x000001a2: return "I7_MSR_TEMPERATURE_TARGET"; /* SandyBridge, IvyBridge. */
+        case 0x000001a1: return g_fIntelNetBurst ? "MSR_PLATFORM_BRV" : "P6_UNK_0000_01a1" /* P6_M_Dothan. */;
+        case 0x000001a2: return g_fIntelNetBurst ? "P4_UNK_0000_01a2" : "I7_MSR_TEMPERATURE_TARGET" /* SandyBridge, IvyBridge. */;
         case 0x000001a4: return "I7_UNK_0000_01a4"; /* SandyBridge, IvyBridge. */
         case 0x000001a6: return "I7_MSR_OFFCORE_RSP_0";
@@ -768 +788 @@
                               ? "MSR_LASTBRANCH_TOS" : NULL /* Pentium M Dothan seems to have something else here. */;
         case 0x000001d3: return "P6_UNK_0000_01d3"; /* P6_M_Dothan. */
+        case 0x000001d7: return g_fIntelNetBurst ? "MSR_LER_FROM_LIP" : NULL;
+        case 0x000001d8: return g_fIntelNetBurst ? "MSR_LER_TO_LIP"   : NULL;
         case 0x000001d9: return "IA32_DEBUGCTL";
-        case 0x000001db: return "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
-        case 0x000001dc: return "P6_LAST_BRANCH_TO_IP";
-        case 0x000001dd: return "P6_LAST_INT_FROM_IP";
-        case 0x000001de: return "P6_LAST_INT_TO_IP";
+        case 0x000001da: return g_fIntelNetBurst ? "MSR_LASTBRANCH_TOS" : NULL;
+        case 0x000001db: return g_fIntelNetBurst ? "P6_LASTBRANCH_0" : "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
+        case 0x000001dc: return g_fIntelNetBurst ? "P6_LASTBRANCH_1" : "P6_LAST_BRANCH_TO_IP";
+        case 0x000001dd: return g_fIntelNetBurst ? "P6_LASTBRANCH_2" : "P6_LAST_INT_FROM_IP";
+        case 0x000001de: return g_fIntelNetBurst ? "P6_LASTBRANCH_3" : "P6_LAST_INT_TO_IP";
         case 0x000001e0: return "MSR_ROB_CR_BKUPTMPDR6";
         case 0x000001e1: return "I7_SB_UNK_0000_01e1";
@@ -866 +889 @@
         case 0x000002e7: return "I7_IB_UNK_0000_02e7"; /* IvyBridge */
         case 0x000002ff: return "IA32_MTRR_DEF_TYPE";
-        case 0x00000300: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_BPU_COUNTER0"   : "I7_SB_UNK_0000_0300" /* SandyBridge */;
-        case 0x00000305: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_MS_COUNTER1"    : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
-        case 0x00000309: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
-        case 0x0000030a: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
-        case 0x0000030b: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
+        case 0x00000300: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER0"   : "I7_SB_UNK_0000_0300" /* SandyBridge */;
+        case 0x00000301: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER1"   : NULL;
+        case 0x00000302: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER2"   : NULL;
+        case 0x00000303: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER3"   : NULL;
+        case 0x00000304: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER0"    : NULL;
+        case 0x00000305: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER1"    : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
+        case 0x00000306: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER2"    : NULL;
+        case 0x00000307: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER3"    : NULL;
+        case 0x00000308: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER0" : NULL;
+        case 0x00000309: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
+        case 0x0000030a: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
+        case 0x0000030b: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
+        case 0x0000030c: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER0" : NULL;
+        case 0x0000030d: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER1" : NULL;
+        case 0x0000030e: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER2" : NULL;
+        case 0x0000030f: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER3" : NULL;
+        case 0x00000310: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER4" : NULL;
+        case 0x00000311: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER5" : NULL;
         case 0x00000345: return "IA32_PERF_CAPABILITIES";
+        case 0x00000360: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR0"   : NULL;
+        case 0x00000361: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR1"   : NULL;
+        case 0x00000362: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR2"   : NULL;
+        case 0x00000363: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR3"   : NULL;
+        case 0x00000364: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR0"    : NULL;
+        case 0x00000365: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR1"    : NULL;
+        case 0x00000366: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR2"    : NULL;
+        case 0x00000367: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR3"    : NULL;
+        case 0x00000368: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR0" : NULL;
+        case 0x00000369: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR1" : NULL;
+        case 0x0000036a: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR2" : NULL;
+        case 0x0000036b: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR3" : NULL;
+        case 0x0000036c: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR0"    : NULL;
+        case 0x0000036d: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR1"    : NULL;
+        case 0x0000036e: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR2"    : NULL;
+        case 0x0000036f: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR3"    : NULL;
+        case 0x00000370: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR4"    : NULL;
+        case 0x00000371: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR5"    : NULL;
         case 0x0000038d: return "IA32_FIXED_CTR_CTRL";
         case 0x0000038e: return "IA32_PERF_GLOBAL_STATUS";
@@ -884 +938 @@
         case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_IvyBridge   ? NULL                                : "I7_IB_UNK_0000_0397";
         case 0x0000039c: return "I7_SB_MSR_PEBS_NUM_ALT";
-        case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */               : "I7_UNC_ARB_PERF_CTR0";       /* >= S,H */
-        case 0x000003b1: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X */               : "I7_UNC_ARB_PERF_CTR1";       /* >= S,H */
-        case 0x000003b2: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X */               : "I7_UNC_ARB_PERF_EVT_SEL0";   /* >= S,H */
-        case 0x000003b3: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X */               : "I7_UNC_ARB_PERF_EVT_SEL1";   /* >= S,H */
-        case 0x000003b4: return "I7_UNC_PMC4";
-        case 0x000003b5: return "I7_UNC_PMC5";
-        case 0x000003b6: return "I7_UNC_PMC6";
-        case 0x000003b7: return "I7_UNC_PMC7";
-        case 0x000003c0: return "I7_UNC_PERF_EVT_SEL0";
-        case 0x000003c1: return "I7_UNC_PERF_EVT_SEL1";
-        case 0x000003c2: return "I7_UNC_PERF_EVT_SEL2";
-        case 0x000003c3: return "I7_UNC_PERF_EVT_SEL3";
-        case 0x000003c4: return "I7_UNC_PERF_EVT_SEL4";
-        case 0x000003c5: return "I7_UNC_PERF_EVT_SEL5";
-        case 0x000003c6: return "I7_UNC_PERF_EVT_SEL6";
-        case 0x000003c7: return "I7_UNC_PERF_EVT_SEL7";
+        case 0x000003a0: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR0"   : NULL;
+        case 0x000003a1: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR1"   : NULL;
+        case 0x000003a2: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR0"   : NULL;
+        case 0x000003a3: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR1"   : NULL;
+        case 0x000003a4: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR0"  : NULL;
+        case 0x000003a5: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR1"  : NULL;
+        case 0x000003a6: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR0" : NULL;
+        case 0x000003a7: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR1" : NULL;
+        case 0x000003a8: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR0"   : NULL;
+        case 0x000003a9: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR1"   : NULL;
+        case 0x000003aa: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR0"   : NULL;
+        case 0x000003ab: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR1"   : NULL;
+        case 0x000003ac: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR0"   : NULL;
+        case 0x000003ad: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR1"   : NULL;
+        case 0x000003ae: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR0"  : NULL;
+        case 0x000003af: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR1"  : NULL;
+        case 0x000003b0: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */               : "I7_UNC_ARB_PERF_CTR0";       /* >= S,H */
+        case 0x000003b1: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X */               : "I7_UNC_ARB_PERF_CTR1";       /* >= S,H */
+        case 0x000003b2: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X */               : "I7_UNC_ARB_PERF_EVT_SEL0";   /* >= S,H */
+        case 0x000003b3: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X */               : "I7_UNC_ARB_PERF_EVT_SEL1";   /* >= S,H */
+        case 0x000003b4: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR0"    : "I7_UNC_PMC4";
+        case 0x000003b5: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR1"    : "I7_UNC_PMC5";
+        case 0x000003b6: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR0"  : "I7_UNC_PMC6";
+        case 0x000003b7: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR1"  : "I7_UNC_PMC7";
+        case 0x000003b8: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR0"   : NULL;
+        case 0x000003b9: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR1"   : NULL;
+        case 0x000003ba: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR0"    : NULL;
+        case 0x000003bb: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR1"    : NULL;
+        case 0x000003bc: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR0"   : NULL;
+        case 0x000003bd: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR1"   : NULL;
+        case 0x000003be: return g_fIntelNetBurst ? "P4_MSR_SSU_ESCR0"   : NULL;
+        case 0x000003c0: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR0"    : "I7_UNC_PERF_EVT_SEL0";
+        case 0x000003c1: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR1"    : "I7_UNC_PERF_EVT_SEL1";
+        case 0x000003c2: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR0"  : "I7_UNC_PERF_EVT_SEL2";
+        case 0x000003c3: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR1"  : "I7_UNC_PERF_EVT_SEL3";
+        case 0x000003c4: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR0"    : "I7_UNC_PERF_EVT_SEL4";
+        case 0x000003c5: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR1"    : "I7_UNC_PERF_EVT_SEL5";
+        case 0x000003c6: return g_fIntelNetBurst ? NULL                 : "I7_UNC_PERF_EVT_SEL6";
+        case 0x000003c7: return g_fIntelNetBurst ? NULL                 : "I7_UNC_PERF_EVT_SEL7";
+        case 0x000003c8: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0"    : NULL;
+        case 0x000003c9: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0"    : NULL;
+        case 0x000003ca: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR0"   : NULL;
+        case 0x000003cb: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR1"   : NULL;
+        case 0x000003cc: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR2"   : NULL;
+        case 0x000003cd: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR3"   : NULL;
+        case 0x000003e0: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR4"   : NULL;
+        case 0x000003e1: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR5"   : NULL;
+        case 0x000003f0: return g_fIntelNetBurst ? "P4_MSR_TC_PRECISE_EVENT" : NULL;
         case 0x000003f1: return "IA32_PEBS_ENABLE";
-        case 0x000003f6: return "I7_MSR_PEBS_LD_LAT";
-        case 0x000003f8: return "I7_MSR_PKG_C3_RESIDENCY";
+        case 0x000003f2: return g_fIntelNetBurst ? "P4_MSR_PEBS_MATRIX_VERT" : "IA32_PEBS_ENABLE";
+        case 0x000003f3: return g_fIntelNetBurst ? "P4_UNK_0000_03f3" : NULL;
+        case 0x000003f4: return g_fIntelNetBurst ? "P4_UNK_0000_03f4" : NULL;
+        case 0x000003f5: return g_fIntelNetBurst ? "P4_UNK_0000_03f5" : NULL;
+        case 0x000003f6: return g_fIntelNetBurst ? "P4_UNK_0000_03f6" : "I7_MSR_PEBS_LD_LAT";
+        case 0x000003f7: return g_fIntelNetBurst ? "P4_UNK_0000_03f7" : "I7_MSR_PEBS_LD_LAT";
+        case 0x000003f8: return g_fIntelNetBurst ? "P4_UNK_0000_03f8" : "I7_MSR_PKG_C3_RESIDENCY";
         case 0x000003f9: return "I7_MSR_PKG_C6_RESIDENCY";
         case 0x000003fa: return "I7_MSR_PKG_C7_RESIDENCY";
@@ -1074 +1165 @@
         case 0xc001001e: return "AMD_K8_MANID";
         case 0xc001001f: return "AMD_K8_NB_CFG1";
-        case 0xc0010021: return "AMD_10H_UNK_c001_0021";
+        case 0xc0010020: return "AMD_K8_PATCH_LOADER";
+        case 0xc0010021: return "AMD_K8_UNK_c001_0021";
         case 0xc0010022: return "AMD_K8_MC_XCPT_REDIR";
         case 0xc0010028: return "AMD_K8_UNK_c001_0028";
@@ -1090 +1182 @@
         case 0xc001003e: return "AMD_K8_HTC";
         case 0xc001003f: return "AMD_K8_STC";
+        case 0xc0010041: return "AMD_K8_FIDVID_CTL";
+        case 0xc0010042: return "AMD_K8_FIDVID_STATUS";
         case 0xc0010043: return "AMD_K8_THERMTRIP_STATUS"; /* BDKG says it was removed in K8 revision C.*/
         case 0xc0010044: return "AMD_K8_MC_CTL_MASK_0";
@@ -1138 +1232 @@
         case 0xc0010112: return "AMD_K8_SMM_ADDR";
         case 0xc0010113: return "AMD_K8_SMM_MASK";
-        case 0xc0010114: return "AMD_K8_VM_CR";
-        case 0xc0010115: return "AMD_K8_IGNNE";
-        case 0xc0010116: return "AMD_K8_SMM_CTL";
-        case 0xc0010117: return "AMD_K8_VM_HSAVE_PA";
-        case 0xc0010118: return "AMD_10H_VM_LOCK_KEY";
-        case 0xc0010119: return "AMD_10H_SSM_LOCK_KEY";
-        case 0xc001011a: return "AMD_10H_LOCAL_SMI_STS";
+        case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_CR"          : "AMD_K8_UNK_c001_0114";
+        case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AMD_K8_IGNNE"          : "AMD_K8_UNK_c001_0115";
+        case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AMD_K8_SMM_CTL"        : "AMD_K8_UNK_c001_0116";
+        case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_HSAVE_PA"    : "AMD_K8_UNK_c001_0117";
+        case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_10H_VM_LOCK_KEY"   : "AMD_K8_UNK_c001_0118";
+        case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AMD_10H_SSM_LOCK_KEY"  : "AMD_K8_UNK_c001_0119";
+        case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AMD_10H_LOCAL_SMI_STS" : "AMD_K8_UNK_c001_011a";
+        case 0xc001011b: return "AMD_K8_UNK_c001_011b";
+        case 0xc001011c: return "AMD_K8_UNK_c001_011c";
         case 0xc0010140: return "AMD_10H_OSVW_ID_LEN";
         case 0xc0010141: return "AMD_10H_OSVW_STS";
@@ -1538 +1634 @@
         case 0x00000010: return "Ia32TimestampCounter";
         case 0x0000001b: return "Ia32ApicBase";
-        case 0x0000002a: *pfTakesValue = true; return "IntelEblCrPowerOn";
+        case 0x0000002a: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcHardPowerOn" : "IntelEblCrPowerOn";
+        case 0x0000002b: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcSoftPowerOn" : NULL;
+        case 0x0000002c: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcFrequencyId" : NULL;
         //case 0x00000033: return "IntelTestCtl";
         case 0x0000003a: return "Ia32FeatureControl";
@@ -1552 +1650 @@
             return "IntelLastBranchFromToN";
 
+        case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AmdK8PatchLevel" : "Ia32BiosSignId";
         case 0x0000009b: return "Ia32SmmMonitorCtl";
 
@@ -1609 +1708 @@
         case 0x00000186: return "Ia32PerfEvtSelN";
         case 0x00000187: return "Ia32PerfEvtSelN";
-        case 0x00000193: return /*CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL :*/ NULL /* Core2_Penryn. */;
+        case 0x00000193: return /*g_fIntelNetBurst ? NULL :*/ NULL /* Core2_Penryn. */;
         case 0x00000198: *pfTakesValue = true; return "Ia32PerfStatus";
         case 0x00000199: *pfTakesValue = true; return "Ia32PerfCtl";
@@ -1626 +1725 @@
                                 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
                               ? "IntelLastBranchTos" : NULL /* Pentium M Dothan seems to have something else here. */;
+        case 0x000001d7: return g_fIntelNetBurst ? "P6LastIntFromIp" : NULL;
+        case 0x000001d8: return g_fIntelNetBurst ? "P6LastIntToIp"   : NULL;
         case 0x000001d9: return "Ia32DebugCtl";
-        case 0x000001db: return "P6LastBranchFromIp";
-        case 0x000001dc: return "P6LastBranchToIp";
-        case 0x000001dd: return "P6LastIntFromIp";
-        case 0x000001de: return "P6LastIntToIp";
+        case 0x000001da: return g_fIntelNetBurst ? "IntelLastBranchTos" : NULL;
+        case 0x000001db: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchFromIp";
+        case 0x000001dc: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchToIp";
+        case 0x000001dd: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntFromIp";
+        case 0x000001de: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntToIp";
         case 0x000001f0: return "IntelI7VirtualLegacyWireCap"; /* SandyBridge. */
         case 0x000001f2: return "Ia32SmrrPhysBase";
@@ -1667 +1769 @@
 
         case 0x000002ff: return "Ia32MtrrDefType";
-        //case 0x00000305: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? TODO : NULL;
-        case 0x00000309: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
-        case 0x0000030a: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
-        case 0x0000030b: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
+        //case 0x00000305: return g_fIntelNetBurst ? TODO : NULL;
+        case 0x00000309: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
+        case 0x0000030a: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
+        case 0x0000030b: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
         case 0x00000345: *pfTakesValue = true; return "Ia32PerfCapabilities";
+        /* Note! Lots of P4 MSR 0x00000360..0x00000371. */
         case 0x0000038d: return "Ia32FixedCtrCtrl";
         case 0x0000038e: *pfTakesValue = true; return "Ia32PerfGlobalStatus";
@@ -1683 +1786 @@
         case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncCBoxConfig";       /* >= S,H */
         case 0x0000039c: return "IntelI7SandyPebsNumAlt";
-        case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfCtrN";      /* >= S,H */
-        case 0x000003b1: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfCtrN";      /* >= S,H */
-        case 0x000003b2: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfEvtSelN";   /* >= S,H */
-        case 0x000003b3: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfEvtSelN";   /* >= S,H */
+         /* Note! Lots of P4 MSR 0x000003a0..0x000003e1. */
+        case 0x000003b0: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfCtrN";      /* >= S,H */
+        case 0x000003b1: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfCtrN";      /* >= S,H */
+        case 0x000003b2: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfEvtSelN";   /* >= S,H */
+        case 0x000003b3: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */            : "IntelI7UncArbPerfEvtSelN";   /* >= S,H */
         case 0x000003b4: case 0x000003b5: case 0x000003b6: case 0x000003b7:
-            return "IntelI7UncPmcN";
+            return g_fIntelNetBurst ? NULL : "IntelI7UncPmcN";
         case 0x000003c0: case 0x000003c1: case 0x000003c2: case 0x000003c3:
         case 0x000003c4: case 0x000003c5: case 0x000003c6: case 0x000003c7:
-            return "IntelI7UncPerfEvtSelN";
+            return g_fIntelNetBurst ? NULL : "IntelI7UncPerfEvtSelN";
         case 0x000003f1: return "Ia32PebsEnable";
-        case 0x000003f6: return "IntelI7PebsLdLat";
-        case 0x000003f8: return "IntelI7PkgCnResidencyN";
+        case 0x000003f6: return g_fIntelNetBurst ? NULL /*??*/ : "IntelI7PebsLdLat";
+        case 0x000003f8: return g_fIntelNetBurst ? NULL : "IntelI7PkgCnResidencyN";
         case 0x000003f9: return "IntelI7PkgCnResidencyN";
         case 0x000003fa: return "IntelI7PkgCnResidencyN";
@@ -1818 +1922 @@
         case 0xc001001a: case 0xc001001d: return "AmdK8TopOfMemN";
         case 0xc001001f: return "AmdK8NbCfg1";
+        case 0xc0010020: return "AmdK8PatchLoader";
         case 0xc0010022: return "AmdK8McXcptRedir";
         case 0xc0010030: case 0xc0010031: case 0xc0010032:
@@ -1824 +1929 @@
         case 0xc001003e: *pfTakesValue = true; return "AmdK8HwThermalCtrl";
         case 0xc001003f: return "AmdK8SwThermalCtrl";
+        case 0xc0010041: *pfTakesValue = true; return "AmdK8FidVidControl";
+        case 0xc0010042: *pfTakesValue = true; return "AmdK8FidVidStatus";
         case 0xc0010044: case 0xc0010045: case 0xc0010046: case 0xc0010047:
         case 0xc0010048: case 0xc0010049: case 0xc001004a: //case 0xc001004b:
@@ -1853 +1960 @@
         case 0xc0010112: return "AmdK8SmmAddr";     /** @todo probably misdetected ign/gp due to locking */
         case 0xc0010113: return "AmdK8SmmMask";     /** @todo probably misdetected ign/gp due to locking */
-        case 0xc0010114: return "AmdK8VmCr";        /** @todo probably misdetected due to locking */
-        case 0xc0010115: return "AmdK8IgnNe";
-        case 0xc0010116: return "AmdK8SmmCtl";
-        case 0xc0010117: return "AmdK8VmHSavePa";   /** @todo probably misdetected due to locking */
-        case 0xc0010118: return "AmdFam10hVmLockKey";
-        case 0xc0010119: return "AmdFam10hSmmLockKey"; /* Not documented by BKDG, found in netbsd patch. */
-        case 0xc001011a: return "AmdFam10hLocalSmiStatus";
+        case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmCr" : NULL;        /** @todo probably misdetected due to locking */
+        case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AmdK8IgnNe" : NULL;
+        case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AmdK8SmmCtl" : NULL;
+        case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmHSavePa" : NULL;   /** @todo probably misdetected due to locking */
+        case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdFam10hVmLockKey" : NULL;
+        case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AmdFam10hSmmLockKey" : NULL; /* Not documented by BKDG, found in netbsd patch. */
+        case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm      ? "AmdFam10hLocalSmiStatus" : NULL;
         case 0xc0010140: *pfTakesValue = true; return "AmdFam10hOsVisWrkIdLength";
         case 0xc0010141: *pfTakesValue = true; return "AmdFam10hOsVisWrkStatus";
@@ -2035 +2142 @@
         case 0x00000040: case 0x00000041: case 0x00000042: case 0x00000043:
         case 0x00000044: case 0x00000045: case 0x00000046: case 0x00000047:
+        case 0x00000600:
             if (g_enmMicroarch >= kCpumMicroarch_Intel_Core2_First)
                 return UINT64_C(0xffff800000000000);
             break;
+
+
+        /* Write only bits. */
+        case 0xc0010041: return RT_BIT_64(16); /* FIDVID_CTL.InitFidVid */
 
         /* Time counters - fudge them to avoid incorrect ignore masks. */
@@ -2106 +2218 @@
             return VBCPUREPBADNESS_BOND_VILLAIN;
 
+        case 0xc0011012:
+            if (CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch))
+                return VBCPUREPBADNESS_MIGHT_BITE;
+            break;
+
         case 0x000001a0: /* IA32_MISC_ENABLE */
         case 0x00000199: /* IA32_PERF_CTL */
@@ -2721 +2838 @@
     uint64_t fSkipMask = 0;
 
-    /** @todo test & adjust on P4. */
-    if (   (   g_enmMicroarch >= kCpumMicroarch_Intel_NB_First
-            && g_enmMicroarch <= kCpumMicroarch_Intel_NB_End)
-        || (   g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Broadwell
+    if (   (   g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Broadwell
             && g_enmMicroarch <= kCpumMicroarch_Intel_Core7_End)
         || (   g_enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
@@ -3015 +3129 @@
         || vbCpuRepSupportsNX())
         fSkipMask |= MSR_K6_EFER_NXE;
+
+    /* NetBurst prescott 2MB (model 4) hung or triple faulted here.  The extra
+       sleep or something seemed to help for some screwed up reason. */
+    if (g_fIntelNetBurst)
+    {
+        // This doesn't matter:
+        //fSkipMask |= MSR_K6_EFER_SCE;
+        //if (vbCpuRepSupportsLongMode())
+        //    fSkipMask |= MSR_K6_EFER_LMA;
+        //vbCpuRepDebug("EFER - netburst workaround - ignore SCE & LMA (fSkipMask=%#llx)\n", fSkipMask);
+
+        vbCpuRepDebug("EFER - netburst sleep fudge - fSkipMask=%#llx\n", fSkipMask);
+        RTThreadSleep(1000);
+    }
+
     return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, NULL);
 }
@@ -3179 +3308 @@
     if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
         fSkipMask |= RT_BIT(9);  /* SetDirtyEnS */
-    if (   CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
+    if (   CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
         || CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
         fSkipMask |= RT_BIT(8);  /* SetDirtyEnE */
-    if (   CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
+    if (   CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
         || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
         fSkipMask |= RT_BIT(7)   /* SysVicLimit */
@@ -3213 +3342 @@
                   |  RT_BIT(9);  /* MonMwaitDis */
     fSkipMask |= RT_BIT(8);      /* #IGNNE port emulation */
-    if (   CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
+    if (   CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
         || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
         fSkipMask |= RT_BIT(7)   /* DisLock */
@@ -3219 +3348 @@
     fSkipMask |= RT_BIT(4);      /* INVD to WBINVD */
     fSkipMask |= RT_BIT(3);      /* TLBCACHEDIS */
-    if (   CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
+    if (   CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
         || CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
         || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
@@ -3480 +3609 @@
         uint64_t    uValue     = paMsrs[i].uValue;
         int         rc;
-#if 0
-        if (uMsr >= 0x10011007)
+#if 1
+        if (uMsr >= 0xc0000000 && g_fIntelNetBurst)
         {
             vbCpuRepDebug("produceMsrReport: uMsr=%#x (%s)...\n", uMsr, getMsrNameHandled(uMsr));
@@ -3524 +3653 @@
         else if (uMsr >= 0x000001a6 && uMsr <= 0x000001a7)
             rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 2 /*cMax*/, "IntelI7MsrOffCoreResponseN", &i);
+        else if (uMsr == 0x000001db && g_fIntelNetBurst)
+            rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4 /*cMax*/, "IntelLastBranchFromToN", &i);
         else if (uMsr == 0x00000200)
             rc = reportMsr_Ia32MtrrPhysBaseMaskN(&paMsrs[i], cMsrs - i, &i);
@@ -3532 +3663 @@
         else if (uMsr == 0x000002ff)
             rc = reportMsr_Ia32MtrrDefType(uMsr);
-        else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b)
+        else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b && !g_fIntelNetBurst)
             rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, false, 0, &i);
-        else if (uMsr == 0x000003f8 || uMsr == 0x000003fc || uMsr == 0x0000060a)
+        else if ((uMsr == 0x000003f8 || uMsr == 0x000003fc || uMsr == 0x0000060a) && !g_fIntelNetBurst)
             rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, false, 0, &i);
-        else if (uMsr == 0x000003f9 || uMsr == 0x000003fd || uMsr == 0x0000060b)
+        else if ((uMsr == 0x000003f9 || uMsr == 0x000003fd || uMsr == 0x0000060b) && !g_fIntelNetBurst)
             rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, false, 0, &i);
-        else if (uMsr == 0x000003fa || uMsr == 0x000003fe || uMsr == 0x0000060c)
+        else if ((uMsr == 0x000003fa || uMsr == 0x000003fe || uMsr == 0x0000060c) && !g_fIntelNetBurst)
             rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, false, 0, &i);
         else if (uMsr >= 0x00000400 && uMsr <= 0x00000477)
@@ -3545 +3676 @@
             rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8, NULL, &i);
         else if (uMsr == 0x00000680 || uMsr == 0x000006c0)
-            rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false, UINT64_C(0xffff800000000000), &i);
+            rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false,
+                                              g_fIntelNetBurst
+                                              ? UINT64_C(0xffffffffffffff00) /* kludge */
+                                              : UINT64_C(0xffff800000000000), &i);
         else if (uMsr >= 0x00000800 && uMsr <= 0x000008ff)
             rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i);
@@ -3594 +3728 @@
         else if (uMsr == 0xc0010070)
             rc = reportMsr_AmdFam10hCofVidControl(uMsr, uValue);
-        else if (uMsr == 0xc0010118 || uMsr == 0xc0010119)
+        else if ((uMsr == 0xc0010118 || uMsr == 0xc0010119) && getMsrFnName(uMsr, NULL))
             rc = printMsrFunction(uMsr, NULL, NULL, annotateValue(uValue)); /* RAZ, write key. */
         else if (uMsr == 0xc0010200)
@@ -3655 +3789 @@
 #else
 
-    uint32_t uMsr = 0xc0010015;
+    uint32_t uMsr = 0xc0000080;
     uint64_t uValue = 0;
     msrProberRead(uMsr, &uValue);
-    reportMsr_AmdK8HwCr(uMsr, uValue);
+    reportMsr_Amd64Efer(uMsr, uValue);
 #endif
     return VINF_SUCCESS;
@@ -3928 +4062 @@
             if (!RT_C_IS_ALNUM(*psz) && *psz != '_')
                 *psz = '_';
+        for (size_t off = strlen(szNameC); off > 1 && szNameC[off - 1] == '_'; off--)
+            szNameC[off - 1] = '\0';
         vbCpuRepDebug("NameC: %s\n", szNameC);
     }
@@ -4070 +4206 @@
         { "--msrs-dev",  'd', RTGETOPT_REQ_NOTHING },
         { "--output",    'o', RTGETOPT_REQ_STRING  },
+        { "--log",       'l', RTGETOPT_REQ_STRING  },
     };
     RTGETOPTSTATE State;
@@ -4082 +4219 @@
     g_pReportOut = NULL;
     g_pDebugOut  = g_pStdErr;
-    const char *pszOutput = NULL;
+    const char *pszOutput   = NULL;
+    const char *pszDebugOut = NULL;
 
     int iOpt;
@@ -4102 +4240 @@
                 break;
 
+            case 'l':
+                pszDebugOut = ValueUnion.psz;
+                break;
+
             case 'h':
-                RTPrintf("Usage: VBoxCpuReport [-m|--msrs-only] [-d|--msrs-dev] [-h|--help] [-V|--version]\n");
+                RTPrintf("Usage: VBoxCpuReport [-m|--msrs-only] [-d|--msrs-dev] [-h|--help] [-V|--version] [-o filename.h] [-l debug.log]\n");
                 RTPrintf("Internal tool for gathering information to the VMM CPU database.\n");
                 return RTEXITCODE_SUCCESS;
@@ -4111 +4253 @@
             default:
                 return RTGetOptPrintError(iOpt, &ValueUnion);
+        }
+    }
+
+    /*
+     * Open the alternative debug log stream.
+     */
+    if (pszDebugOut)
+    {
+        if (RTFileExists(pszDebugOut) && !RTSymlinkExists(pszDebugOut))
+        {
+            char szOld[RTPATH_MAX];
+            rc = RTStrCopy(szOld, sizeof(szOld), pszDebugOut);
+            if (RT_SUCCESS(rc))
+                rc = RTStrCat(szOld, sizeof(szOld), ".old");
+            if (RT_SUCCESS(rc))
+                RTFileRename(pszDebugOut, szOld, RTFILEMOVE_FLAGS_REPLACE);
+        }
+        rc = RTStrmOpen(pszDebugOut, "w", &g_pDebugOut);
+        if (RT_FAILURE(rc))
+        {
+            RTMsgError("Error opening '%s': %Rrc", pszDebugOut, rc);
+            g_pDebugOut = NULL;
         }
     }
@@ -4147 +4311 @@
             break;
     }
+
+    /*
+     * Close the output files.
+     */
+    if (g_pReportOut)
+    {
+        RTStrmClose(g_pReportOut);
+        g_pReportOut = NULL;
+    }
+
+    if (g_pDebugOut)
+    {
+        RTStrmClose(g_pDebugOut);
+        g_pDebugOut = NULL;
+    }
+
     return RT_SUCCESS(rc) ? RTEXITCODE_SUCCESS : RTEXITCODE_FAILURE;
 }
 
-