Changeset 49972 in vbox
- Timestamp:
- Dec 18, 2013 1:10:58 PM (11 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r49966 r49972 78 78 * @param idMsr The MSR we're writing. 79 79 * @param pRange The MSR range descriptor. 80 * @param uValue The value to set. 80 * @param uValue The value to set, ignored bits masked. 81 * @param uRawValue The raw value with the ignored bits not masked. 81 82 */ 82 typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue );83 typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue); 83 84 /** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */ 84 85 typedef FNCPUMWRMSR *PFNCPUMWRMSR; … … 96 97 static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 97 98 { 98 *puValue = pRange->u InitOrReadValue;99 return VINF_SUCCESS; 100 } 101 102 103 /** @callback_method_impl{FNCPUMWRMSR} */ 104 static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )99 *puValue = pRange->uValue; 100 return VINF_SUCCESS; 101 } 102 103 104 /** @callback_method_impl{FNCPUMWRMSR} */ 105 static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 105 106 { 106 107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue)); … … 117 118 118 119 /** @callback_method_impl{FNCPUMWRMSR} */ 119 static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )120 static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 120 121 { 121 122 Assert(pRange->fWrGpMask == UINT64_MAX); … … 141 142 142 143 /** @callback_method_impl{FNCPUMWRMSR} */ 143 static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )144 static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 144 145 { 145 146 /** @todo implement machine check injection. */ … … 157 158 158 159 /** @callback_method_impl{FNCPUMWRMSR} */ 159 static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )160 static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 160 161 { 161 162 /** @todo implement machine check injection. */ … … 173 174 174 175 /** @callback_method_impl{FNCPUMWRMSR} */ 175 static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )176 static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 176 177 { 177 178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue); … … 197 198 198 199 /** @callback_method_impl{FNCPUMWRMSR} */ 199 static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )200 static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 200 201 { 201 202 int rc = PDMApicSetBase(pVCpu, uValue); … … 215 216 216 217 /** @callback_method_impl{FNCPUMWRMSR} */ 217 static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )218 static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 218 219 { 219 220 return VERR_CPUM_RAISE_GP_0; … … 225 226 { 226 227 /** @todo fake microcode update. */ 227 *puValue = pRange->u InitOrReadValue;228 return VINF_SUCCESS; 229 } 230 231 232 /** @callback_method_impl{FNCPUMWRMSR} */ 233 static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )228 *puValue = pRange->uValue; 229 return VINF_SUCCESS; 230 } 231 232 233 /** @callback_method_impl{FNCPUMWRMSR} */ 234 static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 234 235 { 235 236 return VERR_CPUM_RAISE_GP_0; … … 238 239 239 240 /** @callback_method_impl{FNCPUMWRMSR} */ 240 static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )241 static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 241 242 { 242 243 /** @todo Fake bios update trigger better. The value is the address to an … … 256 257 257 258 /** @callback_method_impl{FNCPUMWRMSR} */ 258 static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )259 static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 259 260 { 260 261 /** @todo SMM. */ … … 273 274 274 275 /** @callback_method_impl{FNCPUMWRMSR} */ 275 static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )276 static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 276 277 { 277 278 /** @todo check CPUID leaf 0ah. */ … … 290 291 291 292 /** @callback_method_impl{FNCPUMWRMSR} */ 292 static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )293 static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 293 294 { 294 295 /** @todo should remember writes, though it's supposedly something only a BIOS … … 308 309 309 310 /** @callback_method_impl{FNCPUMWRMSR} */ 310 static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )311 static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 311 312 { 312 313 /** @todo Write MPERF: Calc adjustment. */ … … 326 327 327 328 /** @callback_method_impl{FNCPUMWRMSR} */ 328 static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )329 static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 329 330 { 330 331 /** @todo Write APERF: Calc adjustment. */ … … 353 354 { 354 355 /** @todo Implement variable MTRR storage. */ 355 Assert(pRange->u InitOrReadValue == (idMsr - 0x200) / 2);356 *puValue = 0; 357 return VINF_SUCCESS; 358 } 359 360 361 /** @callback_method_impl{FNCPUMWRMSR} */ 362 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )356 Assert(pRange->uValue == (idMsr - 0x200) / 2); 357 *puValue = 0; 358 return VINF_SUCCESS; 359 } 360 361 362 /** @callback_method_impl{FNCPUMWRMSR} */ 363 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 363 364 { 364 365 /* 365 366 * Validate the value. 366 367 */ 367 Assert(pRange->u InitOrReadValue == (idMsr - 0x200) / 2);368 Assert(pRange->uValue == (idMsr - 0x200) / 2); 368 369 369 370 if ((uValue & 0xff) >= 7) … … 393 394 { 394 395 /** @todo Implement variable MTRR storage. */ 395 Assert(pRange->u InitOrReadValue == (idMsr - 0x200) / 2);396 *puValue = 0; 397 return VINF_SUCCESS; 398 } 399 400 401 /** @callback_method_impl{FNCPUMWRMSR} */ 402 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )396 Assert(pRange->uValue == (idMsr - 0x200) / 2); 397 *puValue = 0; 398 return VINF_SUCCESS; 399 } 400 401 402 /** @callback_method_impl{FNCPUMWRMSR} */ 403 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 403 404 { 404 405 /* 405 406 * Validate the value. 406 407 */ 407 Assert(pRange->u InitOrReadValue == (idMsr - 0x200) / 2);408 Assert(pRange->uValue == (idMsr - 0x200) / 2); 408 409 409 410 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U); … … 433 434 434 435 /** @callback_method_impl{FNCPUMWRMSR} */ 435 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )436 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 436 437 { 437 438 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr); … … 460 461 461 462 /** @callback_method_impl{FNCPUMWRMSR} */ 462 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )463 static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 463 464 { 464 465 if ((uValue & 0xff) >= 7) … … 482 483 483 484 /** @callback_method_impl{FNCPUMWRMSR} */ 484 static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )485 static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 485 486 { 486 487 pVCpu->cpum.s.Guest.msrPAT = uValue; … … 498 499 499 500 /** @callback_method_impl{FNCPUMWRMSR} */ 500 static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )501 static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 501 502 { 502 503 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and … … 516 517 517 518 /** @callback_method_impl{FNCPUMWRMSR} */ 518 static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )519 static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 519 520 { 520 521 if (X86_IS_CANONICAL(uValue)) … … 537 538 538 539 /** @callback_method_impl{FNCPUMWRMSR} */ 539 static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )540 static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 540 541 { 541 542 if (X86_IS_CANONICAL(uValue)) … … 553 554 { 554 555 #if 0 /** @todo implement machine checks. */ 555 *puValue = pRange->u InitOrReadValue & (RT_BIT_64(8) | 0);556 *puValue = pRange->uValue & (RT_BIT_64(8) | 0); 556 557 #else 557 558 *puValue = 0; … … 571 572 572 573 /** @callback_method_impl{FNCPUMWRMSR} */ 573 static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )574 static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 574 575 { 575 576 /** @todo implement machine checks. */ … … 588 589 589 590 /** @callback_method_impl{FNCPUMWRMSR} */ 590 static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )591 static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 591 592 { 592 593 /** @todo implement machine checks. */ … … 605 606 606 607 /** @callback_method_impl{FNCPUMWRMSR} */ 607 static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )608 static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 608 609 { 609 610 /** @todo implement IA32_DEBUGCTL. */ … … 622 623 623 624 /** @callback_method_impl{FNCPUMWRMSR} */ 624 static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )625 static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 625 626 { 626 627 /** @todo implement intel SMM. */ … … 639 640 640 641 /** @callback_method_impl{FNCPUMWRMSR} */ 641 static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )642 static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 642 643 { 643 644 /** @todo implement intel SMM. */ … … 656 657 657 658 /** @callback_method_impl{FNCPUMWRMSR} */ 658 static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )659 static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 659 660 { 660 661 /** @todo implement intel direct cache access (DCA)?? */ … … 682 683 683 684 /** @callback_method_impl{FNCPUMWRMSR} */ 684 static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )685 static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 685 686 { 686 687 /** @todo implement intel direct cache access (DCA)?? */ … … 699 700 700 701 /** @callback_method_impl{FNCPUMWRMSR} */ 701 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )702 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 702 703 { 703 704 /** @todo implement IA32_PERFEVTSEL0+. */ … … 710 711 { 711 712 /** @todo implement IA32_PERFSTATUS. */ 712 *puValue = pRange->u InitOrReadValue;713 return VINF_SUCCESS; 714 } 715 716 717 /** @callback_method_impl{FNCPUMWRMSR} */ 718 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )713 *puValue = pRange->uValue; 714 return VINF_SUCCESS; 715 } 716 717 718 /** @callback_method_impl{FNCPUMWRMSR} */ 719 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 719 720 { 720 721 /* Pentium4 allows writing, but all bits are ignored. */ … … 733 734 734 735 /** @callback_method_impl{FNCPUMWRMSR} */ 735 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )736 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 736 737 { 737 738 /** @todo implement IA32_PERFCTL. */ … … 750 751 751 752 /** @callback_method_impl{FNCPUMWRMSR} */ 752 static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )753 static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 753 754 { 754 755 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */ … … 767 768 768 769 /** @callback_method_impl{FNCPUMWRMSR} */ 769 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )770 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 770 771 { 771 772 /** @todo implement performance counters. */ … … 784 785 785 786 /** @callback_method_impl{FNCPUMWRMSR} */ 786 static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )787 static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 787 788 { 788 789 /** @todo implement performance counters. */ … … 801 802 802 803 /** @callback_method_impl{FNCPUMWRMSR} */ 803 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )804 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 804 805 { 805 806 /** @todo implement performance counters. */ … … 818 819 819 820 /** @callback_method_impl{FNCPUMWRMSR} */ 820 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )821 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 821 822 { 822 823 /** @todo implement performance counters. */ … … 835 836 836 837 /** @callback_method_impl{FNCPUMWRMSR} */ 837 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )838 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 838 839 { 839 840 /** @todo implement performance counters. */ … … 852 853 853 854 /** @callback_method_impl{FNCPUMWRMSR} */ 854 static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )855 static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 855 856 { 856 857 /** @todo implement performance counters. */ … … 869 870 870 871 /** @callback_method_impl{FNCPUMWRMSR} */ 871 static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )872 static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 872 873 { 873 874 /** @todo implement IA32_CLOCK_MODULATION. */ … … 886 887 887 888 /** @callback_method_impl{FNCPUMWRMSR} */ 888 static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )889 static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 889 890 { 890 891 /** @todo implement IA32_THERM_STATUS. */ … … 903 904 904 905 /** @callback_method_impl{FNCPUMWRMSR} */ 905 static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )906 static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 906 907 { 907 908 /** @todo implement IA32_THERM_INTERRUPT. */ … … 920 921 921 922 /** @callback_method_impl{FNCPUMWRMSR} */ 922 static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )923 static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 923 924 { 924 925 /** @todo implement IA32_THERM2_CTL. */ … … 936 937 937 938 /** @callback_method_impl{FNCPUMWRMSR} */ 938 static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )939 static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 939 940 { 940 941 #ifdef LOG_ENABLED … … 982 983 983 984 /** @callback_method_impl{FNCPUMWRMSR} */ 984 static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )985 static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 985 986 { 986 987 switch (idMsr & 3) … … 1036 1037 1037 1038 /** @callback_method_impl{FNCPUMWRMSR} */ 1038 static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1039 static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1039 1040 { 1040 1041 /** @todo Implement machine check exception injection. */ … … 1053 1054 1054 1055 /** @callback_method_impl{FNCPUMWRMSR} */ 1055 static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1056 static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1056 1057 { 1057 1058 return VINF_SUCCESS; … … 1069 1070 1070 1071 /** @callback_method_impl{FNCPUMWRMSR} */ 1071 static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1072 static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1072 1073 { 1073 1074 /** @todo implement TSC deadline timer. */ … … 1090 1091 1091 1092 /** @callback_method_impl{FNCPUMWRMSR} */ 1092 static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1093 static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1093 1094 { 1094 1095 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue); … … 1112 1113 1113 1114 /** @callback_method_impl{FNCPUMWRMSR} */ 1114 static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1115 static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1115 1116 { 1116 1117 /** @todo IA32_DEBUG_INTERFACE (no docs) */ … … 1279 1280 1280 1281 /** @callback_method_impl{FNCPUMWRMSR} */ 1281 static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1282 static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1282 1283 { 1283 1284 PVM pVM = pVCpu->CTX_SUFF(pVM); … … 1338 1339 1339 1340 /** @callback_method_impl{FNCPUMWRMSR} */ 1340 static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1341 static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1341 1342 { 1342 1343 pVCpu->cpum.s.Guest.msrSTAR = uValue; … … 1354 1355 1355 1356 /** @callback_method_impl{FNCPUMWRMSR} */ 1356 static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1357 static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1357 1358 { 1358 1359 if (!X86_IS_CANONICAL(uValue)) … … 1375 1376 1376 1377 /** @callback_method_impl{FNCPUMWRMSR} */ 1377 static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1378 static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1378 1379 { 1379 1380 if (!X86_IS_CANONICAL(uValue)) … … 1396 1397 1397 1398 /** @callback_method_impl{FNCPUMWRMSR} */ 1398 static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1399 static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1399 1400 { 1400 1401 pVCpu->cpum.s.Guest.msrSFMASK = uValue; … … 1412 1413 1413 1414 /** @callback_method_impl{FNCPUMWRMSR} */ 1414 static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1415 static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1415 1416 { 1416 1417 pVCpu->cpum.s.Guest.fs.u64Base = uValue; … … 1427 1428 1428 1429 /** @callback_method_impl{FNCPUMWRMSR} */ 1429 static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1430 static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1430 1431 { 1431 1432 pVCpu->cpum.s.Guest.gs.u64Base = uValue; … … 1443 1444 1444 1445 /** @callback_method_impl{FNCPUMWRMSR} */ 1445 static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1446 static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1446 1447 { 1447 1448 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue; … … 1458 1459 1459 1460 /** @callback_method_impl{FNCPUMWRMSR} */ 1460 static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1461 static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1461 1462 { 1462 1463 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue; … … 1475 1476 { 1476 1477 /** @todo recalc clock frequency ratio? */ 1477 *puValue = pRange->u InitOrReadValue;1478 return VINF_SUCCESS; 1479 } 1480 1481 1482 /** @callback_method_impl{FNCPUMWRMSR} */ 1483 static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1478 *puValue = pRange->uValue; 1479 return VINF_SUCCESS; 1480 } 1481 1482 1483 /** @callback_method_impl{FNCPUMWRMSR} */ 1484 static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1484 1485 { 1485 1486 /** @todo Write EBL_CR_POWERON: Remember written bits. */ … … 1492 1493 { 1493 1494 /** @todo P4 hard power on config */ 1494 *puValue = pRange->u InitOrReadValue;1495 return VINF_SUCCESS; 1496 } 1497 1498 1499 /** @callback_method_impl{FNCPUMWRMSR} */ 1500 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1495 *puValue = pRange->uValue; 1496 return VINF_SUCCESS; 1497 } 1498 1499 1500 /** @callback_method_impl{FNCPUMWRMSR} */ 1501 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1501 1502 { 1502 1503 /** @todo P4 hard power on config */ … … 1509 1510 { 1510 1511 /** @todo P4 soft power on config */ 1511 *puValue = pRange->u InitOrReadValue;1512 return VINF_SUCCESS; 1513 } 1514 1515 1516 /** @callback_method_impl{FNCPUMWRMSR} */ 1517 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1512 *puValue = pRange->uValue; 1513 return VINF_SUCCESS; 1514 } 1515 1516 1517 /** @callback_method_impl{FNCPUMWRMSR} */ 1518 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1518 1519 { 1519 1520 /** @todo P4 soft power on config */ … … 1526 1527 { 1527 1528 /** @todo P4 bus frequency config */ 1528 *puValue = pRange->u InitOrReadValue;1529 return VINF_SUCCESS; 1530 } 1531 1532 1533 /** @callback_method_impl{FNCPUMWRMSR} */ 1534 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1529 *puValue = pRange->uValue; 1530 return VINF_SUCCESS; 1531 } 1532 1533 1534 /** @callback_method_impl{FNCPUMWRMSR} */ 1535 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1535 1536 { 1536 1537 /** @todo P4 bus frequency config */ … … 1579 1580 1580 1581 /** @callback_method_impl{FNCPUMWRMSR} */ 1581 static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1582 static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1582 1583 { 1583 1584 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15)) … … 1608 1609 1609 1610 /** @callback_method_impl{FNCPUMWRMSR} */ 1610 static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1611 static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1611 1612 { 1612 1613 /** @todo implement I/O mwait wakeup. */ … … 1625 1626 1626 1627 /** @callback_method_impl{FNCPUMWRMSR} */ 1627 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1628 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1628 1629 { 1629 1630 /** @todo implement last branch records. */ … … 1642 1643 1643 1644 /** @callback_method_impl{FNCPUMWRMSR} */ 1644 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1645 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1645 1646 { 1646 1647 /** @todo implement last branch records. */ … … 1667 1668 1668 1669 /** @callback_method_impl{FNCPUMWRMSR} */ 1669 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1670 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1670 1671 { 1671 1672 /** @todo implement last branch records. */ … … 1692 1693 1693 1694 /** @callback_method_impl{FNCPUMWRMSR} */ 1694 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1695 static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1695 1696 { 1696 1697 /** @todo implement last branch records. */ … … 1702 1703 static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1703 1704 { 1704 *puValue = pRange->u InitOrReadValue;1705 return VINF_SUCCESS; 1706 } 1707 1708 1709 /** @callback_method_impl{FNCPUMWRMSR} */ 1710 static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1705 *puValue = pRange->uValue; 1706 return VINF_SUCCESS; 1707 } 1708 1709 1710 /** @callback_method_impl{FNCPUMWRMSR} */ 1711 static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1711 1712 { 1712 1713 return VINF_SUCCESS; … … 1717 1718 static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1718 1719 { 1719 *puValue = pRange->u InitOrReadValue;1720 return VINF_SUCCESS; 1721 } 1722 1723 1724 /** @callback_method_impl{FNCPUMWRMSR} */ 1725 static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1720 *puValue = pRange->uValue; 1721 return VINF_SUCCESS; 1722 } 1723 1724 1725 /** @callback_method_impl{FNCPUMWRMSR} */ 1726 static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1726 1727 { 1727 1728 return VINF_SUCCESS; … … 1732 1733 static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1733 1734 { 1734 *puValue = pRange->u InitOrReadValue;1735 return VINF_SUCCESS; 1736 } 1737 1738 1739 /** @callback_method_impl{FNCPUMWRMSR} */ 1740 static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1735 *puValue = pRange->uValue; 1736 return VINF_SUCCESS; 1737 } 1738 1739 1740 /** @callback_method_impl{FNCPUMWRMSR} */ 1741 static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1741 1742 { 1742 1743 return VINF_SUCCESS; … … 1748 1749 { 1749 1750 /** @todo machine check. */ 1750 *puValue = pRange->u InitOrReadValue;1751 return VINF_SUCCESS; 1752 } 1753 1754 1755 /** @callback_method_impl{FNCPUMWRMSR} */ 1756 static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1751 *puValue = pRange->uValue; 1752 return VINF_SUCCESS; 1753 } 1754 1755 1756 /** @callback_method_impl{FNCPUMWRMSR} */ 1757 static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1757 1758 { 1758 1759 /** @todo machine check. */ … … 1770 1771 1771 1772 /** @callback_method_impl{FNCPUMWRMSR} */ 1772 static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1773 static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1773 1774 { 1774 1775 return VINF_SUCCESS; … … 1779 1780 static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1780 1781 { 1781 int rc = CPUMGetGuestCRx(pVCpu, pRange->u InitOrReadValue, puValue);1782 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue); 1782 1783 AssertRC(rc); 1783 1784 return VINF_SUCCESS; … … 1786 1787 1787 1788 /** @callback_method_impl{FNCPUMWRMSR} */ 1788 static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1789 static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1789 1790 { 1790 1791 /* This CRx interface differs from the MOV CRx, GReg interface in that … … 1807 1808 1808 1809 /** @callback_method_impl{FNCPUMWRMSR} */ 1809 static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1810 static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1810 1811 { 1811 1812 /** @todo implement CPUID masking. */ … … 1823 1824 1824 1825 /** @callback_method_impl{FNCPUMWRMSR} */ 1825 static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1826 static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1826 1827 { 1827 1828 /** @todo implement CPUID masking. */ … … 1841 1842 1842 1843 /** @callback_method_impl{FNCPUMWRMSR} */ 1843 static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1844 static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1844 1845 { 1845 1846 /** @todo implement CPUID masking. */ … … 1859 1860 1860 1861 /** @callback_method_impl{FNCPUMWRMSR} */ 1861 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1862 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1862 1863 { 1863 1864 /** @todo implement AES-NI. */ … … 1870 1871 { 1871 1872 /** @todo implement intel C states. */ 1872 *puValue = pRange->u InitOrReadValue;1873 return VINF_SUCCESS; 1874 } 1875 1876 1877 /** @callback_method_impl{FNCPUMWRMSR} */ 1878 static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1873 *puValue = pRange->uValue; 1874 return VINF_SUCCESS; 1875 } 1876 1877 1878 /** @callback_method_impl{FNCPUMWRMSR} */ 1879 static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1879 1880 { 1880 1881 /** @todo implement intel C states. */ … … 1893 1894 1894 1895 /** @callback_method_impl{FNCPUMWRMSR} */ 1895 static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1896 static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1896 1897 { 1897 1898 /** @todo implement last-branch-records. */ … … 1910 1911 1911 1912 /** @callback_method_impl{FNCPUMWRMSR} */ 1912 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1913 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1913 1914 { 1914 1915 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */ … … 1921 1922 { 1922 1923 /** @todo implement memory VLW? */ 1923 *puValue = pRange->u InitOrReadValue;1924 *puValue = pRange->uValue; 1924 1925 /* Note: A20M is known to be bit 1 as this was disclosed in spec update 1925 1926 AAJ49/AAK51/????, which documents the inversion of this bit. The … … 1944 1945 1945 1946 /** @callback_method_impl{FNCPUMWRMSR} */ 1946 static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1947 static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1947 1948 { 1948 1949 /** @todo intel power management */ … … 1961 1962 1962 1963 /** @callback_method_impl{FNCPUMWRMSR} */ 1963 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1964 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1964 1965 { 1965 1966 /** @todo intel performance counters. */ … … 1978 1979 1979 1980 /** @callback_method_impl{FNCPUMWRMSR} */ 1980 static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )1981 static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1981 1982 { 1982 1983 /** @todo intel performance counters. */ … … 2013 2014 2014 2015 /** @callback_method_impl{FNCPUMWRMSR} */ 2015 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2016 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2016 2017 { 2017 2018 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */ … … 2030 2031 2031 2032 /** @callback_method_impl{FNCPUMWRMSR} */ 2032 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2033 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2033 2034 { 2034 2035 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */ … … 2041 2042 { 2042 2043 /** @todo intel RAPL. */ 2043 *puValue = pRange->u InitOrReadValue;2044 *puValue = pRange->uValue; 2044 2045 return VINF_SUCCESS; 2045 2046 } … … 2056 2057 2057 2058 /** @callback_method_impl{FNCPUMWRMSR} */ 2058 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2059 static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2059 2060 { 2060 2061 /** @todo intel power management. */ … … 2082 2083 2083 2084 /** @callback_method_impl{FNCPUMWRMSR} */ 2084 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2085 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2085 2086 { 2086 2087 /** @todo intel RAPL. */ … … 2126 2127 2127 2128 /** @callback_method_impl{FNCPUMWRMSR} */ 2128 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2129 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2129 2130 { 2130 2131 /** @todo intel RAPL. */ … … 2170 2171 2171 2172 /** @callback_method_impl{FNCPUMWRMSR} */ 2172 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2173 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2173 2174 { 2174 2175 /** @todo intel RAPL. */ … … 2196 2197 2197 2198 /** @callback_method_impl{FNCPUMWRMSR} */ 2198 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2199 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2199 2200 { 2200 2201 /** @todo intel RAPL. */ … … 2222 2223 2223 2224 /** @callback_method_impl{FNCPUMWRMSR} */ 2224 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2225 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2225 2226 { 2226 2227 /** @todo intel RAPL. */ … … 2248 2249 2249 2250 /** @callback_method_impl{FNCPUMWRMSR} */ 2250 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2251 static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2251 2252 { 2252 2253 /** @todo intel RAPL. */ … … 2259 2260 { 2260 2261 /** @todo intel power management. */ 2261 *puValue = pRange->u InitOrReadValue;2262 *puValue = pRange->uValue; 2262 2263 return VINF_SUCCESS; 2263 2264 } … … 2268 2269 { 2269 2270 /** @todo intel power management. */ 2270 *puValue = pRange->u InitOrReadValue;2271 *puValue = pRange->uValue; 2271 2272 return VINF_SUCCESS; 2272 2273 } … … 2277 2278 { 2278 2279 /** @todo intel power management. */ 2279 *puValue = pRange->u InitOrReadValue;2280 *puValue = pRange->uValue; 2280 2281 return VINF_SUCCESS; 2281 2282 } … … 2292 2293 2293 2294 /** @callback_method_impl{FNCPUMWRMSR} */ 2294 static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2295 static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2295 2296 { 2296 2297 /** @todo intel power management. */ … … 2309 2310 2310 2311 /** @callback_method_impl{FNCPUMWRMSR} */ 2311 static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2312 static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2312 2313 { 2313 2314 /** @todo intel power management. */ … … 2326 2327 2327 2328 /** @callback_method_impl{FNCPUMWRMSR} */ 2328 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2329 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2329 2330 { 2330 2331 /** @todo uncore msrs. */ … … 2343 2344 2344 2345 /** @callback_method_impl{FNCPUMWRMSR} */ 2345 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2346 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2346 2347 { 2347 2348 /** @todo uncore msrs. */ … … 2360 2361 2361 2362 /** @callback_method_impl{FNCPUMWRMSR} */ 2362 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2363 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2363 2364 { 2364 2365 /** @todo uncore msrs. */ … … 2377 2378 2378 2379 /** @callback_method_impl{FNCPUMWRMSR} */ 2379 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2380 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2380 2381 { 2381 2382 /** @todo uncore msrs. */ … … 2394 2395 2395 2396 /** @callback_method_impl{FNCPUMWRMSR} */ 2396 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2397 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2397 2398 { 2398 2399 /** @todo uncore msrs. */ … … 2420 2421 2421 2422 /** @callback_method_impl{FNCPUMWRMSR} */ 2422 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2423 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2423 2424 { 2424 2425 /** @todo uncore msrs. */ … … 2437 2438 2438 2439 /** @callback_method_impl{FNCPUMWRMSR} */ 2439 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2440 static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2440 2441 { 2441 2442 /** @todo uncore msrs. */ … … 2448 2449 { 2449 2450 /** @todo implement enhanced multi thread termal monitoring? */ 2450 *puValue = pRange->u InitOrReadValue;2451 return VINF_SUCCESS; 2452 } 2453 2454 2455 /** @callback_method_impl{FNCPUMWRMSR} */ 2456 static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2451 *puValue = pRange->uValue; 2452 return VINF_SUCCESS; 2453 } 2454 2455 2456 /** @callback_method_impl{FNCPUMWRMSR} */ 2457 static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2457 2458 { 2458 2459 /** @todo implement enhanced multi thread termal monitoring? */ … … 2471 2472 2472 2473 /** @callback_method_impl{FNCPUMWRMSR} */ 2473 static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2474 static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2474 2475 { 2475 2476 /** @todo SMM & C-states? */ … … 2488 2489 2489 2490 /** @callback_method_impl{FNCPUMWRMSR} */ 2490 static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2491 static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2491 2492 { 2492 2493 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */ … … 2505 2506 2506 2507 /** @callback_method_impl{FNCPUMWRMSR} */ 2507 static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2508 static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2508 2509 { 2509 2510 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */ … … 2522 2523 2523 2524 /** @callback_method_impl{FNCPUMWRMSR} */ 2524 static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2525 static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2525 2526 { 2526 2527 /** @todo Core2+ platform environment control interface control register? */ … … 2570 2571 2571 2572 /** @callback_method_impl{FNCPUMWRMSR} */ 2572 static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2573 static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2573 2574 { 2574 2575 /** @todo implement last exception records. */ … … 2587 2588 2588 2589 /** @callback_method_impl{FNCPUMWRMSR} */ 2589 static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2590 static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2590 2591 { 2591 2592 /** @todo implement last exception records. */ … … 2612 2613 2613 2614 /** @callback_method_impl{FNCPUMWRMSR} */ 2614 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2615 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2615 2616 { 2616 2617 /** @todo Implement TscRateMsr */ … … 2630 2631 2631 2632 /** @callback_method_impl{FNCPUMWRMSR} */ 2632 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2633 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2633 2634 { 2634 2635 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */ … … 2648 2649 2649 2650 /** @callback_method_impl{FNCPUMWRMSR} */ 2650 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2651 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2651 2652 { 2652 2653 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */ … … 2665 2666 2666 2667 /** @callback_method_impl{FNCPUMWRMSR} */ 2667 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2668 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2668 2669 { 2669 2670 /** @todo machine check. */ … … 2682 2683 2683 2684 /** @callback_method_impl{FNCPUMWRMSR} */ 2684 static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2685 static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2685 2686 { 2686 2687 /** @todo AMD performance events. */ … … 2699 2700 2700 2701 /** @callback_method_impl{FNCPUMWRMSR} */ 2701 static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2702 static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2702 2703 { 2703 2704 /** @todo AMD performance events. */ … … 2710 2711 { 2711 2712 /** @todo AMD SYS_CFG */ 2712 *puValue = pRange->u InitOrReadValue;2713 return VINF_SUCCESS; 2714 } 2715 2716 2717 /** @callback_method_impl{FNCPUMWRMSR} */ 2718 static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2713 *puValue = pRange->uValue; 2714 return VINF_SUCCESS; 2715 } 2716 2717 2718 /** @callback_method_impl{FNCPUMWRMSR} */ 2719 static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2719 2720 { 2720 2721 /** @todo AMD SYS_CFG */ … … 2733 2734 2734 2735 /** @callback_method_impl{FNCPUMWRMSR} */ 2735 static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2736 static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2736 2737 { 2737 2738 /** @todo AMD HW_CFG */ … … 2750 2751 2751 2752 /** @callback_method_impl{FNCPUMWRMSR} */ 2752 static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2753 static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2753 2754 { 2754 2755 /** @todo AMD IorrMask/IorrBase */ … … 2767 2768 2768 2769 /** @callback_method_impl{FNCPUMWRMSR} */ 2769 static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2770 static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2770 2771 { 2771 2772 /** @todo AMD IorrMask/IorrBase */ … … 2780 2781 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return 2781 2782 * for TOPMEM2. */ 2782 //if (pRange->u InitOrReadValue == 0)2783 //if (pRange->uValue == 0) 2783 2784 // *puValue = _4G - RamHoleSize; 2784 2785 return VINF_SUCCESS; … … 2787 2788 2788 2789 /** @callback_method_impl{FNCPUMWRMSR} */ 2789 static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2790 static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2790 2791 { 2791 2792 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */ … … 2804 2805 2805 2806 /** @callback_method_impl{FNCPUMWRMSR} */ 2806 static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2807 static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2807 2808 { 2808 2809 /** @todo AMD NB_CFG1 */ … … 2821 2822 2822 2823 /** @callback_method_impl{FNCPUMWRMSR} */ 2823 static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2824 static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2824 2825 { 2825 2826 /** @todo machine check. */ … … 2831 2832 static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2832 2833 { 2833 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->u InitOrReadValue / 2 + 0x80000001, 0);2834 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0); 2834 2835 if (pLeaf) 2835 2836 { 2836 if (!(pRange->u InitOrReadValue & 1))2837 if (!(pRange->uValue & 1)) 2837 2838 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx); 2838 2839 else … … 2846 2847 2847 2848 /** @callback_method_impl{FNCPUMWRMSR} */ 2848 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2849 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2849 2850 { 2850 2851 /** @todo Remember guest programmed CPU name. */ … … 2857 2858 { 2858 2859 /** @todo AMD HTC. */ 2859 *puValue = pRange->u InitOrReadValue;2860 return VINF_SUCCESS; 2861 } 2862 2863 2864 /** @callback_method_impl{FNCPUMWRMSR} */ 2865 static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2860 *puValue = pRange->uValue; 2861 return VINF_SUCCESS; 2862 } 2863 2864 2865 /** @callback_method_impl{FNCPUMWRMSR} */ 2866 static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2866 2867 { 2867 2868 /** @todo AMD HTC. */ … … 2880 2881 2881 2882 /** @callback_method_impl{FNCPUMWRMSR} */ 2882 static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2883 static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2883 2884 { 2884 2885 /** @todo AMD STC. */ … … 2891 2892 { 2892 2893 /** @todo AMD FIDVID_CTL. */ 2893 *puValue = pRange->u InitOrReadValue;2894 return VINF_SUCCESS; 2895 } 2896 2897 2898 /** @callback_method_impl{FNCPUMWRMSR} */ 2899 static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2894 *puValue = pRange->uValue; 2895 return VINF_SUCCESS; 2896 } 2897 2898 2899 /** @callback_method_impl{FNCPUMWRMSR} */ 2900 static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2900 2901 { 2901 2902 /** @todo AMD FIDVID_CTL. */ … … 2908 2909 { 2909 2910 /** @todo AMD FIDVID_STATUS. */ 2910 *puValue = pRange->u InitOrReadValue;2911 *puValue = pRange->uValue; 2911 2912 return VINF_SUCCESS; 2912 2913 } … … 2923 2924 2924 2925 /** @callback_method_impl{FNCPUMWRMSR} */ 2925 static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2926 static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2926 2927 { 2927 2928 /** @todo AMD MC. */ … … 2940 2941 2941 2942 /** @callback_method_impl{FNCPUMWRMSR} */ 2942 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2943 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2943 2944 { 2944 2945 /** @todo AMD SMM/SMI and I/O trap. */ … … 2957 2958 2958 2959 /** @callback_method_impl{FNCPUMWRMSR} */ 2959 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2960 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2960 2961 { 2961 2962 /** @todo AMD SMM/SMI and I/O trap. */ … … 2974 2975 2975 2976 /** @callback_method_impl{FNCPUMWRMSR} */ 2976 static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2977 static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2977 2978 { 2978 2979 /** @todo Interrupt pending message. */ … … 2991 2992 2992 2993 /** @callback_method_impl{FNCPUMWRMSR} */ 2993 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )2994 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2994 2995 { 2995 2996 /** @todo AMD SMM/SMI and trigger I/O cycle. */ … … 3008 3009 3009 3010 /** @callback_method_impl{FNCPUMWRMSR} */ 3010 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3011 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3011 3012 { 3012 3013 /** @todo AMD MMIO Configuration base address. */ … … 3025 3026 3026 3027 /** @callback_method_impl{FNCPUMWRMSR} */ 3027 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3028 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3028 3029 { 3029 3030 /** @todo AMD 0xc0010059. */ … … 3036 3037 { 3037 3038 /** @todo AMD P-states. */ 3038 *puValue = pRange->u InitOrReadValue;3039 *puValue = pRange->uValue; 3039 3040 return VINF_SUCCESS; 3040 3041 } … … 3045 3046 { 3046 3047 /** @todo AMD P-states. */ 3047 *puValue = pRange->u InitOrReadValue;3048 return VINF_SUCCESS; 3049 } 3050 3051 3052 /** @callback_method_impl{FNCPUMWRMSR} */ 3053 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3048 *puValue = pRange->uValue; 3049 return VINF_SUCCESS; 3050 } 3051 3052 3053 /** @callback_method_impl{FNCPUMWRMSR} */ 3054 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3054 3055 { 3055 3056 /** @todo AMD P-states. */ … … 3062 3063 { 3063 3064 /** @todo AMD P-states. */ 3064 *puValue = pRange->u InitOrReadValue;3065 return VINF_SUCCESS; 3066 } 3067 3068 3069 /** @callback_method_impl{FNCPUMWRMSR} */ 3070 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3065 *puValue = pRange->uValue; 3066 return VINF_SUCCESS; 3067 } 3068 3069 3070 /** @callback_method_impl{FNCPUMWRMSR} */ 3071 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3071 3072 { 3072 3073 /** @todo AMD P-states. */ … … 3079 3080 { 3080 3081 /** @todo AMD P-states. */ 3081 *puValue = pRange->u InitOrReadValue;3082 return VINF_SUCCESS; 3083 } 3084 3085 3086 /** @callback_method_impl{FNCPUMWRMSR} */ 3087 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3082 *puValue = pRange->uValue; 3083 return VINF_SUCCESS; 3084 } 3085 3086 3087 /** @callback_method_impl{FNCPUMWRMSR} */ 3088 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3088 3089 { 3089 3090 /** @todo AMD P-states. */ … … 3096 3097 { 3097 3098 /** @todo AMD P-states. */ 3098 *puValue = pRange->u InitOrReadValue;3099 return VINF_SUCCESS; 3100 } 3101 3102 3103 /** @callback_method_impl{FNCPUMWRMSR} */ 3104 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3099 *puValue = pRange->uValue; 3100 return VINF_SUCCESS; 3101 } 3102 3103 3104 /** @callback_method_impl{FNCPUMWRMSR} */ 3105 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3105 3106 { 3106 3107 /** @todo AMD P-states. */ … … 3113 3114 { 3114 3115 /** @todo AMD P-states. */ 3115 *puValue = pRange->u InitOrReadValue;3116 return VINF_SUCCESS; 3117 } 3118 3119 3120 /** @callback_method_impl{FNCPUMWRMSR} */ 3121 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3116 *puValue = pRange->uValue; 3117 return VINF_SUCCESS; 3118 } 3119 3120 3121 /** @callback_method_impl{FNCPUMWRMSR} */ 3122 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3122 3123 { 3123 3124 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */ … … 3137 3138 3138 3139 /** @callback_method_impl{FNCPUMWRMSR} */ 3139 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3140 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3140 3141 { 3141 3142 /** @todo AMD C-states. */ … … 3154 3155 3155 3156 /** @callback_method_impl{FNCPUMWRMSR} */ 3156 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3157 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3157 3158 { 3158 3159 /** @todo AMD machine checks. */ … … 3171 3172 3172 3173 /** @callback_method_impl{FNCPUMWRMSR} */ 3173 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3174 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3174 3175 { 3175 3176 /** @todo AMD SMM. */ … … 3188 3189 3189 3190 /** @callback_method_impl{FNCPUMWRMSR} */ 3190 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3191 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3191 3192 { 3192 3193 /** @todo AMD SMM. */ … … 3206 3207 3207 3208 /** @callback_method_impl{FNCPUMWRMSR} */ 3208 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3209 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3209 3210 { 3210 3211 /** @todo AMD SMM. */ … … 3223 3224 3224 3225 /** @callback_method_impl{FNCPUMWRMSR} */ 3225 static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3226 static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3226 3227 { 3227 3228 /** @todo AMD SVM. */ … … 3240 3241 3241 3242 /** @callback_method_impl{FNCPUMWRMSR} */ 3242 static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3243 static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3243 3244 { 3244 3245 /** @todo AMD IGNNE\# control. */ … … 3257 3258 3258 3259 /** @callback_method_impl{FNCPUMWRMSR} */ 3259 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3260 static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3260 3261 { 3261 3262 /** @todo AMD SMM. */ … … 3274 3275 3275 3276 /** @callback_method_impl{FNCPUMWRMSR} */ 3276 static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3277 static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3277 3278 { 3278 3279 /** @todo AMD SVM. */ … … 3291 3292 3292 3293 /** @callback_method_impl{FNCPUMWRMSR} */ 3293 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3294 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3294 3295 { 3295 3296 /** @todo AMD SVM. */ … … 3308 3309 3309 3310 /** @callback_method_impl{FNCPUMWRMSR} */ 3310 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3311 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3311 3312 { 3312 3313 /** @todo AMD SMM. */ … … 3325 3326 3326 3327 /** @callback_method_impl{FNCPUMWRMSR} */ 3327 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3328 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3328 3329 { 3329 3330 /** @todo AMD SMM/SMI. */ … … 3336 3337 { 3337 3338 /** @todo AMD OS visible workaround. */ 3338 *puValue = pRange->u InitOrReadValue;3339 return VINF_SUCCESS; 3340 } 3341 3342 3343 /** @callback_method_impl{FNCPUMWRMSR} */ 3344 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3339 *puValue = pRange->uValue; 3340 return VINF_SUCCESS; 3341 } 3342 3343 3344 /** @callback_method_impl{FNCPUMWRMSR} */ 3345 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3345 3346 { 3346 3347 /** @todo AMD OS visible workaround. */ … … 3359 3360 3360 3361 /** @callback_method_impl{FNCPUMWRMSR} */ 3361 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3362 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3362 3363 { 3363 3364 /** @todo AMD OS visible workaround. */ … … 3376 3377 3377 3378 /** @callback_method_impl{FNCPUMWRMSR} */ 3378 static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3379 static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3379 3380 { 3380 3381 /** @todo AMD L2I performance counters. */ … … 3393 3394 3394 3395 /** @callback_method_impl{FNCPUMWRMSR} */ 3395 static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3396 static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3396 3397 { 3397 3398 /** @todo AMD L2I performance counters. */ … … 3410 3411 3411 3412 /** @callback_method_impl{FNCPUMWRMSR} */ 3412 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3413 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3413 3414 { 3414 3415 /** @todo AMD Northbridge performance counters. */ … … 3427 3428 3428 3429 /** @callback_method_impl{FNCPUMWRMSR} */ 3429 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3430 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3430 3431 { 3431 3432 /** @todo AMD Northbridge performance counters. */ … … 3440 3441 * cpus. Need to be explored and verify K7 presence. */ 3441 3442 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */ 3442 *puValue = pRange->u InitOrReadValue;3443 return VINF_SUCCESS; 3444 } 3445 3446 3447 /** @callback_method_impl{FNCPUMWRMSR} */ 3448 static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3443 *puValue = pRange->uValue; 3444 return VINF_SUCCESS; 3445 } 3446 3447 3448 /** @callback_method_impl{FNCPUMWRMSR} */ 3449 static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3449 3450 { 3450 3451 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3462 3463 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when 3463 3464 * describing EBL_CR_POWERON. */ 3464 *puValue = pRange->u InitOrReadValue;3465 return VINF_SUCCESS; 3466 } 3467 3468 3469 /** @callback_method_impl{FNCPUMWRMSR} */ 3470 static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3465 *puValue = pRange->uValue; 3466 return VINF_SUCCESS; 3467 } 3468 3469 3470 /** @callback_method_impl{FNCPUMWRMSR} */ 3471 static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3471 3472 { 3472 3473 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3491 3492 3492 3493 /** @callback_method_impl{FNCPUMWRMSR} */ 3493 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3494 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3494 3495 { 3495 3496 /** @todo Changing CPUID leaf 7/0. */ … … 3511 3512 3512 3513 /** @callback_method_impl{FNCPUMWRMSR} */ 3513 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3514 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3514 3515 { 3515 3516 /** @todo Changing CPUID leaf 6. */ … … 3531 3532 3532 3533 /** @callback_method_impl{FNCPUMWRMSR} */ 3533 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3534 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3534 3535 { 3535 3536 /** @todo Changing CPUID leaf 0x80000001. */ … … 3551 3552 3552 3553 /** @callback_method_impl{FNCPUMWRMSR} */ 3553 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3554 static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3554 3555 { 3555 3556 /** @todo Changing CPUID leaf 0x80000001. */ … … 3562 3563 { 3563 3564 /** @todo Fake AMD microcode patching. */ 3564 *puValue = pRange->u InitOrReadValue;3565 return VINF_SUCCESS; 3566 } 3567 3568 3569 /** @callback_method_impl{FNCPUMWRMSR} */ 3570 static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3565 *puValue = pRange->uValue; 3566 return VINF_SUCCESS; 3567 } 3568 3569 3570 /** @callback_method_impl{FNCPUMWRMSR} */ 3571 static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3571 3572 { 3572 3573 /** @todo Fake AMD microcode patching. */ … … 3587 3588 3588 3589 /** @callback_method_impl{FNCPUMWRMSR} */ 3589 static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3590 static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3590 3591 { 3591 3592 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3608 3609 3609 3610 /** @callback_method_impl{FNCPUMWRMSR} */ 3610 static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3611 static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3611 3612 { 3612 3613 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3629 3630 3630 3631 /** @callback_method_impl{FNCPUMWRMSR} */ 3631 static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3632 static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3632 3633 { 3633 3634 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3650 3651 3651 3652 /** @callback_method_impl{FNCPUMWRMSR} */ 3652 static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3653 static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3653 3654 { 3654 3655 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3671 3672 3672 3673 /** @callback_method_impl{FNCPUMWRMSR} */ 3673 static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3674 static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3674 3675 { 3675 3676 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3692 3693 3693 3694 /** @callback_method_impl{FNCPUMWRMSR} */ 3694 static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3695 static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3695 3696 { 3696 3697 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3713 3714 3714 3715 /** @callback_method_impl{FNCPUMWRMSR} */ 3715 static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3716 static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3716 3717 { 3717 3718 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3734 3735 3735 3736 /** @callback_method_impl{FNCPUMWRMSR} */ 3736 static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3737 static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3737 3738 { 3738 3739 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3755 3756 3756 3757 /** @callback_method_impl{FNCPUMWRMSR} */ 3757 static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3758 static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3758 3759 { 3759 3760 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3776 3777 3777 3778 /** @callback_method_impl{FNCPUMWRMSR} */ 3778 static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3779 static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3779 3780 { 3780 3781 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3797 3798 3798 3799 /** @callback_method_impl{FNCPUMWRMSR} */ 3799 static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3800 static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3800 3801 { 3801 3802 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3818 3819 3819 3820 /** @callback_method_impl{FNCPUMWRMSR} */ 3820 static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3821 static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3821 3822 { 3822 3823 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3839 3840 3840 3841 /** @callback_method_impl{FNCPUMWRMSR} */ 3841 static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3842 static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3842 3843 { 3843 3844 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3860 3861 3861 3862 /** @callback_method_impl{FNCPUMWRMSR} */ 3862 static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3863 static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3863 3864 { 3864 3865 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3881 3882 3882 3883 /** @callback_method_impl{FNCPUMWRMSR} */ 3883 static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3884 static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3884 3885 { 3885 3886 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3900 3901 3901 3902 /** @callback_method_impl{FNCPUMWRMSR} */ 3902 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3903 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3903 3904 { 3904 3905 /** @todo AMD FPU config. */ … … 3917 3918 3918 3919 /** @callback_method_impl{FNCPUMWRMSR} */ 3919 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3920 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3920 3921 { 3921 3922 /** @todo AMD decoder config. */ … … 3935 3936 3936 3937 /** @callback_method_impl{FNCPUMWRMSR} */ 3937 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3938 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3938 3939 { 3939 3940 /* Note! 10h and 16h */ … … 3953 3954 3954 3955 /** @callback_method_impl{FNCPUMWRMSR} */ 3955 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3956 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3956 3957 { 3957 3958 /** @todo AMD unit config. */ … … 3970 3971 3971 3972 /** @callback_method_impl{FNCPUMWRMSR} */ 3972 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3973 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3973 3974 { 3974 3975 /** @todo AMD unit config 2. */ … … 3987 3988 3988 3989 /** @callback_method_impl{FNCPUMWRMSR} */ 3989 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )3990 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3990 3991 { 3991 3992 /** @todo AMD combined unit config 3. */ … … 4004 4005 4005 4006 /** @callback_method_impl{FNCPUMWRMSR} */ 4006 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4007 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4007 4008 { 4008 4009 /** @todo AMD execution unit config. */ … … 4021 4022 4022 4023 /** @callback_method_impl{FNCPUMWRMSR} */ 4023 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4024 static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4024 4025 { 4025 4026 /** @todo AMD load-store config 2. */ … … 4038 4039 4039 4040 /** @callback_method_impl{FNCPUMWRMSR} */ 4040 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4041 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4041 4042 { 4042 4043 /** @todo AMD IBS. */ … … 4055 4056 4056 4057 /** @callback_method_impl{FNCPUMWRMSR} */ 4057 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4058 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4058 4059 { 4059 4060 /** @todo AMD IBS. */ … … 4072 4073 4073 4074 /** @callback_method_impl{FNCPUMWRMSR} */ 4074 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4075 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4075 4076 { 4076 4077 /** @todo AMD IBS. */ … … 4089 4090 4090 4091 /** @callback_method_impl{FNCPUMWRMSR} */ 4091 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4092 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4092 4093 { 4093 4094 /** @todo AMD IBS. */ … … 4106 4107 4107 4108 /** @callback_method_impl{FNCPUMWRMSR} */ 4108 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4109 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4109 4110 { 4110 4111 /** @todo AMD IBS. */ … … 4128 4129 4129 4130 /** @callback_method_impl{FNCPUMWRMSR} */ 4130 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4131 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4131 4132 { 4132 4133 /** @todo AMD IBS. */ … … 4145 4146 4146 4147 /** @callback_method_impl{FNCPUMWRMSR} */ 4147 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4148 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4148 4149 { 4149 4150 /** @todo AMD IBS. */ … … 4162 4163 4163 4164 /** @callback_method_impl{FNCPUMWRMSR} */ 4164 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4165 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4165 4166 { 4166 4167 /** @todo AMD IBS. */ … … 4179 4180 4180 4181 /** @callback_method_impl{FNCPUMWRMSR} */ 4181 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4182 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4182 4183 { 4183 4184 /** @todo AMD IBS. */ … … 4201 4202 4202 4203 /** @callback_method_impl{FNCPUMWRMSR} */ 4203 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4204 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4204 4205 { 4205 4206 /** @todo AMD IBS. */ … … 4218 4219 4219 4220 /** @callback_method_impl{FNCPUMWRMSR} */ 4220 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4221 static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4221 4222 { 4222 4223 /** @todo AMD IBS. */ … … 4235 4236 4236 4237 /** @callback_method_impl{FNCPUMWRMSR} */ 4237 static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue )4238 static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4238 4239 { 4239 4240 /** @todo AMD IBS. */ … … 4859 4860 } 4860 4861 4861 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted );4862 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue); 4862 4863 if (RT_SUCCESS(rc)) 4863 4864 { -
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r49893 r49972 2265 2265 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001), 0); 2266 2266 if (pLeaf) 2267 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;2267 pVM->cpum.s.aGuestCpuIdStd[1].ecx = pLeaf->uEcx |= X86_CPUID_FEATURE_ECX_HVP; 2268 2268 pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1; 2269 2269 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n")); -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r49954 r49972 753 753 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite; 754 754 755 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.u InitOrReadValue, 0);755 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0); 756 756 if (RT_FAILURE(rc)) 757 757 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n", -
trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp
r49966 r49972 627 627 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes", 628 628 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM."); 629 STAM_REL_REG(pVM, &pCpum->cMsrWrites ToIgnoredBits,STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",629 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP", 630 630 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs."); 631 STAM_REL_REG(pVM, &pCpum->cMsrWrites RaiseGp,STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",631 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits", 632 632 STAMUNIT_OCCURENCES, "Writing of ignored bits."); 633 633 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown", -
trunk/src/VBox/VMM/VMMR3/cpus/AMD_Athlon_64_3200.h
r49966 r49972 113 113 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, UINT64_C(0xfffffffffffff3f8)), 114 114 RFN(0x00000400, 0x00000413, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN), 115 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0x800, 0xfe, UINT64_C(0xfffffffffffff 600)),115 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0x800, 0xfe, UINT64_C(0xfffffffffffff200)), 116 116 MFN(0xc0000081, "AMD64_STAR", Amd64SyscallTarget, Amd64SyscallTarget), /* value=0x0 */ 117 117 MFN(0xc0000082, "AMD64_STAR64", Amd64LongSyscallTarget, Amd64LongSyscallTarget), /* value=0x0 */ -
trunk/src/VBox/VMM/VMMR3/cpus/AMD_FX_8150_Eight_Core.h
r49922 r49972 137 137 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, UINT64_C(0xfffffffffffff3f8)), 138 138 RFN(0x00000400, 0x0000041b, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN), 139 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0x4d01, 0xfe, UINT64_C(0xffffffffffff8 600)),139 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0x4d01, 0xfe, UINT64_C(0xffffffffffff8200)), 140 140 MFN(0xc0000081, "AMD64_STAR", Amd64SyscallTarget, Amd64SyscallTarget), /* value=0x230010`00000000 */ 141 141 MFN(0xc0000082, "AMD64_STAR64", Amd64LongSyscallTarget, Amd64LongSyscallTarget), /* value=0xfffff800`02ed0bc0 */ -
trunk/src/VBox/VMM/VMMR3/cpus/AMD_Phenom_II_X6_1100T.h
r49952 r49972 122 122 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, UINT64_C(0xfffffffffffff3f8)), 123 123 RFN(0x00000400, 0x00000417, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN), 124 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0xd01, 0xfe, UINT64_C(0xffffffffffff8 600)),124 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0xd01, 0xfe, UINT64_C(0xffffffffffff8200)), 125 125 MFN(0xc0000081, "AMD64_STAR", Amd64SyscallTarget, Amd64SyscallTarget), /* value=0x230010`00000000 */ 126 126 MFN(0xc0000082, "AMD64_STAR64", Amd64LongSyscallTarget, Amd64LongSyscallTarget), /* value=0xffffffff`8174b4f0 */ -
trunk/src/VBox/VMM/VMMR3/cpus/Quad_Core_AMD_Opteron_2384.h
r49922 r49972 119 119 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, UINT64_C(0xfffffffffffff3f8)), 120 120 RFN(0x00000400, 0x00000417, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN), 121 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0x4d01, 0xfe, UINT64_C(0xffffffffffff8 600)),121 MFX(0xc0000080, "AMD64_EFER", Amd64Efer, Amd64Efer, 0x4d01, 0xfe, UINT64_C(0xffffffffffff8200)), 122 122 MFN(0xc0000081, "AMD64_STAR", Amd64SyscallTarget, Amd64SyscallTarget), /* value=0x230010`00000000 */ 123 123 MFN(0xc0000082, "AMD64_STAR64", Amd64LongSyscallTarget, Amd64LongSyscallTarget), /* value=0xfffff800`0245dd00 */ -
trunk/src/VBox/VMM/include/CPUMInternal.h
r49966 r49972 118 118 /** Invalid zero value. */ 119 119 kCpumMsrRdFn_Invalid = 0, 120 /** Return the CPUMMSRRANGE::u InitOrReadValue. */120 /** Return the CPUMMSRRANGE::uValue. */ 121 121 kCpumMsrRdFn_FixedValue, 122 122 /** Alias to the MSR range starting at the MSR given by 123 * CPUMMSRRANGE::u InitOrReadValue. Must be used in pair with123 * CPUMMSRRANGE::uValue. Must be used in pair with 124 124 * kCpumMsrWrFn_MsrAlias. */ 125 125 kCpumMsrRdFn_MsrAlias, … … 388 388 kCpumMsrWrFn_ReadOnly, 389 389 /** Alias to the MSR range starting at the MSR given by 390 * CPUMMSRRANGE::u InitOrReadValue. Must be used in pair with390 * CPUMMSRRANGE::uValue. Must be used in pair with 391 391 * kCpumMsrRdFn_MsrAlias. */ 392 392 kCpumMsrWrFn_MsrAlias, … … 619 619 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid 620 620 * offset into CPUM. */ 621 uint64_t u InitOrReadValue;621 uint64_t uValue; 622 622 /** The bits to ignore when writing. [24] */ 623 623 uint64_t fWrIgnMask; -
trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp
r49966 r49972 2775 2775 2776 2776 2777 /** 2778 * Generic report for an MSR implemented by functions, extended version. 2779 * 2780 * @returns VBox status code. 2781 * @param uMsr The MSR. 2782 * @param pszRdWrFnName The read/write function name, optional. 2783 * @param uValue The MSR range value. 2784 * @param fSkipMask Mask of bits to skip. 2785 * @param fNoGpMask Mask of bits to remove from the GP mask after 2786 * probing 2787 * @param pszAnnotate Annotation. 2788 */ 2777 2789 static int reportMsr_GenFunctionEx(uint32_t uMsr, const char *pszRdWrFnName, uint32_t uValue, 2778 uint64_t fSkipMask, const char *pszAnnotate)2790 uint64_t fSkipMask, uint64_t fNoGpMask, const char *pszAnnotate) 2779 2791 { 2780 2792 /* Resolve default function name. */ … … 2792 2804 if (RT_SUCCESS(rc)) 2793 2805 { 2806 fGpMask &= ~fNoGpMask; 2807 2794 2808 if (fGpMask == UINT64_MAX && uValue == 0 && !msrProberModifyZero(uMsr)) 2795 2809 rc = printMsrFunctionReadOnly(uMsr, pszRdWrFnName, pszAnnotate); … … 2822 2836 if (vbCpuRepSupportsX2Apic()) 2823 2837 fSkipMask |= RT_BIT_64(10); 2824 return reportMsr_GenFunctionEx(uMsr, "Ia32ApicBase", uValue, fSkipMask, NULL);2838 return reportMsr_GenFunctionEx(uMsr, "Ia32ApicBase", uValue, fSkipMask, 0, NULL); 2825 2839 } 2826 2840 … … 3144 3158 } 3145 3159 3146 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, NULL);3160 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, MSR_K6_EFER_LMA, NULL); 3147 3161 } 3148 3162 … … 3322 3336 | RT_BIT(0) /* SysAckLimit */; 3323 3337 3324 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));3338 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue)); 3325 3339 } 3326 3340 … … 3354 3368 fSkipMask |= RT_BIT(0); /* SMMLOCK */ 3355 3369 3356 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));3370 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue)); 3357 3371 } 3358 3372 … … 3370 3384 uint64_t fSkipMask = RT_BIT(4) | RT_BIT(3); 3371 3385 fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK; 3372 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, annotateValue(uValue));3386 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, 0, annotateValue(uValue)); 3373 3387 } 3374 3388 … … 3386 3400 uint64_t fSkipMask = RT_BIT(11); 3387 3401 fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK; 3388 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, annotateValue(uValue));3402 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, 0, annotateValue(uValue)); 3389 3403 } 3390 3404 … … 3401 3415 /* Skip know bits here, as harm seems to come from messing with them. */ 3402 3416 uint64_t fSkipMask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(RT_BIT_64(23) - 1); 3403 return reportMsr_GenFunctionEx(uMsr, NULL, uMsr == 0xc001001d, fSkipMask, annotateValue(uValue));3417 return reportMsr_GenFunctionEx(uMsr, NULL, uMsr == 0xc001001d, fSkipMask, 0, annotateValue(uValue)); 3404 3418 } 3405 3419 … … 3486 3500 fSkipMask |= UINT32_C(0x0000003f); /* CpuFid */ 3487 3501 3488 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));3502 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue)); 3489 3503 } 3490 3504 … … 3556 3570 fSkipMask |= RT_BIT_64(28); /* Unknown killer bit, possibly applicable to other microarchs. */ 3557 3571 } 3558 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));3572 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue)); 3559 3573 } 3560 3574 … … 3577 3591 | RT_BIT_64(10) /* DcacheAggressivePriority */; 3578 3592 fSkipMask |= RT_BIT_64(46) | RT_BIT_64(45); /* Killer field. Seen bit 46 set, 45 clear. Messing with either means reboot/BSOD. */ 3579 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));3593 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue)); 3580 3594 } 3581 3595 … … 3593 3607 uint64_t fSkipMask = RT_BIT_64(54) /* LateSbzResync */; 3594 3608 fSkipMask |= RT_BIT_64(35); /* Undocumented killer bit. */ 3595 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));3609 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue)); 3596 3610 } 3597 3611 … … 3683 3697 rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i); 3684 3698 else if (uMsr == 0x00002000 && g_enmVendor == CPUMCPUVENDOR_INTEL) 3685 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 0, X86_CR0_PE | X86_CR0_PG, 3699 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 0, X86_CR0_PE | X86_CR0_PG, 0, 3686 3700 annotateIfMissingBits(uValue, X86_CR0_PE | X86_CR0_PE | X86_CR0_ET)); 3687 3701 else if (uMsr == 0x00002002 && g_enmVendor == CPUMCPUVENDOR_INTEL) 3688 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 2, 0, annotateValue(uValue));3702 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 2, 0, 0, annotateValue(uValue)); 3689 3703 else if (uMsr == 0x00002003 && g_enmVendor == CPUMCPUVENDOR_INTEL) 3690 3704 { … … 3692 3706 if (!vbCpuRepSupportsPae()) 3693 3707 fCr3Mask &= X86_CR3_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK; 3694 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 3, fCr3Mask, annotateValue(uValue));3708 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 3, fCr3Mask, 0, annotateValue(uValue)); 3695 3709 } 3696 3710 else if (uMsr == 0x00002004 && g_enmVendor == CPUMCPUVENDOR_INTEL) 3697 3711 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 4, 3698 X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_SMXE, 3712 X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_SMXE, 0, 3699 3713 annotateValue(uValue)); 3700 3714 else if (uMsr == 0xc0000080) 3701 3715 rc = reportMsr_Amd64Efer(uMsr, uValue); 3702 3716 else if (uMsr == 0xc0000082 || uMsr == 0xc0000083 || uMsr == 0xc0000100 || uMsr == 0xc0000101 || uMsr == 0xc0000102) 3703 rc = reportMsr_GenFunctionEx(uMsr, NULL, 0, UINT64_C(0xffff800000000000), annotateValue(uValue)); /* Canoncial address hack. */3717 rc = reportMsr_GenFunctionEx(uMsr, NULL, 0, UINT64_C(0xffff800000000000), 0, annotateValue(uValue)); /* Canoncial address hack. */ 3704 3718 else if (uMsr >= 0xc0000408 && uMsr <= 0xc000040f) 3705 3719 rc = reportMsr_AmdFam10hMc4MiscN(&paMsrs[i], cMsrs - i, &i);
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