Changeset 50141 in vbox
- Timestamp:
- Jan 21, 2014 4:10:44 PM (11 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
r49482 r50141 726 726 && (pSRegCS->Attr.n.u4Type & X86_SEL_TYPE_CODE)) 727 727 { 728 /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 729 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */ 730 if ( pSRegCS->Attr.n.u1Long 731 && CPUMIsGuestInLongMode(pVCpu)) 732 { 733 *ppvFlat = Addr; 734 return VINF_SUCCESS; 735 } 736 728 737 /* 729 * Check level. 738 * Limit check. Note that the limit in the hidden register is the 739 * final value. The granularity bit was included in its calculation. 730 740 */ 731 unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL); 732 if ( !(pSRegCS->Attr.n.u4Type & X86_SEL_TYPE_CONF) 733 ? uLevel <= pSRegCS->Attr.n.u2Dpl 734 : uLevel >= pSRegCS->Attr.n.u2Dpl /* hope I got this right now... */ 735 ) 741 uint32_t u32Limit = pSRegCS->u32Limit; 742 if ((RTGCUINTPTR)Addr <= u32Limit) 736 743 { 737 /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 738 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */ 739 if ( pSRegCS->Attr.n.u1Long 740 && CPUMIsGuestInLongMode(pVCpu)) 741 { 742 *ppvFlat = Addr; 743 return VINF_SUCCESS; 744 } 745 746 /* 747 * Limit check. Note that the limit in the hidden register is the 748 * final value. The granularity bit was included in its calculation. 749 */ 750 uint32_t u32Limit = pSRegCS->u32Limit; 751 if ((RTGCUINTPTR)Addr <= u32Limit) 752 { 753 *ppvFlat = Addr + pSRegCS->u64Base; 754 return VINF_SUCCESS; 755 } 756 757 return VERR_OUT_OF_SELECTOR_BOUNDS; 744 *ppvFlat = Addr + pSRegCS->u64Base; 745 return VINF_SUCCESS; 758 746 } 759 Log(("selmValidateAndConvertCSAddrHidden: Invalid RPL Attr.n.u4Type=%x cpl=%x dpl=%x\n", 760 pSRegCS->Attr.n.u4Type, uLevel, pSRegCS->Attr.n.u2Dpl)); 761 return VERR_INVALID_RPL; 747 748 return VERR_OUT_OF_SELECTOR_BOUNDS; 762 749 } 763 750 return VERR_NOT_CODE_SELECTOR;
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