Changeset 50748 in vbox for trunk/src/VBox

Timestamp:

Mar 12, 2014 2:29:06 PM (11 years ago)

Author:

vboxsync

Message:

VMM/HMR0: cleanup.

File:

• trunk/src/VBox/VMM/VMMR0/HMR0.cpp (modified) (14 diffs)

trunk/src/VBox/VMM/VMMR0/HMR0.cpp

@@ -1008 +1008 @@
         rc = SUPR0EnableVTx(true /* fEnable */);
         if (RT_SUCCESS(rc))
+        {
             /* If the host provides a VT-x init API, then we'll rely on that for global init. */
             g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
+        }
         else
             AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
@@ -1060 +1062 @@
 VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
 {
-    /* Make sure we don't touch HM after we've disabled HM in
-       preparation of a suspend. */
+    /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
     if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
         return VERR_HM_SUSPEND_PENDING;
@@ -1330 +1331 @@
     AssertReturn(pVM, VERR_INVALID_PARAMETER);
 
-    /* Make sure we don't touch HM after we've disabled HM in
-       preparation of a suspend. */
+    /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
     AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
 
@@ -1391 +1391 @@
         rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
 
-    /* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
+    /* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
     HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE);
     pVCpu->hm.s.idEnteredCpu = idCpu;
@@ -1430 +1430 @@
     AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
 
-    /* Load the host as we may be resuming code after a longjmp and quite
+    /* Load the host-state as we may be resuming code after a longjmp and quite
        possibly now be scheduled on a different CPU. */
     rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
@@ -1440 +1440 @@
 #endif
 
-    /* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
-       and ring-3 calls. */
+    /* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
     if (RT_FAILURE(rc))
         pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
@@ -1895 +1894 @@
 # if HC_ARCH_BITS == 64
     uint64_t    u32Base  = X86DESC64_BASE(pDesc);
-
     Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
          Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
 # else
     uint32_t    u32Base  = X86DESC_BASE(pDesc);
-
     Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
          Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
@@ -1926 +1923 @@
     } const s_aFlags[] =
     {
-        { "vip",NULL, X86_EFL_VIP },
-        { "vif",NULL, X86_EFL_VIF },
-        { "ac", NULL, X86_EFL_AC },
-        { "vm", NULL, X86_EFL_VM },
-        { "rf", NULL, X86_EFL_RF },
-        { "nt", NULL, X86_EFL_NT },
-        { "ov", "nv", X86_EFL_OF },
-        { "dn", "up", X86_EFL_DF },
-        { "ei", "di", X86_EFL_IF },
-        { "tf", NULL, X86_EFL_TF },
-        { "nt", "pl", X86_EFL_SF },
-        { "nz", "zr", X86_EFL_ZF },
-        { "ac", "na", X86_EFL_AF },
-        { "po", "pe", X86_EFL_PF },
-        { "cy", "nc", X86_EFL_CF },
+        { "vip", NULL, X86_EFL_VIP },
+        { "vif", NULL, X86_EFL_VIF },
+        { "ac",  NULL, X86_EFL_AC },
+        { "vm",  NULL, X86_EFL_VM },
+        { "rf",  NULL, X86_EFL_RF },
+        { "nt",  NULL, X86_EFL_NT },
+        { "ov",  "nv", X86_EFL_OF },
+        { "dn",  "up", X86_EFL_DF },
+        { "ei",  "di", X86_EFL_IF },
+        { "tf",  NULL, X86_EFL_TF },
+        { "nt",  "pl", X86_EFL_SF },
+        { "nz",  "zr", X86_EFL_ZF },
+        { "ac",  "na", X86_EFL_AF },
+        { "po",  "pe", X86_EFL_PF },
+        { "cy",  "nc", X86_EFL_CF },
     };
     char szEFlags[80];
     char *psz = szEFlags;
-    uint32_t efl = pCtx->eflags.u32;
+    uint32_t uEFlags = pCtx->eflags.u32;
     for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
     {
-        const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
+        const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
         if (pszAdd)
         {
@@ -1985 +1982 @@
              pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
              pCtx->r14, pCtx->r15,
-             pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
+             pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
              pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
              pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
@@ -1995 +1992 @@
              pCtx->dr[0],  pCtx->dr[1], pCtx->dr[2],  pCtx->dr[3],
              pCtx->dr[4],  pCtx->dr[5], pCtx->dr[6],  pCtx->dr[7],
-             pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
+             pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
              pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
              pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
@@ -2015 +2012 @@
              ,
              pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
-             pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
+             pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
              pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0],  pCtx->dr[1],
              pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2],  pCtx->dr[3],
@@ -2022 +2019 @@
              pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0,  pCtx->cr2,
              pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3,  pCtx->cr4,
-             pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
+             pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
              pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
              pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
@@ -2036 +2033 @@
         pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
         pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
-
 
     Log(("MSR:\n"
@@ -2053 +2049 @@
         pCtx->msrSFMASK,
         pCtx->msrKERNELGSBASE));
-
 }