Changeset 51182 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- May 5, 2014 12:08:40 PM (11 years ago)
- svn:sync-xref-src-repo-rev:
- 93555
- Location:
- trunk/src/VBox/VMM/VMMR0
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r50856 r51182 4845 4845 /* 4846 4846 * AMD-V does not provide us with the original exception but we have it in u64IntInfo since we 4847 * injected the event during VM-entry. Software interrupts and exceptions will be regenerated 4848 * when the recompiler restarts the instruction. 4847 * injected the event during VM-entry. 4849 4848 */ 4850 4849 SVMEVENT Event; 4851 4850 Event.u = pVCpu->hm.s.Event.u64IntInfo; 4852 if ( Event.n.u3Type == SVM_EVENT_EXCEPTION 4853 || Event.n.u3Type == SVM_EVENT_SOFTWARE_INT) 4854 { 4855 pVCpu->hm.s.Event.fPending = false; 4856 } 4857 else 4858 Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector)); 4851 Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. u8Vector=%#x\n", Event.n.u8Vector)); 4852 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch); 4853 return VINF_EM_RAW_INJECT_TRPM_EVENT; 4859 4854 } 4860 4855 -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r51145 r51182 10650 10650 uint32_t uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo); 10651 10651 10652 /* Software interrupts and exceptions will be regenerated when the recompiler restarts the instruction. */ 10653 if ( uIntType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT 10654 && uIntType != VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 10655 && uIntType != VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT) 10652 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo); 10653 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo); 10654 10655 /* Save it as a pending event and it'll be converted to a TRPM event on the way out to ring-3. */ 10656 Assert(!pVCpu->hm.s.Event.fPending); 10657 pVCpu->hm.s.Event.fPending = true; 10658 pVCpu->hm.s.Event.u64IntInfo = pVmxTransient->uIdtVectoringInfo; 10659 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient); 10660 AssertRCReturn(rc, rc); 10661 if (fErrorCodeValid) 10662 pVCpu->hm.s.Event.u32ErrCode = pVmxTransient->uIdtVectoringErrorCode; 10663 else 10664 pVCpu->hm.s.Event.u32ErrCode = 0; 10665 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 10666 && uVector == X86_XCPT_PF) 10656 10667 { 10657 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo); 10658 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo); 10659 10660 /* Save it as a pending event and it'll be converted to a TRPM event on the way out to ring-3. */ 10661 Assert(!pVCpu->hm.s.Event.fPending); 10662 pVCpu->hm.s.Event.fPending = true; 10663 pVCpu->hm.s.Event.u64IntInfo = pVmxTransient->uIdtVectoringInfo; 10664 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient); 10665 AssertRCReturn(rc, rc); 10666 if (fErrorCodeValid) 10667 pVCpu->hm.s.Event.u32ErrCode = pVmxTransient->uIdtVectoringErrorCode; 10668 else 10669 pVCpu->hm.s.Event.u32ErrCode = 0; 10670 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 10671 && uVector == X86_XCPT_PF) 10672 { 10673 pVCpu->hm.s.Event.GCPtrFaultAddress = pMixedCtx->cr2; 10674 } 10675 10676 Log4(("Pending event on TaskSwitch uIntType=%#x uVector=%#x\n", uIntType, uVector)); 10668 pVCpu->hm.s.Event.GCPtrFaultAddress = pMixedCtx->cr2; 10677 10669 } 10670 10671 Log4(("Pending event on TaskSwitch uIntType=%#x uVector=%#x\n", uIntType, uVector)); 10672 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch); 10673 return VINF_EM_RAW_INJECT_TRPM_EVENT; 10678 10674 } 10679 10675 }
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