- Timestamp:
- May 22, 2014 4:42:22 AM (11 years ago)
- Location:
- trunk
- Files:
-
- 10 edited
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include/VBox/vmm/cpum.h (modified) (2 diffs)
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include/VBox/vmm/gim.h (modified) (4 diffs)
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src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMAll/GIMAll.cpp (modified) (3 diffs)
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src/VBox/VMM/VMMAll/GIMAllHv.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR3/GIM.cpp (modified) (6 diffs)
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src/VBox/VMM/VMMR3/GIMHv.cpp (modified) (6 diffs)
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src/VBox/VMM/VMMR3/GIMMinimal.cpp (modified) (1 diff)
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src/VBox/VMM/include/GIMHvInternal.h (modified) (1 diff)
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src/VBox/VMM/include/GIMInternal.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/cpum.h
r51285 r51333 595 595 kCpumMsrRdFn_AmdFam14hIbsBrTarget, 596 596 597 kCpumMsrRdFn_Gim, 598 597 599 /** End of valid MSR read function indexes. */ 598 600 kCpumMsrRdFn_End … … 817 819 kCpumMsrWrFn_AmdFam14hIbsBrTarget, 818 820 821 kCpumMsrWrFn_Gim, 822 819 823 /** End of valid MSR write function indexes. */ 820 824 kCpumMsrWrFn_End -
trunk/include/VBox/vmm/gim.h
r50994 r51333 31 31 #include <VBox/param.h> 32 32 33 #include <VBox/vmm/cpum.h> 34 35 /** The value used to specify that VirtualBox must use the newest 36 * implementation version of the GIM provider. */ 37 #define GIM_VERSION_LATEST UINT32_C(0) 38 33 39 RT_C_DECLS_BEGIN 34 40 … … 40 46 * Providers identifiers. 41 47 */ 42 typedef enum GIMPROVIDER 48 typedef enum GIMPROVIDERID 43 49 { 44 50 /** None. */ 45 GIMPROVIDER _NONE = 0,51 GIMPROVIDERID_NONE = 0, 46 52 /** Minimal. */ 47 GIMPROVIDER _MINIMAL,53 GIMPROVIDERID_MINIMAL, 48 54 /** Microsoft Hyper-V. */ 49 GIMPROVIDER _HYPERV,55 GIMPROVIDERID_HYPERV, 50 56 /** Linux KVM Interface. */ 51 GIMPROVIDER _KVM,57 GIMPROVIDERID_KVM, 52 58 /** Ensure 32-bit type. */ 53 GIMPROVIDER _32BIT_HACK = 0x7fffffff54 } GIMPROVIDER ;59 GIMPROVIDERID_32BIT_HACK = 0x7fffffff 60 } GIMPROVIDERID; 55 61 56 62 63 #if 0 57 64 /** 58 65 * A GIM Hypercall handler. … … 64 71 /** Pointer to a GIM hypercall handler. */ 65 72 typedef FNGIMHYPERCALL *PFNGIMHYPERCALL; 73 74 /** 75 * A GIM MSR-read handler. 76 * 77 * @returns VBox status code. 78 * @param pVM Pointer to the VMCPU. 79 * @param idMsr The MSR being read. 80 * @param pRange The range that the MSR belongs to. 81 * @param puValue Where to store the value of the MSR. 82 */ 83 typedef DECLCALLBACK(int) FNGIMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 84 /** Pointer to a GIM MSR-read handler. */ 85 typedef FNGIMRDMSR *PFNGIMRDMSR; 86 87 /** 88 * A GIM MSR-write handler. 89 * 90 * @returns VBox status code. 91 * @param pVM Pointer to the VMCPU. 92 * @param idMsr The MSR being written. 93 * @param pRange The range that the MSR belongs to. 94 * @param uValue The value to set, ignored bits masked. 95 * @param uRawValue The raw value with the ignored bits not masked. 96 */ 97 typedef DECLCALLBACK(int) FNGIMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue); 98 /** Pointer to a GIM MSR-write handler. */ 99 typedef FNGIMWRMSR *PFNGIMWRMSR; 100 #endif 101 66 102 67 103 #ifdef IN_RC … … 88 124 * @{ 89 125 */ 90 VMMR3_INT_DECL(int) 91 VMMR3_INT_DECL(int) 126 VMMR3_INT_DECL(int) GIMR3Init(PVM pVM); 127 VMMR3_INT_DECL(int) GIMR3Term(PVM pVM); 92 128 /** @} */ 93 129 #endif /* IN_RING3 */ 94 130 95 96 /** 97 * Checks whether GIM is being used by this VM. 98 * 99 * @retval @c true if used. 100 * @retval @c false if no GIM provider ("none") is used. 101 * 102 * @param pVM Pointer to the VM. 103 * @internal 104 */ 105 VMMDECL(bool) GIMIsEnabled(PVM pVM); 131 VMMDECL(bool) GIMIsEnabled(PVM pVM); 132 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 133 VMM_INT_DECL(int) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 134 VMM_INT_DECL(int) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue); 106 135 107 136 /** @} */ -
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r51301 r51333 24 24 #include <VBox/vmm/hm.h> 25 25 #include <VBox/vmm/tm.h> 26 #include <VBox/vmm/gim.h> 26 27 #include "CPUMInternal.h" 27 28 #include <VBox/vmm/vm.h> … … 4388 4389 } 4389 4390 4391 4392 4393 /* 4394 * GIM MSRs. 4395 * GIM MSRs. 4396 * GIM MSRs. 4397 */ 4398 4399 4400 /** @callback_method_impl{FNCPUMRDMSR} */ 4401 static DECLCALLBACK(int) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4402 { 4403 return GIMReadMsr(pVCpu, idMsr, pRange, puValue); 4404 } 4405 4406 4407 /** @callback_method_impl{FNCPUMWRMSR} */ 4408 static DECLCALLBACK(int) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4409 { 4410 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue); 4411 } 4390 4412 4391 4413 … … 4646 4668 cpumMsrRd_AmdFam10hIbsCtl, 4647 4669 cpumMsrRd_AmdFam14hIbsBrTarget, 4670 4671 cpumMsrRd_Gim 4648 4672 }; 4649 4673 … … 4860 4884 cpumMsrWr_AmdFam10hIbsCtl, 4861 4885 cpumMsrWr_AmdFam14hIbsBrTarget, 4886 4887 cpumMsrWr_Gim 4862 4888 }; 4863 4889 -
trunk/src/VBox/VMM/VMMAll/GIMAll.cpp
r50953 r51333 22 22 #define LOG_GROUP LOG_GROUP_GIM 23 23 #include "GIMInternal.h" 24 #include <VBox/err.h> 24 25 #include <VBox/vmm/vm.h> 25 26 27 /* Include all the providers. */ 28 #include "GIMHvInternal.h" 29 #include "GIMMinimalInternal.h" 26 30 31 32 /** 33 * Checks whether GIM is being used by this VM. 34 * 35 * @retval @c true if used. 36 * @retval @c false if no GIM provider ("none") is used. 37 * 38 * @param pVM Pointer to the VM. 39 * @internal 40 */ 27 41 VMMDECL(bool) GIMIsEnabled(PVM pVM) 28 42 { … … 31 45 32 46 47 /** 48 * Implements a GIM hypercall with the provider configured for the VM. 49 * 50 * @returns VBox status code. 51 * @param pVCpu Pointer to the VMCPU. 52 * @param pCtx Pointer to the guest-CPU context. 53 */ 33 54 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx) 34 55 { … … 37 58 VMCPU_ASSERT_EMT(pVCpu); 38 59 39 return pVM->gim.s.CTX_SUFF(pfnHypercall)(pVCpu, pCtx); 60 switch (pVM->gim.s.enmProviderId) 61 { 62 case GIMPROVIDERID_HYPERV: 63 return GIMHvHypercall(pVCpu, pCtx); 64 65 default: 66 AssertMsgFailed(("GIMHypercall: for unknown provider %u\n", pVM->gim.s.enmProviderId)); 67 return VERR_INTERNAL_ERROR_5; /** @todo Define and use VERR_GIM_HYPERCALL_UNEXPECTED */; 68 } 40 69 } 41 70 71 72 /** 73 * Invokes the read-MSR handler for the GIM provider configured for the VM. 74 * 75 * @returns VBox status code. 76 * @param pVCpu Pointer to the VMCPU. 77 * @param idMsr The MSR to read. 78 * @param pRange The range this MSR belongs to. 79 * @param puValue Where to store the MSR value read. 80 */ 81 VMM_INT_DECL(int) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 82 { 83 PVM pVM = pVCpu->CTX_SUFF(pVM); 84 Assert(GIMIsEnabled(pVM)); 85 VMCPU_ASSERT_EMT(pVCpu); 86 87 switch (pVM->gim.s.enmProviderId) 88 { 89 case GIMPROVIDERID_HYPERV: 90 return GIMHvReadMsr(pVCpu, idMsr, pRange, puValue); 91 92 default: 93 AssertMsgFailed(("GIMReadMsr: for unknown provider %u idMsr=%#RX32 -> #GP(0)", pVM->gim.s.enmProviderId, idMsr)); 94 return VERR_CPUM_RAISE_GP_0; 95 } 96 } 97 98 99 /** 100 * Invokes the write-MSR handler for the GIM provider configured for the VM. 101 * 102 * @returns VBox status code. 103 * @param pVCpu Pointer to the VMCPU. 104 * @param idMsr The MSR to write. 105 * @param pRange The range this MSR belongs to. 106 * @param uValue The value to set, ignored bits masked. 107 * @param uRawValue The raw value with the ignored bits not masked. 108 */ 109 VMM_INT_DECL(int) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 110 { 111 PVM pVM = pVCpu->CTX_SUFF(pVM); 112 Assert(GIMIsEnabled(pVM)); 113 VMCPU_ASSERT_EMT(pVCpu); 114 115 switch (pVM->gim.s.enmProviderId) 116 { 117 case GIMPROVIDERID_HYPERV: 118 return GIMHvWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue); 119 120 default: 121 AssertMsgFailed(("GIMWriteMsr: for unknown provider %u idMsr=%#RX32 -> #GP(0)", pVM->gim.s.enmProviderId, idMsr)); 122 return VERR_CPUM_RAISE_GP_0; 123 } 124 } 125 -
trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp
r50953 r51333 30 30 } 31 31 32 33 DECLEXPORT(int) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 34 { 35 return VINF_SUCCESS; 36 } 37 38 39 DECLEXPORT(int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 40 { 41 return VINF_SUCCESS; 42 } 43 -
trunk/src/VBox/VMM/VMMR3/GIM.cpp
r50994 r51333 28 28 * A GIM provider implements a particular hypervisor interface such as Microsoft 29 29 * Hyper-V, Linux KVM and so on. It hooks into various components in the VMM to 30 * ease the guest in running under a recognized virtualized environment. Thisis31 * also referred to as paravirtualization interfaces.30 * ease the guest in running under a recognized, virtualized environment. This 31 * is also referred to as paravirtualization interfaces. 32 32 * 33 33 * The idea behind this is primarily for making guests more accurate and … … 39 39 * itself, resulting in higher accuracy and saving several CPU cycles. 40 40 * 41 * Only one provider can be active for a running VM. 41 * At most, only one GIM provider can be active for a running VM and cannot be 42 * changed during the lifetime of the VM. 42 43 */ 43 44 … … 105 106 AssertLogRelRCReturn(rc, rc); 106 107 108 /** @cfgm{GIM/Version, uint32_t} 109 * The interface version. The default is 0, which means "provide the most 110 * up-to-date implementation". */ 111 uint32_t uVersion; 112 rc = CFGMR3QueryU32Def(pCfgNode, "Version", &uVersion, 0 /* default */); 113 AssertLogRelRCReturn(rc, rc); 114 107 115 /* 108 116 * Setup the GIM provider for this VM. 109 117 */ 110 LogRel(("GIM: Using provider \"%s\" \n", szProvider));118 LogRel(("GIM: Using provider \"%s\" version %u\n", szProvider, uVersion)); 111 119 if (!RTStrCmp(szProvider, "None")) 112 120 { 113 121 Assert(!pVM->gim.s.fEnabled); 114 pVM->gim.s.enmProvider = GIMPROVIDER_NONE;122 pVM->gim.s.enmProviderId = GIMPROVIDERID_NONE; 115 123 } 116 124 else 117 125 { 118 126 pVM->gim.s.fEnabled = true; 127 pVM->gim.s.u32Version = uVersion; 119 128 if (!RTStrCmp(szProvider, "Minimal")) 120 129 { 121 pVM->gim.s.enmProvider = GIMPROVIDER_MINIMAL;130 pVM->gim.s.enmProviderId = GIMPROVIDERID_MINIMAL; 122 131 rc = GIMR3MinimalInit(pVM); 123 132 } 124 133 else if (!RTStrCmp(szProvider, "HyperV")) 125 134 { 126 pVM->gim.s.enmProvider = GIMPROVIDER_HYPERV;135 pVM->gim.s.enmProviderId = GIMPROVIDERID_HYPERV; 127 136 rc = GIMR3HvInit(pVM); 128 137 } … … 157 166 } 158 167 159 switch (pVM->gim.s.enmProvider )160 { 161 case GIMPROVIDER _MINIMAL:168 switch (pVM->gim.s.enmProviderId) 169 { 170 case GIMPROVIDERID_MINIMAL: 162 171 { 163 172 GIMR3MinimalRelocate(pVM, offDelta); … … 165 174 } 166 175 167 case GIMPROVIDER _HYPERV:176 case GIMPROVIDERID_HYPERV: 168 177 { 169 178 GIMR3HvRelocate(pVM, offDelta); … … 171 180 } 172 181 173 case GIMPROVIDER _KVM: /** @todo KVM. */182 case GIMPROVIDERID_KVM: /** @todo KVM. */ 174 183 default: 175 184 { 176 AssertMsgFailed(("Invalid provider id %#x\n", pVM->gim.s.enmProvider));185 AssertMsgFailed(("Invalid provider Id %#x\n", pVM->gim.s.enmProviderId)); 177 186 break; 178 187 } -
trunk/src/VBox/VMM/VMMR3/GIMHv.cpp
r50953 r51333 25 25 #include <iprt/assert.h> 26 26 #include <iprt/err.h> 27 #include <iprt/string.h> 27 28 28 29 #include <VBox/vmm/cpum.h> … … 30 31 #include <VBox/vmm/hm.h> 31 32 #include <VBox/vmm/pdmapi.h> 33 #include <VBox/version.h> 32 34 33 35 /******************************************************************************* … … 37 39 38 40 41 /** 42 * Initializes the Hyper-V GIM provider. 43 * 44 * @returns VBox status code. 45 * @param pVM Pointer to the VM. 46 * @param uVersion The interface version this VM should use. 47 */ 39 48 VMMR3_INT_DECL(int) GIMR3HvInit(PVM pVM) 40 49 { 41 50 AssertReturn(pVM, VERR_INVALID_PARAMETER); 42 AssertReturn(pVM->gim.s.enmProvider == GIMPROVIDER_HYPERV, VERR_INTERNAL_ERROR_5);51 AssertReturn(pVM->gim.s.enmProviderId == GIMPROVIDERID_HYPERV, VERR_INTERNAL_ERROR_5); 43 52 44 53 int rc; 54 #if 0 45 55 pVM->gim.s.pfnHypercallR3 = &GIMHvHypercall; 46 56 if (!HMIsEnabled(pVM)) … … 51 61 rc = PDMR3LdrGetSymbolR0(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallR0); 52 62 AssertRCReturn(rc, rc); 63 #endif 64 65 /* 66 * Determine interface capabilities based on the version. 67 */ 68 uint32_t uBaseFeat = 0; 69 uint32_t uPartFlags = 0; 70 uint32_t uPowMgmtFeat = 0; 71 uint32_t uMiscFeat = 0; 72 uint32_t uHyperHints = 0; 73 if (!pVM->gim.s.u32Version) 74 { 75 uBaseFeat = GIM_HV_BASE_FEAT_PART_REF_COUNT_MSR; 76 pVM->gim.s.u.hv.u16HyperIdVersionMajor = VBOX_VERSION_MAJOR; 77 pVM->gim.s.u.hv.u16HyperIdVersionMajor = VBOX_VERSION_MINOR; 78 pVM->gim.s.u.hv.u32HyperIdBuildNumber = VBOX_VERSION_BUILD; 79 } 53 80 54 81 /* … … 57 84 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP); 58 85 59 /** @todo Register CPUID leaves, MSR ranges with CPUM. */ 86 /* 87 * Modify the standard hypervisor leaves for Hyper-V. 88 */ 89 CPUMCPUIDLEAF HyperLeaf; 90 RT_ZERO(HyperLeaf); 91 HyperLeaf.uLeaf = UINT32_C(0x40000000); 92 HyperLeaf.uEax = UINT32_C(0x40000005); /* Minimum value for Hyper-V */ 93 HyperLeaf.uEbx = 0x7263694D; /* 'Micr' */ 94 HyperLeaf.uEcx = 0x666F736F; /* 'osof' */ 95 HyperLeaf.uEdx = 0x76482074; /* 't Hv' */ 96 rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf); 97 AssertLogRelRCReturn(rc, rc); 98 99 HyperLeaf.uLeaf = UINT32_C(0x40000001); 100 HyperLeaf.uEax = 0x31237648; /* 'Hv#1' */ 101 HyperLeaf.uEbx = 0; /* Reserved */ 102 HyperLeaf.uEcx = 0; /* Reserved */ 103 HyperLeaf.uEdx = 0; /* Reserved */ 104 rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf); 105 AssertLogRelRCReturn(rc, rc); 106 107 /* 108 * Add Hyper-V specific leaves. 109 */ 110 HyperLeaf.uLeaf = UINT32_C(0x40000002); /* MBZ until MSR_HV_GUEST_OS_ID is set by the guest. */ 111 HyperLeaf.uEax = 0; 112 HyperLeaf.uEbx = 0; 113 HyperLeaf.uEcx = 0; 114 HyperLeaf.uEdx = 0; 115 rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf); 116 AssertLogRelRCReturn(rc, rc); 117 118 HyperLeaf.uLeaf = UINT32_C(0x40000003); 119 HyperLeaf.uEax = uBaseFeat; 120 HyperLeaf.uEbx = uPartFlags; 121 HyperLeaf.uEcx = uPowMgmtFeat; 122 HyperLeaf.uEdx = uMiscFeat; 123 rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf); 124 AssertLogRelRCReturn(rc, rc); 125 126 /* 127 * Register the complete MSR range for Hyper-V. 128 */ 129 CPUMMSRRANGE MsrRange; 130 RT_ZERO(MsrRange); 131 MsrRange.uFirst = UINT32_C(0x40000000); 132 MsrRange.uLast = UINT32_C(0x40000105); 133 MsrRange.enmRdFn = kCpumMsrRdFn_Gim; 134 MsrRange.enmWrFn = kCpumMsrWrFn_Gim; 135 RTStrCopy(MsrRange.szName, sizeof(MsrRange.szName), "Hyper-V"); 136 rc = CPUMR3MsrRangesInsert(pVM, &MsrRange); 137 AssertLogRelRCReturn(rc, rc); 138 139 60 140 return VINF_SUCCESS; 61 141 } … … 64 144 VMMR3_INT_DECL(void) GIMR3HvRelocate(PVM pVM, RTGCINTPTR offDelta) 65 145 { 66 int rc = PDMR3LdrGetSymbolRC(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallRC);67 AssertFatalRC(rc);146 // int rc = PDMR3LdrGetSymbolRC(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallRC); 147 // AssertFatalRC(rc); 68 148 } 69 149 -
trunk/src/VBox/VMM/VMMR3/GIMMinimal.cpp
r50994 r51333 36 36 { 37 37 AssertReturn(pVM, VERR_INVALID_PARAMETER); 38 AssertReturn(pVM->gim.s.enmProvider == GIMPROVIDER_MINIMAL, VERR_INTERNAL_ERROR_5);38 AssertReturn(pVM->gim.s.enmProviderId == GIMPROVIDERID_MINIMAL, VERR_INTERNAL_ERROR_5); 39 39 40 40 Assert(CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP)); -
trunk/src/VBox/VMM/include/GIMHvInternal.h
r50953 r51333 21 21 #include <iprt/cdefs.h> 22 22 #include <VBox/types.h> 23 #include <VBox/vmm/cpum.h> 24 25 /** @name Hyper-V base feature identification. 26 * Base features based on current partition privileges. 27 * @{ 28 */ 29 /** Virtual processor runtime MSR available. */ 30 #define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0) 31 /** Partition reference counter MSR available. */ 32 #define GIM_HV_BASE_FEAT_PART_REF_COUNT_MSR RT_BIT(1) 33 /** Basic Synthetic Interrupt Controller MSRs available. */ 34 #define GIM_HV_BASE_FEAT_BASIC_SYNTH_IC RT_BIT(2) 35 /** Synthetic Timer MSRs available. */ 36 #define GIM_HV_BASE_FEAT_SYNTH_TIMER_MSRS RT_BIT(3) 37 /** APIC access MSRs (EOI, ICR, TPR) available. */ 38 #define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4) 39 /** Hypercall MSRs available. */ 40 #define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5) 41 /** Access to VCPU index MSR available. */ 42 #define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6) 43 /** Virtual system reset MSR available. */ 44 #define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7) 45 /** Statistic pages MSRs available. */ 46 #define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8) 47 /** Paritition reference TSC MSR available. */ 48 #define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9) 49 /** Virtual guest idle state MSR available. */ 50 #define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10) 51 /** Timer frequency MSRs available. */ 52 #define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11) 53 /** Debug MSRs available. */ 54 #define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12) 55 /** @} */ 56 57 /** @name Hyper-V partition-creation feature identification. 58 * Indicates flags specified during partition creation. 59 * @{ 60 */ 61 /** Create partitions. */ 62 #define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0) 63 /** Access partition Id. */ 64 #define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1) 65 /** Access memory pool. */ 66 #define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2) 67 /** Adjust message buffers. */ 68 #define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3) 69 /** Post messages. */ 70 #define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4) 71 /** Signal events. */ 72 #define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5) 73 /** Create port. */ 74 #define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6) 75 /** Connect port. */ 76 #define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7) 77 /** Access statistics. */ 78 #define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8) 79 /** Debugging.*/ 80 #define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11) 81 /** CPU management. */ 82 #define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12) 83 /** CPU profiler. */ 84 #define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13) 85 /** Enable expanded stack walking. */ 86 #define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14) 87 /** @} */ 88 89 /** @name Hyper-V power management feature identification. 90 * @{ 91 */ 92 /** Maximum CPU power state C0. */ 93 #define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0) 94 /** Maximum CPU power state C1. */ 95 #define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1) 96 /** Maximum CPU power state C2. */ 97 #define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2) 98 /** Maximum CPU power state C3. */ 99 #define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3) 100 /** HPET is required to enter C3 power state. */ 101 #define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4) 102 /** @} */ 103 104 /** @name Hyper-V miscellaneous feature identification. 105 * Miscellaneous features available for the current partition. 106 * @{ 107 */ 108 /** MWAIT instruction available. */ 109 #define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0) 110 /** Guest debugging support available. */ 111 #define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1) 112 /** Performance monitor support is available. */ 113 #define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2) 114 /** Support for physical CPU dynamic partitioning events. */ 115 #define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3) 116 /** Support for passing hypercall input parameter block via XMM registers. */ 117 #define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4) 118 /** Support for virtual guest idle state. */ 119 #define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5) 120 /** Support for hypervisor sleep state. */ 121 #define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6) 122 /** Support for querying NUMA distances. */ 123 #define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7) 124 /** Support for determining timer frequencies. */ 125 #define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8) 126 /** Support for injecting synthetic machine checks. */ 127 #define GIM_HV_MISC_FEAT_INJECT_SYNTH_MC_XCPT RT_BIT(9) 128 /** Support for guest crash MSRs. */ 129 #define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10) 130 /** Support for debug MSRs. */ 131 #define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11) 132 /** Npiep1 Available */ /** @todo What the heck is this? */ 133 #define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12) 134 /** Disable hypervisor available. */ 135 #define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13) 136 /** @} */ 137 138 /** @name Hyper-V implementation recommendations. 139 * Recommendations from the hypervisor for the guest for optimal performance. 140 * @{ 141 */ 142 /** Use hypercall for address space switches rather than MOV CR3. */ 143 #define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0) 144 /** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */ 145 #define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1) 146 /** Use hypercall for inter-CPU TLB flushes rather than IPIs. */ 147 #define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2) 148 /** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */ 149 #define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3) 150 /** Use hypervisor provided MSR for a system reset. */ 151 #define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4) 152 /** Relax timer-related checks (watchdogs/deadman timeouts) that rely on 153 * timely deliver of external interrupts. */ 154 #define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5) 155 /** Use DMA remapping. */ 156 #define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6) 157 /** Use interrupt remapping. */ 158 #define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7) 159 /** Use X2APIC MSRs rather than MMIO. */ 160 #define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8) 161 /** Deprecate Auto EOI (end of interrupt). */ 162 #define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9) 163 /** @} */ 164 165 166 /** @name Hyper-V implementation hardware features. 167 * Which hardware features are in use by the hypervisor. 168 * @{ 169 */ 170 /** APIC overlay is used. */ 171 #define GIM_HV_HOST_FEAT_AVIC RT_BIT(0) 172 /** MSR bitmaps is used. */ 173 #define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1) 174 /** Architectural performance counter supported. */ 175 #define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2) 176 /** Nested paging is used. */ 177 #define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3) 178 /** DMA remapping is used. */ 179 #define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4) 180 /** Interrupt remapping is used. */ 181 #define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5) 182 /** Memory patrol scrubber is present. */ 183 #define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6) 184 /** @} */ 185 186 187 /** @name Hyper-V MSRs. 188 * @{ 189 */ 190 /** Guest OS identification (R/W) */ 191 #define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000) 192 /** Enable hypercall interface (R/W) */ 193 #define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001) 194 /** Virtual processor's (VCPU) index (R) */ 195 #define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002) 196 /** Reset operation (R/W) */ 197 #define MSR_GIM_HV_RESET UINT32_C(0x40000003) 198 /** Virtual processor's (VCPU) runtime (R) */ 199 #define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010) 200 /** Per-VM reference counter (R) */ 201 #define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020) 202 /** Per-VM TSC (R) */ 203 #define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021) 204 /** Frequency of TSC in Hz as reported by the hypervisor (R) */ 205 #define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022) 206 /** Frequency of LAPIC in Hz as reported by the hypervisor (R) */ 207 #define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023) 208 /** Access to APIC EOI (End-Of-Interrupt) register (W) */ 209 #define MSR_GIM_HV_EOI UINT32_C(0x40000070) 210 /** Access to APIC ICR (Interrupt Command) register (R/W) */ 211 #define MSR_GIM_HV_ICR UINT32_C(0x40000071) 212 /** Access to APIC TPR (Task Priority) register (R/W) */ 213 #define MSR_GIM_HV_TPR UINT32_C(0x40000072) 214 /** Enables lazy EOI processing (R/W) */ 215 #define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073) 216 /** Control behaviour of synthetic interrupt controller (R/W) */ 217 #define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080) 218 /** Synthetic interrupt controller version (R) */ 219 #define MSR_GIM_HV_SVERSION UINT32_C(0x40000081) 220 /** Base address of synthetic interrupt event flag (R/W) */ 221 #define MSR_GIM_HV_SIEFP UINT32_C(0x40000082) 222 /** Base address of synthetic interrupt parameter page (R/W) */ 223 #define MSR_GIM_HV_SIMP UINT32_C(0x40000083) 224 /** End-Of-Message in synthetic interrupt parameter page (W) */ 225 #define MSR_GIM_HV_EOM UINT32_C(0x40000084) 226 /** Configures synthetic interrupt source 0 (R/W) */ 227 #define MSR_GIM_HV_SINT0 UINT32_C(0x40000090) 228 /** Configures synthetic interrupt source 1 (R/W) */ 229 #define MSR_GIM_HV_SINT1 UINT32_C(0x40000091) 230 /** Configures synthetic interrupt source 2 (R/W) */ 231 #define MSR_GIM_HV_SINT2 UINT32_C(0x40000092) 232 /** Configures synthetic interrupt source 3 (R/W) */ 233 #define MSR_GIM_HV_SINT3 UINT32_C(0x40000093) 234 /** Configures synthetic interrupt source 4 (R/W) */ 235 #define MSR_GIM_HV_SINT4 UINT32_C(0x40000094) 236 /** Configures synthetic interrupt source 5 (R/W) */ 237 #define MSR_GIM_HV_SINT5 UINT32_C(0x40000095) 238 /** Configures synthetic interrupt source 6 (R/W) */ 239 #define MSR_GIM_HV_SINT6 UINT32_C(0x40000096) 240 /** Configures synthetic interrupt source 7 (R/W) */ 241 #define MSR_GIM_HV_SINT7 UINT32_C(0x40000097) 242 /** Configures synthetic interrupt source 8 (R/W) */ 243 #define MSR_GIM_HV_SINT8 UINT32_C(0x40000098) 244 /** Configures synthetic interrupt source 9 (R/W) */ 245 #define MSR_GIM_HV_SINT9 UINT32_C(0x40000099) 246 /** Configures synthetic interrupt source 10 (R/W) */ 247 #define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A) 248 /** Configures synthetic interrupt source 11 (R/W) */ 249 #define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B) 250 /** Configures synthetic interrupt source 12 (R/W) */ 251 #define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C) 252 /** Configures synthetic interrupt source 13 (R/W) */ 253 #define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D) 254 /** Configures synthetic interrupt source 14 (R/W) */ 255 #define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E) 256 /** Configures synthetic interrupt source 15 (R/W) */ 257 #define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F) 258 /** Configures register for synthetic timer 0 (R/W) */ 259 #define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0) 260 /** Expiration time or period for synthetic timer 0 (R/W) */ 261 #define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1) 262 /** Configures register for synthetic timer 1 (R/W) */ 263 #define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2) 264 /** Expiration time or period for synthetic timer 1 (R/W) */ 265 #define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3) 266 /** Configures register for synthetic timer 2 (R/W) */ 267 #define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4) 268 /** Expiration time or period for synthetic timer 2 (R/W) */ 269 #define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5) 270 /** Configures register for synthetic timer 3 (R/W) */ 271 #define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6) 272 /** Expiration time or period for synthetic timer 3 (R/W) */ 273 #define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7) 274 /** Trigger to transition to power state C1 (R) */ 275 #define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1) 276 /** Trigger to transition to power state C2 (R) */ 277 #define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2) 278 /** Trigger to transition to power state C3 (R) */ 279 #define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3) 280 /** Configure the recipe for power state transitions to C1 (R/W) */ 281 #define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1) 282 /** Configure the recipe for power state transitions to C2 (R/W) */ 283 #define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2) 284 /** Configure the recipe for power state transitions to C3 (R/W) */ 285 #define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3) 286 /** Map the guest's retail partition stats page (R/W) */ 287 #define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0) 288 /** Map the guest's internal partition stats page (R/W) */ 289 #define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1) 290 /** Map the guest's retail VP stats page (R/W) */ 291 #define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2) 292 /** Map the guest's internal VP stats page (R/W) */ 293 #define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3) 294 /** Trigger the guest's transition to idle power state (R) */ 295 #define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0) 296 /** Synthetic debug control. */ 297 #define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1) 298 /** Synthetic debug status. */ 299 #define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2) 300 /** Synthetic debug send buffer. */ 301 #define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3) 302 /** Synthetic debug receive buffer. */ 303 #define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4) 304 /** Synthetic debug pending buffer. */ 305 #define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5) 306 /** Guest crash MSR 0. */ 307 #define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100) 308 /** Guest crash MSR 1. */ 309 #define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101) 310 /** Guest crash MSR 2. */ 311 #define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102) 312 /** Guest crash MSR 3. */ 313 #define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103) 314 /** Guest crash MSR 4. */ 315 #define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104) 316 /** Guest crash control. */ 317 #define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105) 318 /** @} */ 319 23 320 24 321 RT_C_DECLS_BEGIN 25 322 26 323 #ifdef IN_RING3 27 VMMR3_INT_DECL(int) 28 VMMR3_INT_DECL(void) 324 VMMR3_INT_DECL(int) GIMR3HvInit(PVM pVM); 325 VMMR3_INT_DECL(void) GIMR3HvRelocate(PVM pVM, RTGCINTPTR offDelta); 29 326 #endif /* IN_RING3 */ 30 327 31 DECLEXPORT(int) GIMHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 328 VMMDECL(int) GIMHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 329 VMMDECL(int) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 330 VMMDECL(int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue); 32 331 33 332 RT_C_DECLS_END -
trunk/src/VBox/VMM/include/GIMInternal.h
r50994 r51333 21 21 #include <VBox/vmm/gim.h> 22 22 23 #define GIM_SSM_VERSION 124 25 26 23 RT_C_DECLS_BEGIN 27 24 … … 41 38 bool fEnabled; 42 39 /** The provider that is active for this VM. */ 43 GIMPROVIDER enmProvider; 40 GIMPROVIDERID enmProviderId; 41 /** The interface version. */ 42 uint32_t u32Version; 43 44 #if 0 44 45 /** Pointer to the provider's ring-3 hypercall handler. */ 45 46 R3PTRTYPE(PFNGIMHYPERCALL) pfnHypercallR3; … … 48 49 /** Pointer to the provider's raw-mode context hypercall handler. */ 49 50 RCPTRTYPE(PFNGIMHYPERCALL) pfnHypercallRC; 51 52 /** Pointer to the provider's ring-3 MSR-read handler. */ 53 R3PTRTYPE(PFNGIMRDMSR) pfnReadMsrR3; 54 /** Pointer to the provider's ring-0 MSR-read handler. */ 55 R0PTRTYPE(PFNGIMRDMSR) pfnReadMsrR0; 56 /** Pointer to the provider's raw-mode context MSR-read handler. */ 57 RCPTRTYPE(PFNGIMRDMSR) pfnReadMsrRC; 58 59 /** Pointer to the provider's ring-3 MSR-read handler. */ 60 R3PTRTYPE(PFNGIMWDMSR) pfnWriteMsrR3; 61 /** Pointer to the provider's ring-0 MSR-read handler. */ 62 R0PTRTYPE(PFNGIMWDMSR) pfnWriteMsrRR0; 63 /** Pointer to the provider's raw-mode context MSR-read handler. */ 64 RCPTRTYPE(PFNGIMWDMSR) pfnWriteMsrRRC; 65 #endif 50 66 51 67 union … … 58 74 { 59 75 /** Hypervisor system identity - Minor version number. */ 60 uint16_t u VersionMinor;76 uint16_t u16HyperIdVersionMinor; 61 77 /** Hypervisor system identity - Major version number. */ 62 uint16_t u VersionMajor;63 /** Hypervisor system identify - Service branch (Bits 31-24) and number (Bits64 * 23-0). */65 uint32_t uVersionService; 78 uint16_t u16HyperIdVersionMajor; 79 /** Hypervisor system identify - Build number. */ 80 uint32_t u32HyperIdBuildNumber; 81 66 82 /** Guest OS identity MSR. */ 67 83 uint64_t u64GuestOsIdMsr;
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