VirtualBox

Changeset 51367 in vbox for trunk


Ignore:
Timestamp:
May 23, 2014 7:45:35 AM (11 years ago)
Author:
vboxsync
Message:

VMM/GIM: Hyper-V provider, work-in-progress.

Location:
trunk/src/VBox/VMM
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/GIMAll.cpp

    r51333 r51367  
    8181VMM_INT_DECL(int) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
    8282{
     83    Assert(pVCpu);
    8384    PVM pVM = pVCpu->CTX_SUFF(pVM);
    8485    Assert(GIMIsEnabled(pVM));
    … …  
    109110VMM_INT_DECL(int) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
    110111{
     112    Assert(pVCpu);
    111113    PVM pVM = pVCpu->CTX_SUFF(pVM);
    112114    Assert(GIMIsEnabled(pVM));

  • trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp

    r51333 r51367  
    2323#include "GIMHvInternal.h"
    2424
    25 #include <iprt/err.h>
     25#include <VBox/err.h>
     26#include <VBox/vmm/tm.h>
     27#include <VBox/vmm/vm.h>
    2628
    2729DECLEXPORT(int) GIMHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
    … …  
    3335DECLEXPORT(int) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
    3436{
    35     return VINF_SUCCESS;
     37    NOREF(pRange);
     38    switch (idMsr)
     39    {
     40        case MSR_GIM_HV_TIME_REF_COUNT:
     41        {
     42            /* Hyper-V reports the time in 100ns units. */
     43            uint64_t u64Tsc      = TMCpuTickGet(pVCpu);
     44            uint64_t u64TscHz    = TMCpuTicksPerSecond(pVCpu->CTX_SUFF(pVM));
     45            uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
     46            *puValue = (u64Tsc / u64Tsc100Ns);
     47            return VINF_SUCCESS;
     48        }
     49
     50        case MSR_GIM_HV_VP_INDEX:
     51            *puValue = pVCpu->idCpu;
     52            return VINF_SUCCESS;
     53
     54        default:
     55            break;
     56    }
     57
     58    LogRel(("GIMHvReadMsr: Unknown/invalid RdMsr %#RX32 -> #GP(0)\n", idMsr));
     59    return VERR_CPUM_RAISE_GP_0;
    3660}
    3761
    … …  
    3963DECLEXPORT(int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
    4064{
    41     return VINF_SUCCESS;
     65    LogRel(("GIMHvWriteMsr: Unknown/invalid WrMsr %#RX32 -> #GP(0)\n", idMsr));
     66    return VERR_CPUM_RAISE_GP_0;
    4267}
    4368

  • trunk/src/VBox/VMM/VMMR3/GIM.cpp

    r51333 r51367  
    116116     * Setup the GIM provider for this VM.
    117117     */
    118     LogRel(("GIM: Using provider \"%s\" version %u\n", szProvider, uVersion));
     118    LogRel(("GIM: Using provider \"%s\" (Implementation version: %u)\n", szProvider, uVersion));
    119119    if (!RTStrCmp(szProvider, "None"))
    120120    {
    … …  
    143143        }
    144144    }
    145 
    146145    return rc;
    147146}

  • trunk/src/VBox/VMM/VMMR3/GIMHv.cpp

    r51333 r51367  
    3636*   Defined Constants And Macros                                               *
    3737*******************************************************************************/
    38 #define GIMHV_HYPERCALL                 "GIMHvHypercall"
     38//#define GIMHV_HYPERCALL                 "GIMHvHypercall"
     39#ifdef VBOX_WITH_STATISTICS
     40# define GIMHV_MSRRANGE(a_uFirst, a_uLast, a_szName) \
     41    { (a_uFirst), (a_uLast), kCpumMsrRdFn_Gim, kCpumMsrWrFn_Gim, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
     42#else
     43# define GIMHV_MSRRANGE(a_uFirst, a_uLast, a_szName) \
     44    { (a_uFirst), (a_uLast), kCpumMsrRdFn_Gim, kCpumMsrWrFn_Gim, 0, 0, 0, 0, 0, a_szName }
     45#endif
     46
     47/**
     48 * Array of MSR ranges supported by Hyper-V.
     49 */
     50static CPUMMSRRANGE const g_aMsrRanges_HyperV[] =
     51{
     52    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE0_START,  MSR_GIM_HV_RANGE0_END,  "Hyper-V range 0"),
     53    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE1_START,  MSR_GIM_HV_RANGE1_END,  "Hyper-V range 1"),
     54    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE2_START,  MSR_GIM_HV_RANGE2_END,  "Hyper-V range 2"),
     55    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE3_START,  MSR_GIM_HV_RANGE3_END,  "Hyper-V range 3"),
     56    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE4_START,  MSR_GIM_HV_RANGE4_END,  "Hyper-V range 4"),
     57    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE5_START,  MSR_GIM_HV_RANGE5_END,  "Hyper-V range 5"),
     58    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE6_START,  MSR_GIM_HV_RANGE6_END,  "Hyper-V range 6"),
     59    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE7_START,  MSR_GIM_HV_RANGE7_END,  "Hyper-V range 7"),
     60    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE8_START,  MSR_GIM_HV_RANGE8_END,  "Hyper-V range 8"),
     61    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE9_START,  MSR_GIM_HV_RANGE9_END,  "Hyper-V range 9"),
     62    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE10_START, MSR_GIM_HV_RANGE10_END, "Hyper-V range 10"),
     63    GIMHV_MSRRANGE(MSR_GIM_HV_RANGE11_START, MSR_GIM_HV_RANGE11_END, "Hyper-V range 11")
     64};
     65#undef GIMHV_MSR
    3966
    4067
    … …  
    73100    if (!pVM->gim.s.u32Version)
    74101    {
    75         uBaseFeat = GIM_HV_BASE_FEAT_PART_REF_COUNT_MSR;
     102        uBaseFeat = 0
     103                  //| GIM_HV_BASE_FEAT_VP_RUNTIME_MSR
     104                  | GIM_HV_BASE_FEAT_PART_REF_COUNT_MSR
     105                  //| GIM_HV_BASE_FEAT_BASIC_SYNTH_IC
     106                  //| GIM_HV_BASE_FEAT_SYNTH_TIMER_MSRS
     107                  //| GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS
     108                  //| GIM_HV_BASE_FEAT_HYPERCALL_MSRS
     109                  | GIM_HV_BASE_FEAT_VP_ID_MSR
     110                  //| GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR
     111                  //| GIM_HV_BASE_FEAT_STAT_PAGES_MSR
     112                  //| GIM_HV_BASE_FEAT_PART_REF_TSC_MSR
     113                  //| GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR
     114                  //| GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS
     115                  //| GIM_HV_BASE_FEAT_DEBUG_MSRS
     116                  ;
     117
    76118        pVM->gim.s.u.hv.u16HyperIdVersionMajor = VBOX_VERSION_MAJOR;
    77119        pVM->gim.s.u.hv.u16HyperIdVersionMajor = VBOX_VERSION_MINOR;
    … …  
    108150     * Add Hyper-V specific leaves.
    109151     */
    110     HyperLeaf.uLeaf        = UINT32_C(0x40000002); /* MBZ until MSR_HV_GUEST_OS_ID is set by the guest. */
     152    HyperLeaf.uLeaf        = UINT32_C(0x40000002); /* MBZ until MSR_GIM_HV_GUEST_OS_ID is set by the guest. */
    111153    HyperLeaf.uEax         = 0;
    112154    HyperLeaf.uEbx         = 0;
    … …  
    125167
    126168    /*
    127      * Register the complete MSR range for Hyper-V.
     169     * Insert all MSR ranges of Hyper-V.
    128170     */
    129     CPUMMSRRANGE MsrRange;
    130     RT_ZERO(MsrRange);
    131     MsrRange.uFirst     = UINT32_C(0x40000000);
    132     MsrRange.uLast      = UINT32_C(0x40000105);
    133     MsrRange.enmRdFn    = kCpumMsrRdFn_Gim;
    134     MsrRange.enmWrFn    = kCpumMsrWrFn_Gim;
    135     RTStrCopy(MsrRange.szName, sizeof(MsrRange.szName), "Hyper-V");
    136     rc = CPUMR3MsrRangesInsert(pVM, &MsrRange);
    137     AssertLogRelRCReturn(rc, rc);
    138 
    139 
     171    for (uint32_t i = 0; i < RT_ELEMENTS(g_aMsrRanges_HyperV); i++)
     172    {
     173        rc = CPUMR3MsrRangesInsert(pVM, &g_aMsrRanges_HyperV[i]);
     174        AssertLogRelRCReturn(rc, rc);
     175    }
    140176    return VINF_SUCCESS;
    141177}
    … …  
    144180VMMR3_INT_DECL(void) GIMR3HvRelocate(PVM pVM, RTGCINTPTR offDelta)
    145181{
    146 //    int rc = PDMR3LdrGetSymbolRC(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallRC);
    147 //    AssertFatalRC(rc);
     182#if 0
     183    int rc = PDMR3LdrGetSymbolRC(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallRC);
     184    AssertFatalRC(rc);
     185#endif
    148186}
    149187

  • trunk/src/VBox/VMM/VMMR3/VM.cpp

    r50953 r51367  
    989989                                                                    if (RT_SUCCESS(rc))
    990990                                                                    {
    991                                                                         /* GIM must be init'd after PDM, relies on PDMR3 for
    992                                                                            symbol resolution.*/
     991                                                                        /* GIM must be init'd after PDM, may rely on PDMR3 for
     992                                                                           symbol resolution. */
    993993                                                                        rc = GIMR3Init(pVM);
    994994                                                                        if (RT_SUCCESS(rc))

  • trunk/src/VBox/VMM/include/GIMHvInternal.h

    r51333 r51367  
    188188 * @{
    189189 */
     190/** Start of range 0. */
     191#define MSR_GIM_HV_RANGE0_START                   UINT32_C(0x40000000)
    190192/** Guest OS identification (R/W) */
    191193#define MSR_GIM_HV_GUEST_OS_ID                    UINT32_C(0x40000000)
    … …  
    196198/** Reset operation (R/W) */
    197199#define MSR_GIM_HV_RESET                          UINT32_C(0x40000003)
     200/** End of range 0. */
     201#define MSR_GIM_HV_RANGE0_END                     MSR_GIM_HV_RESET
     202
     203/** Start of range 1. */
     204#define MSR_GIM_HV_RANGE1_START                   UINT32_C(0x40000010)
    198205/** Virtual processor's (VCPU) runtime (R) */
    199206#define MSR_GIM_HV_VP_RUNTIME                     UINT32_C(0x40000010)
     207/** End of range 1. */
     208#define MSR_GIM_HV_RANGE1_END                     MSR_GIM_HV_VP_RUNTIME
     209
     210/** Start of range 2. */
     211#define MSR_GIM_HV_RANGE2_START                   UINT32_C(0x40000020)
    200212/** Per-VM reference counter (R) */
    201213#define MSR_GIM_HV_TIME_REF_COUNT                 UINT32_C(0x40000020)
    … …  
    206218/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
    207219#define MSR_GIM_HV_APIC_FREQ                      UINT32_C(0x40000023)
     220/** End of range 2. */
     221#define MSR_GIM_HV_RANGE2_END                     MSR_GIM_HV_APIC_FREQ
     222
     223/** Start of range 3. */
     224#define MSR_GIM_HV_RANGE3_START                   UINT32_C(0x40000070)
    208225/** Access to APIC EOI (End-Of-Interrupt) register (W) */
    209226#define MSR_GIM_HV_EOI                            UINT32_C(0x40000070)
    … …  
    214231/** Enables lazy EOI processing (R/W) */
    215232#define MSR_GIM_HV_APIC_ASSIST_PAGE               UINT32_C(0x40000073)
     233/** End of range 3. */
     234#define MSR_GIM_HV_RANGE3_END                     MSR_GIM_HV_APIC_ASSIST_PAGE
     235
     236/** Start of range 4. */
     237#define MSR_GIM_HV_RANGE4_START                   UINT32_C(0x40000080)
    216238/** Control behaviour of synthetic interrupt controller (R/W) */
    217239#define MSR_GIM_HV_SCONTROL                       UINT32_C(0x40000080)
    … …  
    224246/** End-Of-Message in synthetic interrupt parameter page (W) */
    225247#define MSR_GIM_HV_EOM                            UINT32_C(0x40000084)
     248/** End of range 4. */
     249#define MSR_GIM_HV_RANGE4_END                     MSR_GIM_HV_EOM
     250
     251/** Start of range 5. */
     252#define MSR_GIM_HV_RANGE5_START                   UINT32_C(0x40000090)
    226253/** Configures synthetic interrupt source 0 (R/W) */
    227254#define MSR_GIM_HV_SINT0                          UINT32_C(0x40000090)
    … …  
    256283/** Configures synthetic interrupt source 15 (R/W) */
    257284#define MSR_GIM_HV_SINT15                         UINT32_C(0x4000009F)
     285/** End of range 5. */
     286#define MSR_GIM_HV_RANGE5_END                     MSR_GIM_HV_SINT15
     287
     288/** Start of range 6. */
     289#define MSR_GIM_HV_RANGE6_START                   UINT32_C(0x400000B0)
    258290/** Configures register for synthetic timer 0 (R/W) */
    259291#define MSR_GIM_HV_STIMER0_CONFIG                 UINT32_C(0x400000B0)
    … …  
    272304/** Expiration time or period for synthetic timer 3 (R/W) */
    273305#define MSR_GIM_HV_STIMER3_COUNT                  UINT32_C(0x400000B7)
     306/** End of range 6. */
     307#define MSR_GIM_HV_RANGE6_END                     MSR_GIM_HV_STIMER3_COUNT
     308
     309/** Start of range 7. */
     310#define MSR_GIM_HV_RANGE7_START                   UINT32_C(0x400000C1)
    274311/** Trigger to transition to power state C1 (R) */
    275312#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1         UINT32_C(0x400000C1)
    … …  
    278315/** Trigger to transition to power state C3 (R) */
    279316#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3         UINT32_C(0x400000C3)
     317/** End of range 7. */
     318#define MSR_GIM_HV_RANGE7_END                     MSR_GIM_HV_POWER_STATE_TRIGGER_C3
     319
     320/** Start of range 8. */
     321#define MSR_GIM_HV_RANGE8_START                   UINT32_C(0x400000D1)
    280322/** Configure the recipe for power state transitions to C1 (R/W) */
    281323#define MSR_GIM_HV_POWER_STATE_CONFIG_C1          UINT32_C(0x400000D1)
    … …  
    284326/** Configure the recipe for power state transitions to C3 (R/W) */
    285327#define MSR_GIM_HV_POWER_STATE_CONFIG_C3          UINT32_C(0x400000D3)
     328/** End of range 8. */
     329#define MSR_GIM_HV_RANGE8_END                     MSR_GIM_HV_POWER_STATE_CONFIG_C3
     330
     331/** Start of range 9. */
     332#define MSR_GIM_HV_RANGE9_START                   UINT32_C(0x400000E0)
    286333/** Map the guest's retail partition stats page (R/W) */
    287334#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE         UINT32_C(0x400000E0)
    … …  
    292339/** Map the guest's internal VP stats page (R/W) */
    293340#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE         UINT32_C(0x400000E3)
     341/** End of range 9. */
     342#define MSR_GIM_HV_RANGE9_END                     MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
     343
     344/** Start of range 10. */
     345#define MSR_GIM_HV_RANGE10_START                  UINT32_C(0x400000F0)
    294346/** Trigger the guest's transition to idle power state (R) */
    295347#define MSR_GIM_HV_GUEST_IDLE                     UINT32_C(0x400000F0)
    … …  
    304356/** Synthetic debug pending buffer. */
    305357#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER     UINT32_C(0x400000F5)
     358/** End of range 10. */
     359#define MSR_GIM_HV_RANGE10_END                    MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
     360
     361/** Start of range 11. */
     362#define MSR_GIM_HV_RANGE11_START                  UINT32_C(0x40000100)
    306363/** Guest crash MSR 0. */
    307364#define MSR_GIM_HV_CRASH_P0                       UINT32_C(0x40000100)
    … …  
    316373/** Guest crash control. */
    317374#define MSR_GIM_HV_CRASH_CTL                      UINT32_C(0x40000105)
     375/** End of range 11. */
     376#define MSR_GIM_HV_RANGE11_END                    MSR_GIM_HV_CRASH_CTL
    318377/** @} */
    319378
     379AssertCompile(MSR_GIM_HV_RANGE0_START  <= MSR_GIM_HV_RANGE0_END);
     380AssertCompile(MSR_GIM_HV_RANGE1_START  <= MSR_GIM_HV_RANGE1_END);
     381AssertCompile(MSR_GIM_HV_RANGE2_START  <= MSR_GIM_HV_RANGE2_END);
     382AssertCompile(MSR_GIM_HV_RANGE3_START  <= MSR_GIM_HV_RANGE3_END);
     383AssertCompile(MSR_GIM_HV_RANGE4_START  <= MSR_GIM_HV_RANGE4_END);
     384AssertCompile(MSR_GIM_HV_RANGE5_START  <= MSR_GIM_HV_RANGE5_END);
     385AssertCompile(MSR_GIM_HV_RANGE6_START  <= MSR_GIM_HV_RANGE6_END);
     386AssertCompile(MSR_GIM_HV_RANGE7_START  <= MSR_GIM_HV_RANGE7_END);
     387AssertCompile(MSR_GIM_HV_RANGE8_START  <= MSR_GIM_HV_RANGE8_END);
     388AssertCompile(MSR_GIM_HV_RANGE9_START  <= MSR_GIM_HV_RANGE9_END);
     389AssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
     390AssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
    320391
    321392RT_C_DECLS_BEGIN
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