Changeset 51421 in vbox

Timestamp:

May 27, 2014 10:59:35 AM (11 years ago)

Author:

vboxsync

Message:

VMM/HMSVMR0: Check single-step only on success and update HMCPU force-flags when continuing in ring-0.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -4416 +4416 @@
         {
             rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
-            if (RT_UNLIKELY(rc != VINF_SUCCESS))
+            if (RT_LIKELY(rc == VINF_SUCCESS))
+                HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);     /* RIP updated by EMInterpretInstruction(). */
+            else
                 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
-            /* RIP updated by EMInterpretInstruction(). */
-            HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
-        }
-
-        /* If this is an X2APIC WRMSR access, update the APIC state as well. */
-        if (   pCtx->ecx >= MSR_IA32_X2APIC_START
-            && pCtx->ecx <= MSR_IA32_X2APIC_END)
-        {
-            /*
-             * We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
-             * virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
-             * EMInterpretWrmsr() changes it.
-             */
-            HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
-        }
-        else if (pCtx->ecx == MSR_K6_EFER)
-            HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
-        else if (pCtx->ecx == MSR_IA32_TSC)
-            pSvmTransient->fUpdateTscOffsetting = true;
+        }
+
+        if (rc == VINF_SUCCESS)
+        {
+            /* If this is an X2APIC WRMSR access, update the APIC state as well. */
+            if (   pCtx->ecx >= MSR_IA32_X2APIC_START
+                && pCtx->ecx <= MSR_IA32_X2APIC_END)
+            {
+                /*
+                 * We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
+                 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
+                 * EMInterpretWrmsr() changes it.
+                 */
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
+            }
+            else if (pCtx->ecx == MSR_K6_EFER)
+                HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
+            else if (pCtx->ecx == MSR_IA32_TSC)
+                pSvmTransient->fUpdateTscOffsetting = true;
+        }
     }
     else