VirtualBox

Changeset 51517 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Jun 4, 2014 4:52:30 AM (11 years ago)
Author:
vboxsync
Message:

VMM: Doxygen comment nits.

Location:
trunk/src/VBox/VMM
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp

    r48728 r51517  
    24772477 * the VM, in which case we'll drop the base memory pages.  Presently we will
    24782478 * make no attempt to preserve anything that happens to be present in the base
    2479  * memory that is replaced, this is of course incorrectly but it's too much
     2479 * memory that is replaced, this is of course incorrect but it's too much
    24802480 * effort.
    24812481 *
    … …  
    27472747 * @param   pVM             Pointer to the VM.
    27482748 * @param   pDevIns         The device instance owning the region.
     2749 * @param   iRegion         The index of the registered region.
     2750 * @param   GCPhys          The guest-physical address to be remapped.
    27492751 */
    27502752VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)

  • trunk/src/VBox/VMM/VMMR3/STAM.cpp

    r48235 r51517  
    55
    66/*
    7  * Copyright (C) 2006-2013 Oracle Corporation
     7 * Copyright (C) 2006-2014 Oracle Corporation
    88 *
    99 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    16551655        if (!fGVMMMatched)
    16561656        {
    1657             /** @todo match cpu leaves some rainy day.  */
     1657            /** @todo match cpu leaves some rainy day. */
    16581658        }
    16591659
    … …  
    26632663    if (!fUpdate)
    26642664    {
    2665         /** @todo check the cpu leaves - rainy day.   */
     2665        /** @todo check the cpu leaves - rainy day. */
    26662666    }
    26672667    if (fUpdate)

  • trunk/src/VBox/VMM/VMMRZ/PGMRZDynMap.cpp

    r45618 r51517  
    55
    66/*
    7  * Copyright (C) 2008-2012 Oracle Corporation
     7 * Copyright (C) 2008-2014 Oracle Corporation
    88 *
    99 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    5454# define PGMR0DYNMAP_PAGES_PER_CPU          256
    5555/** The minimum number of pages we reserve per CPU.
    56  * This must be equal or larger than the autoset size.  */
     56 * This must be equal or larger than the autoset size. */
    5757# define PGMR0DYNMAP_PAGES_PER_CPU_MIN      64
    5858/** Calcs the overload threshold (safety margin).  Current set at 50%. */
    5959# define PGMR0DYNMAP_CALC_OVERLOAD(cPages)  ((cPages) / 2)
    6060/** The number of guard pages.
    61  * @remarks Never do tuning of the hashing or whatnot with a strict build!  */
     61 * @remarks Never do tuning of the hashing or whatnot with a strict build! */
    6262# if defined(VBOX_STRICT)
    6363#  define PGMR0DYNMAP_GUARD_PAGES           1
    … …  
    7373/** Define this to just clear the present bit on guard pages.
    7474 * The alternative is to replace the entire PTE with an bad not-present
    75  * PTE. Either way, XNU will screw us. :-/   */
     75 * PTE. Either way, XNU will screw us. :-/ */
    7676# define PGMR0DYNMAP_GUARD_NP
    7777#endif
    … …  
    200200    /** The physical address of the currently mapped page.
    201201     * This is duplicate for three reasons: cache locality, cache policy of the PT
    202      * mappings and sanity checks.   */
     202     * mappings and sanity checks. */
    203203    RTHCPHYS                    HCPhys;
    204204    /** Pointer to the page. */
    … …  
    220220} PGMR0DYNMAPENTRY;
    221221/** Pointer a mapping cache entry for the ring-0.
    222  * @sa PPGMRZDYNMAPENTRY, PPGMRCDYNMAPENTRY,  */
     222 * @sa PPGMRZDYNMAPENTRY, PPGMRCDYNMAPENTRY, */
    223223typedef PGMR0DYNMAPENTRY *PPGMR0DYNMAPENTRY;
    224224
    … …  
    240240    /** Spinlock serializing the normal operation of the cache. */
    241241    RTSPINLOCK                  hSpinlock;
    242     /** Array for tracking and managing the pages.  */
     242    /** Array for tracking and managing the pages. */
    243243    PPGMR0DYNMAPENTRY           paPages;
    244244    /** The cache size given as a number of pages. */
    … …  
    298298
    299299/** Mapping cache entry for the current context.
    300  * @sa PGMR0DYNMAPENTRY, PGMRCDYNMAPENTRY  */
     300 * @sa PGMR0DYNMAPENTRY, PGMRCDYNMAPENTRY */
    301301typedef CTX_MID(PGM,DYNMAPENTRY) PGMRZDYNMAPENTRY;
    302302/** Pointer a mapping cache entry for the current context.
    303  * @sa PGMR0DYNMAPENTRY, PGMRCDYNMAPENTRY  */
     303 * @sa PGMR0DYNMAPENTRY, PGMRCDYNMAPENTRY */
    304304typedef PGMRZDYNMAPENTRY *PPGMRZDYNMAPENTRY;
    305305
    306306/** Pointer to the mapping cache instance for the current context.
    307  * @sa PGMR0DYNMAP, PGMRCDYNMAP  */
     307 * @sa PGMR0DYNMAP, PGMRCDYNMAP */
    308308typedef CTX_MID(PGM,DYNMAP) *PPGMRZDYNMAP;
    309309

  • trunk/src/VBox/VMM/include/CPUMInternal.h

    r51301 r51517  
    55
    66/*
    7  * Copyright (C) 2006-2012 Oracle Corporation
     7 * Copyright (C) 2006-2014 Oracle Corporation
    88 *
    99 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    9797#define CPUM_SYNC_DEBUG_REGS_GUEST      RT_BIT(17)
    9898/** Sync the debug state on next entry (32->64 switcher only).
    99  * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers.  */
     99 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
    100100#define CPUM_SYNC_DEBUG_REGS_HYPER      RT_BIT(18)
    101101/** Host CPU requires fxsave/fxrstor leaky bit handling. */
    … …  
    129129    /** The maximum physical address with of the CPU. */
    130130    uint8_t         cMaxPhysAddrWidth;
    131     /** Alignment padding.  */
     131    /** Alignment padding. */
    132132    uint8_t         abPadding[3];
    133133
    134     /** Supports MSRs.  */
     134    /** Supports MSRs. */
    135135    uint32_t        fMsr : 1;
    136136    /** Supports the page size extension (4/2 MB pages). */
    … …  
    139139     *  4GB). */
    140140    uint32_t        fPse36 : 1;
    141     /** Supports physical address extension (PAE).  */
     141    /** Supports physical address extension (PAE). */
    142142    uint32_t        fPae : 1;
    143143    /** Page attribute table (PAT) support (page level cache control). */
    … …  
    156156    uint32_t        fMonitorMWait : 1;
    157157
    158     /** AMD64: Supports long mode.  */
     158    /** AMD64: Supports long mode. */
    159159    uint32_t        fLongMode : 1;
    160160    /** AMD64: SYSCALL/SYSRET support. */
    … …  
    169169    /** Indicates that FPU instruction and data pointers may leak.
    170170     * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
    171      * is only saved and restored if an exception is pending.   */
     171     * is only saved and restored if an exception is pending. */
    172172    uint32_t        fLeakyFxSR : 1;
    173173
    174     /** Alignment padding.  */
     174    /** Alignment padding. */
    175175    uint32_t        fPadding : 9;
    176176
    … …  
    200200     *  Set to cCpuIdLeaves if none present. */
    201201    uint32_t                    iFirstExtCpuIdLeaf;
    202     /** Alignment padding.  */
     202    /** Alignment padding. */
    203203    uint32_t                    uPadding;
    204204    /** How to handle unknown CPUID leaves. */
    … …  
    438438    } CR4;
    439439
    440     /** The (more) portable CPUID level.  */
     440    /** The (more) portable CPUID level. */
    441441    uint8_t                 u8PortableCpuIdLevel;
    442442    /** Indicates that a state restore is pending.

  • trunk/src/VBox/VMM/include/PGMInternal.h

    r47786 r51517  
    55
    66/*
    7  * Copyright (C) 2006-2013 Oracle Corporation
     7 * Copyright (C) 2006-2014 Oracle Corporation
    88 *
    99 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    494494#endif
    495495
    496 /** Pointer to a shadow PAE PTE.  */
     496/** Pointer to a shadow PAE PTE. */
    497497typedef PGMSHWPTEPAE       *PPGMSHWPTEPAE;
    498 /** Pointer to a const shadow PAE PTE.  */
     498/** Pointer to a const shadow PAE PTE. */
    499499typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
    500500
    501 /** Pointer to a shadow PAE page table.  */
     501/** Pointer to a shadow PAE page table. */
    502502typedef PGMSHWPTPAE        *PPGMSHWPTPAE;
    503 /** Pointer to a const shadow PAE page table.  */
     503/** Pointer to a const shadow PAE page table. */
    504504typedef PGMSHWPTPAE const  *PCPGMSHWPTPAE;
    505 /** @}  */
     505/** @} */
    506506
    507507
    … …  
    674674    STAMPROFILE                         Stat;
    675675#endif
    676     /** Array of cached physical addresses for the monitored ranged.  */
     676    /** Array of cached physical addresses for the monitored ranged. */
    677677    PGMPHYS2VIRTHANDLER                 aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
    678678} PGMVIRTHANDLER;
    … …  
    13211321
    13221322#if 0
    1323 /** Enables sanity checking of write monitoring using CRC-32.  */
     1323/** Enables sanity checking of write monitoring using CRC-32. */
    13241324# define PGMLIVESAVERAMPAGE_WITH_CRC32
    13251325#endif
    … …  
    13471347    /** Whether the page is/was write monitored earlier in this pass. */
    13481348    uint32_t    fWriteMonitoredJustNow : 1;
    1349     /** Bits reserved for future use.  */
     1349    /** Bits reserved for future use. */
    13501350    uint32_t    u2Reserved : 2;
    13511351#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
    1352     /** CRC-32 for the page. This is for internal consistency checks.  */
     1352    /** CRC-32 for the page. This is for internal consistency checks. */
    13531353    uint32_t    u32Crc;
    13541354#endif
    … …  
    15711571    /** CRC-32 for the first half of the page.
    15721572     * This is used together with u32CrcH2 to quickly detect changes in the page
    1573      * during the non-final passes.  */
     1573     * during the non-final passes. */
    15741574    uint32_t    u32CrcH1;
    15751575    /** CRC-32 for the second half of the page. */
    … …  
    16341634/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
    16351635#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage)   ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
    1636 /** Gets the MMIO2 range ID from an MMIO2 page ID.  */
     1636/** Gets the MMIO2 range ID from an MMIO2 page ID. */
    16371637#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage)     ( (uint8_t)((a_idPage) >> 24) )
    1638 /** Gets the MMIO2 page index from an MMIO2 page ID.  */
     1638/** Gets the MMIO2 page index from an MMIO2 page ID. */
    16391639#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage)          ( ((a_idPage) & UINT32_C(0x00ffffff)) )
    16401640/** @} */
    … …  
    18171817    /** The physical address of the currently mapped page.
    18181818     * This is duplicate for three reasons: cache locality, cache policy of the PT
    1819      * mappings and sanity checks.   */
     1819     * mappings and sanity checks. */
    18201820    RTHCPHYS                    HCPhys;
    18211821    /** Pointer to the page. */
    … …  
    18511851    /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
    18521852    uint32_t                        u32Magic;
    1853     /** Array for tracking and managing the pages.  */
     1853    /** Array for tracking and managing the pages. */
    18541854    RCPTRTYPE(PPGMRCDYNMAPENTRY)    paPages;
    18551855    /** The cache size given as a number of pages. */
    … …  
    18971897     * The max is UINT16_MAX - 1. */
    18981898    uint16_t                    cInlinedRefs;
    1899     /** Unreferences.  */
     1899    /** Unreferences. */
    19001900    uint16_t                    cUnrefs;
    19011901
    … …  
    20712071    PGMPOOLKIND_FREE,
    20722072
    2073     /** Shw: 32-bit page table;     Gst: no paging  */
     2073    /** Shw: 32-bit page table;     Gst: no paging. */
    20742074    PGMPOOLKIND_32BIT_PT_FOR_PHYS,
    2075     /** Shw: 32-bit page table;     Gst: 32-bit page table.  */
     2075    /** Shw: 32-bit page table;     Gst: 32-bit page table. */
    20762076    PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
    2077     /** Shw: 32-bit page table;     Gst: 4MB page.  */
     2077    /** Shw: 32-bit page table;     Gst: 4MB page. */
    20782078    PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
    2079     /** Shw: PAE page table;        Gst: no paging  */
     2079    /** Shw: PAE page table;        Gst: no paging. */
    20802080    PGMPOOLKIND_PAE_PT_FOR_PHYS,
    20812081    /** Shw: PAE page table;        Gst: 32-bit page table. */
    20822082    PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
    2083     /** Shw: PAE page table;        Gst: Half of a 4MB page.  */
     2083    /** Shw: PAE page table;        Gst: Half of a 4MB page. */
    20842084    PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
    20852085    /** Shw: PAE page table;        Gst: PAE page table. */
    20862086    PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
    2087     /** Shw: PAE page table;        Gst: 2MB page.  */
     2087    /** Shw: PAE page table;        Gst: 2MB page. */
    20882088    PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
    20892089
    … …  
    21142114    /** Shw: 64-bit page directory pointer table;   Gst: 64-bit page directory pointer table. */
    21152115    PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
    2116     /** Shw: 64-bit page directory pointer table;   Gst: no paging  */
     2116    /** Shw: 64-bit page directory pointer table;   Gst: no paging. */
    21172117    PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
    21182118    /** Shw: 64-bit page directory table;           Gst: 64-bit page directory table. */
    21192119    PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
    2120     /** Shw: 64-bit page directory table;           Gst: no paging  */
     2120    /** Shw: 64-bit page directory table;           Gst: no paging. */
    21212121    PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
    21222122
    … …  
    21242124    PGMPOOLKIND_64BIT_PML4,
    21252125
    2126     /** Shw: EPT page directory pointer table;      Gst: no paging  */
     2126    /** Shw: EPT page directory pointer table;      Gst: no paging. */
    21272127    PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
    2128     /** Shw: EPT page directory table;              Gst: no paging  */
     2128    /** Shw: EPT page directory table;              Gst: no paging. */
    21292129    PGMPOOLKIND_EPT_PD_FOR_PHYS,
    2130     /** Shw: EPT page table;                        Gst: no paging  */
     2130    /** Shw: EPT page table;                        Gst: no paging. */
    21312131    PGMPOOLKIND_EPT_PT_FOR_PHYS,
    21322132
    … …  
    22312231    RTGCPTR             GCPtrLastAccessHandlerFault;
    22322232    uint64_t            cLastAccessHandler;
    2233     /** @}  */
     2233    /** @} */
    22342234    /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
    22352235    uint32_t volatile   cLocked;
    … …  
    22702270    /** The VM handle - RC Ptr. */
    22712271    PVMRC                       pVMRC;
    2272     /** The max pool size. This includes the special IDs.  */
     2272    /** The max pool size. This includes the special IDs. */
    22732273    uint16_t                    cMaxPages;
    22742274    /** The current pool size. */
    … …  
    26402640
    26412641    /** The guest physical address that is the result of the walk.
    2642      * @remarks only valid if fSucceeded is set.  */
     2642     * @remarks only valid if fSucceeded is set. */
    26432643    RTGCPHYS        GCPhys;
    26442644
    … …  
    31163116    bool                            fPhysWriteMonitoringEngaged;
    31173117    /** Set if the CPU has less than 52-bit physical address width.
    3118      * This is used  */
     3118     * This is used */
    31193119    bool                            fLessThan52PhysicalAddressBits;
    31203120    /** Set when nested paging is active.
    … …  
    31603160    RTGCPHYS                        GCPhys4MBPSEMask;
    31613161    /** Mask containing the invalid bits of a guest physical address.
    3162      * @remarks this does not stop at bit 52.  */
     3162     * @remarks this does not stop at bit 52. */
    31633163    RTGCPHYS                        GCPhysInvAddrMask;
    31643164
    … …  
    31903190    R3PTRTYPE(PPGMMODEDATA)         paModeData;
    31913191    RTR3PTR                         R3PtrAlignment0;
    3192     /** MMIO2 lookup array for ring-3.  Indexed by idMmio2 minus 1.  */
     3192    /** MMIO2 lookup array for ring-3.  Indexed by idMmio2 minus 1. */
    31933193    R3PTRTYPE(PPGMMMIO2RANGE)       apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
    31943194
    … …  
    32113211    R0PTRTYPE(PPGMROMRANGE)         pRomRangesR0;
    32123212    RTR0PTR                         R0PtrAlignment0;
    3213     /** MMIO2 lookup array for ring-3.  Indexed by idMmio2 minus 1.  */
     3213    /** MMIO2 lookup array for ring-3.  Indexed by idMmio2 minus 1. */
    32143214    R0PTRTYPE(PPGMMMIO2RANGE)       apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
    32153215
    … …  
    32793279    /** The address of the raw-mode context mapping cache. */
    32803280    RCPTRTYPE(PPGMRCDYNMAP)         pRCDynMap;
    3281     /** The address of the ring-0 mapping cache if we're making use of it.  */
     3281    /** The address of the ring-0 mapping cache if we're making use of it. */
    32823282    RTR0PTR                         pvR0DynMapUsed;
    32833283
    … …  
    32863286    uint32_t                        cDeprecatedPageLocks;
    32873287#if HC_ARCH_BITS == 64
    3288     /** Alignment padding.  */
     3288    /** Alignment padding. */
    32893289    uint32_t                        u32Alignment2;
    32903290#endif
    … …  
    33943394        struct
    33953395        {
    3396             /** The number of ready pages.  */
     3396            /** The number of ready pages. */
    33973397            uint32_t                cReadyPages;
    33983398            /** The number of dirty pages. */
    33993399            uint32_t                cDirtyPages;
    3400             /** The number of ready zero pages.  */
     3400            /** The number of ready zero pages. */
    34013401            uint32_t                cZeroPages;
    34023402            /** The number of write monitored pages. */
    … …  
    34073407        /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
    34083408        uint32_t                    cIgnoredPages;
    3409         /** Indicates that a live save operation is active.  */
     3409        /** Indicates that a live save operation is active. */
    34103410        bool                        fActive;
    34113411        /** Padding. */
    … …  
    34223422         * link speed so we can decide when we're done.  It is reset after the first
    34233423         * 7 passes so the speed estimate doesn't get inflated by the initial set of
    3424          * zero pages.   */
     3424         * zero pages. */
    34253425        uint64_t                    cSavedPages;
    34263426        /** The nanosecond timestamp when cSavedPages was 0. */
    … …  
    34763476    RCPTRTYPE(PGMSTATS *)           pStatsRC;
    34773477    RTRCPTR                         RCPtrAlignment;
    3478     /** @}  */
     3478    /** @} */
    34793479#endif
    34803480} PGM;
    … …  
    38413841    /** Mask containing the big page PDE bits that we shadow in the PTE. */
    38423842    uint64_t                        fGst64ShadowedBigPde4PteMask;
    3843     /** @}  */
     3843    /** @} */
    38443844
    38453845    /** Pointer to the page of the current active CR3 - R3 Ptr. */
    … …  
    39433943    /** @} */
    39443944
    3945 #ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap.  */
     3945#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
    39463946    /** @name Statistics
    39473947     * @{ */
    … …  
    39583958    /** Alignment padding. */
    39593959    RTR3PTR                         pPaddingR3;
    3960     /** @}  */
     3960    /** @} */
    39613961#endif /* VBOX_WITH_STATISTICS */
    39623962} PGMCPU;
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