VirtualBox

Changeset 52970 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Oct 7, 2014 8:56:48 AM (11 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
96416
Message:

Devices/Graphics: added original vmsvga and vmsvga_glext headers (2009-04)

Location:
trunk/src/VBox/Devices/Graphics
Files:
7 added
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Graphics/vmsvga/svga3d_caps.h

    r49983 r52970  
     1/**********************************************************
     2 * Copyright 2007-2009 VMware, Inc.  All rights reserved.
     3 *
     4 * Permission is hereby granted, free of charge, to any person
     5 * obtaining a copy of this software and associated documentation
     6 * files (the "Software"), to deal in the Software without
     7 * restriction, including without limitation the rights to use, copy,
     8 * modify, merge, publish, distribute, sublicense, and/or sell copies
     9 * of the Software, and to permit persons to whom the Software is
     10 * furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be
     13 * included in all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     22 * SOFTWARE.
     23 *
     24 **********************************************************/
     25
    126/*
    2  * VMware SVGA II 3D capability definitions
     27 * svga3d_caps.h --
     28 *
     29 *       Definitions for SVGA3D hardware capabilities.  Capabilities
     30 *       are used to query for optional rendering features during
     31 *       driver initialization. The capability data is stored as very
     32 *       basic key/value dictionary within the "FIFO register" memory
     33 *       area at the beginning of BAR2.
     34 *
     35 *       Note that these definitions are only for 3D capabilities.
     36 *       The SVGA device also has "device capabilities" and "FIFO
     37 *       capabilities", which are non-3D-specific and are stored as
     38 *       bitfields rather than key/value pairs.
    339 */
    440
    … …  
    642#define _SVGA3D_CAPS_H_
    743
     44#define SVGA_FIFO_3D_CAPS_SIZE   (SVGA_FIFO_3D_CAPS_LAST - \
     45                                  SVGA_FIFO_3D_CAPS + 1)
    846
    947
    10 #endif /* _SVGA3D_CAPS_H_ */
     48/*
     49 * SVGA3dCapsRecordType
     50 *
     51 *    Record types that can be found in the caps block.
     52 *    Related record types are grouped together numerically so that
     53 *    SVGA3dCaps_FindRecord() can be applied on a range of record
     54 *    types.
     55 */
    1156
     57typedef enum {
     58   SVGA3DCAPS_RECORD_UNKNOWN        = 0,
     59   SVGA3DCAPS_RECORD_DEVCAPS_MIN    = 0x100,
     60   SVGA3DCAPS_RECORD_DEVCAPS        = 0x100,
     61   SVGA3DCAPS_RECORD_DEVCAPS_MAX    = 0x1ff
     62} SVGA3dCapsRecordType;
     63
     64
     65/*
     66 * SVGA3dCapsRecordHeader
     67 *
     68 *    Header field leading each caps block record. Contains the offset (in
     69 *    register words, NOT bytes) to the next caps block record (or the end
     70 *    of caps block records which will be a zero word) and the record type
     71 *    as defined above.
     72 */
     73
     74typedef
     75struct SVGA3dCapsRecordHeader {
     76   uint32_t length;
     77   SVGA3dCapsRecordType type;
     78}
     79SVGA3dCapsRecordHeader;
     80
     81
     82/*
     83 * SVGA3dCapsRecord
     84 *
     85 *    Caps block record; "data" is a placeholder for the actual data structure
     86 *    contained within the record; for example a record containing a FOOBAR
     87 *    structure would be of size "sizeof(SVGA3dCapsRecordHeader) +
     88 *    sizeof(FOOBAR)".
     89 */
     90
     91typedef
     92struct SVGA3dCapsRecord {
     93   SVGA3dCapsRecordHeader header;
     94   uint32_t data[1];
     95}
     96SVGA3dCapsRecord;
     97
     98
     99typedef uint32_t SVGA3dCapPair[2];
     100
     101
     102/*
     103 *----------------------------------------------------------------------
     104 *
     105 * SVGA3dCaps_FindRecord
     106 *
     107 *    Finds the record with the highest-valued type within the given range
     108 *    in the caps block.
     109 *
     110 *    Result: pointer to found record, or NULL if not found.
     111 *
     112 *----------------------------------------------------------------------
     113 */
     114#if 0
     115static INLINE SVGA3dCapsRecord *
     116SVGA3dCaps_FindRecord(const uint32_t *capsBlock,
     117                      SVGA3dCapsRecordType recordTypeMin,
     118                      SVGA3dCapsRecordType recordTypeMax)
     119{
     120   SVGA3dCapsRecord *record, *found = NULL;
     121   uint32_t offset;
     122
     123   /*
     124    * Search linearly through the caps block records for the specified type.
     125    */
     126   for (offset = 0; capsBlock[offset] != 0; offset += capsBlock[offset]) {
     127      record = (SVGA3dCapsRecord *) (capsBlock + offset);
     128      if ((record->header.type >= recordTypeMin) &&
     129          (record->header.type <= recordTypeMax) &&
     130          (!found || (record->header.type > found->header.type))) {
     131         found = record;
     132      }
     133   }
     134
     135   return found;
     136}
     137#endif
     138
     139#endif // _SVGA3D_CAPS_H_

  • trunk/src/VBox/Devices/Graphics/vmsvga/svga3d_reg.h

    r49983 r52970  
    1 /*
    2  * VMware SVGA II 3D definitions
     1/**********************************************************
     2 * Copyright 1998-2009 VMware, Inc.  All rights reserved.
     3 *
     4 * Permission is hereby granted, free of charge, to any person
     5 * obtaining a copy of this software and associated documentation
     6 * files (the "Software"), to deal in the Software without
     7 * restriction, including without limitation the rights to use, copy,
     8 * modify, merge, publish, distribute, sublicense, and/or sell copies
     9 * of the Software, and to permit persons to whom the Software is
     10 * furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be
     13 * included in all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     22 * SOFTWARE.
     23 *
     24 **********************************************************/
     25
     26/*
     27 * svga3d_reg.h --
     28 *
     29 *       SVGA 3D hardware definitions
    330 */
    431
    … …  
    633#define _SVGA3D_REG_H_
    734
     35#include "svga_reg.h"
     36
     37
     38/*
     39 * 3D Hardware Version
     40 *
     41 *   The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
     42 *   register.   Is set by the host and read by the guest.  This lets
     43 *   us make new guest drivers which are backwards-compatible with old
     44 *   SVGA hardware revisions.  It does not let us support old guest
     45 *   drivers.  Good enough for now.
     46 *
     47 */
     48
     49#define SVGA3D_MAKE_HWVERSION(major, minor)      (((major) << 16) | ((minor) & 0xFF))
     50#define SVGA3D_MAJOR_HWVERSION(version)          ((version) >> 16)
     51#define SVGA3D_MINOR_HWVERSION(version)          ((version) & 0xFF)
     52
     53typedef enum {
     54   SVGA3D_HWVERSION_WS5_RC1   = SVGA3D_MAKE_HWVERSION(0, 1),
     55   SVGA3D_HWVERSION_WS5_RC2   = SVGA3D_MAKE_HWVERSION(0, 2),
     56   SVGA3D_HWVERSION_WS51_RC1  = SVGA3D_MAKE_HWVERSION(0, 3),
     57   SVGA3D_HWVERSION_WS6_B1    = SVGA3D_MAKE_HWVERSION(1, 1),
     58   SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
     59   SVGA3D_HWVERSION_WS65_B1   = SVGA3D_MAKE_HWVERSION(2, 0),
     60   SVGA3D_HWVERSION_WS8_B1    = SVGA3D_MAKE_HWVERSION(2, 1),
     61   SVGA3D_HWVERSION_CURRENT   = SVGA3D_HWVERSION_WS8_B1
     62} SVGA3dHardwareVersion;
     63
     64/*
     65 * Generic Types
     66 */
     67
     68typedef uint32_t SVGA3dBool; /* 32-bit Bool definition */
     69#define SVGA3D_NUM_CLIPPLANES                   6
     70#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS  8
     71#define SVGA3D_MAX_CONTEXT_IDS                  256
     72#define SVGA3D_MAX_SURFACE_IDS                  (32 * 1024)
     73
     74/*
     75 * Surface formats.
     76 *
     77 * If you modify this list, be sure to keep GLUtil.c in sync. It
     78 * includes the internal format definition of each surface in
     79 * GLUtil_ConvertSurfaceFormat, and it contains a table of
     80 * human-readable names in GLUtil_GetFormatName.
     81 */
     82
     83typedef enum SVGA3dSurfaceFormat {
     84   SVGA3D_FORMAT_INVALID               = 0,
     85
     86   SVGA3D_X8R8G8B8                     = 1,
     87   SVGA3D_A8R8G8B8                     = 2,
     88
     89   SVGA3D_R5G6B5                       = 3,
     90   SVGA3D_X1R5G5B5                     = 4,
     91   SVGA3D_A1R5G5B5                     = 5,
     92   SVGA3D_A4R4G4B4                     = 6,
     93
     94   SVGA3D_Z_D32                        = 7,
     95   SVGA3D_Z_D16                        = 8,
     96   SVGA3D_Z_D24S8                      = 9,
     97   SVGA3D_Z_D15S1                      = 10,
     98
     99   SVGA3D_LUMINANCE8                   = 11,
     100   SVGA3D_LUMINANCE4_ALPHA4            = 12,
     101   SVGA3D_LUMINANCE16                  = 13,
     102   SVGA3D_LUMINANCE8_ALPHA8            = 14,
     103
     104   SVGA3D_DXT1                         = 15,
     105   SVGA3D_DXT2                         = 16,
     106   SVGA3D_DXT3                         = 17,
     107   SVGA3D_DXT4                         = 18,
     108   SVGA3D_DXT5                         = 19,
     109
     110   SVGA3D_BUMPU8V8                     = 20,
     111   SVGA3D_BUMPL6V5U5                   = 21,
     112   SVGA3D_BUMPX8L8V8U8                 = 22,
     113   SVGA3D_BUMPL8V8U8                   = 23,
     114
     115   SVGA3D_ARGB_S10E5                   = 24,   /* 16-bit floating-point ARGB */
     116   SVGA3D_ARGB_S23E8                   = 25,   /* 32-bit floating-point ARGB */
     117
     118   SVGA3D_A2R10G10B10                  = 26,
     119
     120   /* signed formats */
     121   SVGA3D_V8U8                         = 27,
     122   SVGA3D_Q8W8V8U8                     = 28,
     123   SVGA3D_CxV8U8                       = 29,
     124
     125   /* mixed formats */
     126   SVGA3D_X8L8V8U8                     = 30,
     127   SVGA3D_A2W10V10U10                  = 31,
     128
     129   SVGA3D_ALPHA8                       = 32,
     130
     131   /* Single- and dual-component floating point formats */
     132   SVGA3D_R_S10E5                      = 33,
     133   SVGA3D_R_S23E8                      = 34,
     134   SVGA3D_RG_S10E5                     = 35,
     135   SVGA3D_RG_S23E8                     = 36,
     136
     137   /*
     138    * Any surface can be used as a buffer object, but SVGA3D_BUFFER is
     139    * the most efficient format to use when creating new surfaces
     140    * expressly for index or vertex data.
     141    */
     142
     143   SVGA3D_BUFFER                       = 37,
     144
     145   SVGA3D_Z_D24X8                      = 38,
     146
     147   SVGA3D_V16U16                       = 39,
     148
     149   SVGA3D_G16R16                       = 40,
     150   SVGA3D_A16B16G16R16                 = 41,
     151
     152   /* Packed Video formats */
     153   SVGA3D_UYVY                         = 42,
     154   SVGA3D_YUY2                         = 43,
     155
     156   /* Planar video formats */
     157   SVGA3D_NV12                         = 44,
     158
     159   /* Video format with alpha */
     160   SVGA3D_AYUV                         = 45,
     161
     162   SVGA3D_BC4_UNORM                    = 108,
     163   SVGA3D_BC5_UNORM                    = 111,
     164
     165   /* Advanced D3D9 depth formats. */
     166   SVGA3D_Z_DF16                       = 118,
     167   SVGA3D_Z_DF24                       = 119,
     168   SVGA3D_Z_D24S8_INT                  = 120,
     169
     170   SVGA3D_FORMAT_MAX
     171} SVGA3dSurfaceFormat;
     172
     173typedef uint32_t SVGA3dColor; /* a, r, g, b */
     174
     175/*
     176 * These match the D3DFORMAT_OP definitions used by Direct3D. We need
     177 * them so that we can query the host for what the supported surface
     178 * operations are (when we're using the D3D backend, in particular),
     179 * and so we can send those operations to the guest.
     180 */
     181typedef enum {
     182   SVGA3DFORMAT_OP_TEXTURE                               = 0x00000001,
     183   SVGA3DFORMAT_OP_VOLUMETEXTURE                         = 0x00000002,
     184   SVGA3DFORMAT_OP_CUBETEXTURE                           = 0x00000004,
     185   SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET                = 0x00000008,
     186   SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET              = 0x00000010,
     187   SVGA3DFORMAT_OP_ZSTENCIL                              = 0x00000040,
     188   SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH   = 0x00000080,
     189
     190/*
     191 * This format can be used as a render target if the current display mode
     192 * is the same depth if the alpha channel is ignored. e.g. if the device
     193 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
     194 * format op list entry for A8R8G8B8 should have this cap.
     195 */
     196   SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET  = 0x00000100,
     197
     198/*
     199 * This format contains DirectDraw support (including Flip).  This flag
     200 * should not to be set on alpha formats.
     201 */
     202   SVGA3DFORMAT_OP_DISPLAYMODE                           = 0x00000400,
     203
     204/*
     205 * The rasterizer can support some level of Direct3D support in this format
     206 * and implies that the driver can create a Context in this mode (for some
     207 * render target format).  When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
     208 * flag must also be set.
     209 */
     210   SVGA3DFORMAT_OP_3DACCELERATION                        = 0x00000800,
     211
     212/*
     213 * This is set for a private format when the driver has put the bpp in
     214 * the structure.
     215 */
     216   SVGA3DFORMAT_OP_PIXELSIZE                             = 0x00001000,
     217
     218/*
     219 * Indicates that this format can be converted to any RGB format for which
     220 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
     221 */
     222   SVGA3DFORMAT_OP_CONVERT_TO_ARGB                       = 0x00002000,
     223
     224/*
     225 * Indicates that this format can be used to create offscreen plain surfaces.
     226 */
     227   SVGA3DFORMAT_OP_OFFSCREENPLAIN                        = 0x00004000,
     228
     229/*
     230 * Indicated that this format can be read as an SRGB texture (meaning that the
     231 * sampler will linearize the looked up data)
     232 */
     233   SVGA3DFORMAT_OP_SRGBREAD                              = 0x00008000,
     234
     235/*
     236 * Indicates that this format can be used in the bumpmap instructions
     237 */
     238   SVGA3DFORMAT_OP_BUMPMAP                               = 0x00010000,
     239
     240/*
     241 * Indicates that this format can be sampled by the displacement map sampler
     242 */
     243   SVGA3DFORMAT_OP_DMAP                                  = 0x00020000,
     244
     245/*
     246 * Indicates that this format cannot be used with texture filtering
     247 */
     248   SVGA3DFORMAT_OP_NOFILTER                              = 0x00040000,
     249
     250/*
     251 * Indicates that format conversions are supported to this RGB format if
     252 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
     253 */
     254   SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB                    = 0x00080000,
     255
     256/*
     257 * Indicated that this format can be written as an SRGB target (meaning that the
     258 * pixel pipe will DE-linearize data on output to format)
     259 */
     260   SVGA3DFORMAT_OP_SRGBWRITE                             = 0x00100000,
     261
     262/*
     263 * Indicates that this format cannot be used with alpha blending
     264 */
     265   SVGA3DFORMAT_OP_NOALPHABLEND                          = 0x00200000,
     266
     267/*
     268 * Indicates that the device can auto-generated sublevels for resources
     269 * of this format
     270 */
     271   SVGA3DFORMAT_OP_AUTOGENMIPMAP                         = 0x00400000,
     272
     273/*
     274 * Indicates that this format can be used by vertex texture sampler
     275 */
     276   SVGA3DFORMAT_OP_VERTEXTEXTURE                         = 0x00800000,
     277
     278/*
     279 * Indicates that this format supports neither texture coordinate wrap
     280 * modes, nor mipmapping
     281 */
     282   SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP                  = 0x01000000
     283} SVGA3dFormatOp;
     284
     285/*
     286 * This structure is a conversion of SVGA3DFORMAT_OP_*.
     287 * Entries must be located at the same position.
     288 */
     289typedef union {
     290   uint32_t value;
     291   struct {
     292      uint32_t texture : 1;
     293      uint32_t volumeTexture : 1;
     294      uint32_t cubeTexture : 1;
     295      uint32_t offscreenRenderTarget : 1;
     296      uint32_t sameFormatRenderTarget : 1;
     297      uint32_t unknown1 : 1;
     298      uint32_t zStencil : 1;
     299      uint32_t zStencilArbitraryDepth : 1;
     300      uint32_t sameFormatUpToAlpha : 1;
     301      uint32_t unknown2 : 1;
     302      uint32_t displayMode : 1;
     303      uint32_t acceleration3d : 1;
     304      uint32_t pixelSize : 1;
     305      uint32_t convertToARGB : 1;
     306      uint32_t offscreenPlain : 1;
     307      uint32_t sRGBRead : 1;
     308      uint32_t bumpMap : 1;
     309      uint32_t dmap : 1;
     310      uint32_t noFilter : 1;
     311      uint32_t memberOfGroupARGB : 1;
     312      uint32_t sRGBWrite : 1;
     313      uint32_t noAlphaBlend : 1;
     314      uint32_t autoGenMipMap : 1;
     315      uint32_t vertexTexture : 1;
     316      uint32_t noTexCoordWrapNorMip : 1;
     317   } s;
     318} SVGA3dSurfaceFormatCaps;
     319
     320/*
     321 * SVGA_3D_CMD_SETRENDERSTATE Types.  All value types
     322 * must fit in a uint32_t.
     323 */
     324
     325typedef enum {
     326   SVGA3D_RS_INVALID                   = 0,
     327   SVGA3D_RS_ZENABLE                   = 1,     /* SVGA3dBool */
     328   SVGA3D_RS_ZWRITEENABLE              = 2,     /* SVGA3dBool */
     329   SVGA3D_RS_ALPHATESTENABLE           = 3,     /* SVGA3dBool */
     330   SVGA3D_RS_DITHERENABLE              = 4,     /* SVGA3dBool */
     331   SVGA3D_RS_BLENDENABLE               = 5,     /* SVGA3dBool */
     332   SVGA3D_RS_FOGENABLE                 = 6,     /* SVGA3dBool */
     333   SVGA3D_RS_SPECULARENABLE            = 7,     /* SVGA3dBool */
     334   SVGA3D_RS_STENCILENABLE             = 8,     /* SVGA3dBool */
     335   SVGA3D_RS_LIGHTINGENABLE            = 9,     /* SVGA3dBool */
     336   SVGA3D_RS_NORMALIZENORMALS          = 10,    /* SVGA3dBool */
     337   SVGA3D_RS_POINTSPRITEENABLE         = 11,    /* SVGA3dBool */
     338   SVGA3D_RS_POINTSCALEENABLE          = 12,    /* SVGA3dBool */
     339   SVGA3D_RS_STENCILREF                = 13,    /* uint32_t */
     340   SVGA3D_RS_STENCILMASK               = 14,    /* uint32_t */
     341   SVGA3D_RS_STENCILWRITEMASK          = 15,    /* uint32_t */
     342   SVGA3D_RS_FOGSTART                  = 16,    /* float */
     343   SVGA3D_RS_FOGEND                    = 17,    /* float */
     344   SVGA3D_RS_FOGDENSITY                = 18,    /* float */
     345   SVGA3D_RS_POINTSIZE                 = 19,    /* float */
     346   SVGA3D_RS_POINTSIZEMIN              = 20,    /* float */
     347   SVGA3D_RS_POINTSIZEMAX              = 21,    /* float */
     348   SVGA3D_RS_POINTSCALE_A              = 22,    /* float */
     349   SVGA3D_RS_POINTSCALE_B              = 23,    /* float */
     350   SVGA3D_RS_POINTSCALE_C              = 24,    /* float */
     351   SVGA3D_RS_FOGCOLOR                  = 25,    /* SVGA3dColor */
     352   SVGA3D_RS_AMBIENT                   = 26,    /* SVGA3dColor */
     353   SVGA3D_RS_CLIPPLANEENABLE           = 27,    /* SVGA3dClipPlanes */
     354   SVGA3D_RS_FOGMODE                   = 28,    /* SVGA3dFogMode */
     355   SVGA3D_RS_FILLMODE                  = 29,    /* SVGA3dFillMode */
     356   SVGA3D_RS_SHADEMODE                 = 30,    /* SVGA3dShadeMode */
     357   SVGA3D_RS_LINEPATTERN               = 31,    /* SVGA3dLinePattern */
     358   SVGA3D_RS_SRCBLEND                  = 32,    /* SVGA3dBlendOp */
     359   SVGA3D_RS_DSTBLEND                  = 33,    /* SVGA3dBlendOp */
     360   SVGA3D_RS_BLENDEQUATION             = 34,    /* SVGA3dBlendEquation */
     361   SVGA3D_RS_CULLMODE                  = 35,    /* SVGA3dFace */
     362   SVGA3D_RS_ZFUNC                     = 36,    /* SVGA3dCmpFunc */
     363   SVGA3D_RS_ALPHAFUNC                 = 37,    /* SVGA3dCmpFunc */
     364   SVGA3D_RS_STENCILFUNC               = 38,    /* SVGA3dCmpFunc */
     365   SVGA3D_RS_STENCILFAIL               = 39,    /* SVGA3dStencilOp */
     366   SVGA3D_RS_STENCILZFAIL              = 40,    /* SVGA3dStencilOp */
     367   SVGA3D_RS_STENCILPASS               = 41,    /* SVGA3dStencilOp */
     368   SVGA3D_RS_ALPHAREF                  = 42,    /* float (0.0 .. 1.0) */
     369   SVGA3D_RS_FRONTWINDING              = 43,    /* SVGA3dFrontWinding */
     370   SVGA3D_RS_COORDINATETYPE            = 44,    /* SVGA3dCoordinateType */
     371   SVGA3D_RS_ZBIAS                     = 45,    /* float */
     372   SVGA3D_RS_RANGEFOGENABLE            = 46,    /* SVGA3dBool */
     373   SVGA3D_RS_COLORWRITEENABLE          = 47,    /* SVGA3dColorMask */
     374   SVGA3D_RS_VERTEXMATERIALENABLE      = 48,    /* SVGA3dBool */
     375   SVGA3D_RS_DIFFUSEMATERIALSOURCE     = 49,    /* SVGA3dVertexMaterial */
     376   SVGA3D_RS_SPECULARMATERIALSOURCE    = 50,    /* SVGA3dVertexMaterial */
     377   SVGA3D_RS_AMBIENTMATERIALSOURCE     = 51,    /* SVGA3dVertexMaterial */
     378   SVGA3D_RS_EMISSIVEMATERIALSOURCE    = 52,    /* SVGA3dVertexMaterial */
     379   SVGA3D_RS_TEXTUREFACTOR             = 53,    /* SVGA3dColor */
     380   SVGA3D_RS_LOCALVIEWER               = 54,    /* SVGA3dBool */
     381   SVGA3D_RS_SCISSORTESTENABLE         = 55,    /* SVGA3dBool */
     382   SVGA3D_RS_BLENDCOLOR                = 56,    /* SVGA3dColor */
     383   SVGA3D_RS_STENCILENABLE2SIDED       = 57,    /* SVGA3dBool */
     384   SVGA3D_RS_CCWSTENCILFUNC            = 58,    /* SVGA3dCmpFunc */
     385   SVGA3D_RS_CCWSTENCILFAIL            = 59,    /* SVGA3dStencilOp */
     386   SVGA3D_RS_CCWSTENCILZFAIL           = 60,    /* SVGA3dStencilOp */
     387   SVGA3D_RS_CCWSTENCILPASS            = 61,    /* SVGA3dStencilOp */
     388   SVGA3D_RS_VERTEXBLEND               = 62,    /* SVGA3dVertexBlendFlags */
     389   SVGA3D_RS_SLOPESCALEDEPTHBIAS       = 63,    /* float */
     390   SVGA3D_RS_DEPTHBIAS                 = 64,    /* float */
     391
     392
     393   /*
     394    * Output Gamma Level
     395    *
     396    * Output gamma effects the gamma curve of colors that are output from the
     397    * rendering pipeline.  A value of 1.0 specifies a linear color space. If the
     398    * value is <= 0.0, gamma correction is ignored and linear color space is
     399    * used.
     400    */
     401
     402   SVGA3D_RS_OUTPUTGAMMA               = 65,    /* float */
     403   SVGA3D_RS_ZVISIBLE                  = 66,    /* SVGA3dBool */
     404   SVGA3D_RS_LASTPIXEL                 = 67,    /* SVGA3dBool */
     405   SVGA3D_RS_CLIPPING                  = 68,    /* SVGA3dBool */
     406   SVGA3D_RS_WRAP0                     = 69,    /* SVGA3dWrapFlags */
     407   SVGA3D_RS_WRAP1                     = 70,    /* SVGA3dWrapFlags */
     408   SVGA3D_RS_WRAP2                     = 71,    /* SVGA3dWrapFlags */
     409   SVGA3D_RS_WRAP3                     = 72,    /* SVGA3dWrapFlags */
     410   SVGA3D_RS_WRAP4                     = 73,    /* SVGA3dWrapFlags */
     411   SVGA3D_RS_WRAP5                     = 74,    /* SVGA3dWrapFlags */
     412   SVGA3D_RS_WRAP6                     = 75,    /* SVGA3dWrapFlags */
     413   SVGA3D_RS_WRAP7                     = 76,    /* SVGA3dWrapFlags */
     414   SVGA3D_RS_WRAP8                     = 77,    /* SVGA3dWrapFlags */
     415   SVGA3D_RS_WRAP9                     = 78,    /* SVGA3dWrapFlags */
     416   SVGA3D_RS_WRAP10                    = 79,    /* SVGA3dWrapFlags */
     417   SVGA3D_RS_WRAP11                    = 80,    /* SVGA3dWrapFlags */
     418   SVGA3D_RS_WRAP12                    = 81,    /* SVGA3dWrapFlags */
     419   SVGA3D_RS_WRAP13                    = 82,    /* SVGA3dWrapFlags */
     420   SVGA3D_RS_WRAP14                    = 83,    /* SVGA3dWrapFlags */
     421   SVGA3D_RS_WRAP15                    = 84,    /* SVGA3dWrapFlags */
     422   SVGA3D_RS_MULTISAMPLEANTIALIAS      = 85,    /* SVGA3dBool */
     423   SVGA3D_RS_MULTISAMPLEMASK           = 86,    /* uint32_t */
     424   SVGA3D_RS_INDEXEDVERTEXBLENDENABLE  = 87,    /* SVGA3dBool */
     425   SVGA3D_RS_TWEENFACTOR               = 88,    /* float */
     426   SVGA3D_RS_ANTIALIASEDLINEENABLE     = 89,    /* SVGA3dBool */
     427   SVGA3D_RS_COLORWRITEENABLE1         = 90,    /* SVGA3dColorMask */
     428   SVGA3D_RS_COLORWRITEENABLE2         = 91,    /* SVGA3dColorMask */
     429   SVGA3D_RS_COLORWRITEENABLE3         = 92,    /* SVGA3dColorMask */
     430   SVGA3D_RS_SEPARATEALPHABLENDENABLE  = 93,    /* SVGA3dBool */
     431   SVGA3D_RS_SRCBLENDALPHA             = 94,    /* SVGA3dBlendOp */
     432   SVGA3D_RS_DSTBLENDALPHA             = 95,    /* SVGA3dBlendOp */
     433   SVGA3D_RS_BLENDEQUATIONALPHA        = 96,    /* SVGA3dBlendEquation */
     434   SVGA3D_RS_TRANSPARENCYANTIALIAS     = 97,    /* SVGA3dTransparencyAntialiasType */
     435   SVGA3D_RS_LINEAA                    = 98,    /* SVGA3dBool */
     436   SVGA3D_RS_LINEWIDTH                 = 99,    /* float */
     437   SVGA3D_RS_MAX
     438} SVGA3dRenderStateName;
     439
     440typedef enum {
     441   SVGA3D_TRANSPARENCYANTIALIAS_NORMAL            = 0,
     442   SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE   = 1,
     443   SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE       = 2,
     444   SVGA3D_TRANSPARENCYANTIALIAS_MAX
     445} SVGA3dTransparencyAntialiasType;
     446
     447typedef enum {
     448   SVGA3D_VERTEXMATERIAL_NONE     = 0,    /* Use the value in the current material */
     449   SVGA3D_VERTEXMATERIAL_DIFFUSE  = 1,    /* Use the value in the diffuse component */
     450   SVGA3D_VERTEXMATERIAL_SPECULAR = 2     /* Use the value in the specular component */
     451} SVGA3dVertexMaterial;
     452
     453typedef enum {
     454   SVGA3D_FILLMODE_INVALID = 0,
     455   SVGA3D_FILLMODE_POINT   = 1,
     456   SVGA3D_FILLMODE_LINE    = 2,
     457   SVGA3D_FILLMODE_FILL    = 3,
     458   SVGA3D_FILLMODE_MAX
     459} SVGA3dFillModeType;
     460
     461
     462typedef
     463union {
     464   struct {
     465      uint16_t   mode;       /* SVGA3dFillModeType */
     466      uint16_t   face;       /* SVGA3dFace */
     467   } s;
     468   uint32_t uintValue;
     469} SVGA3dFillMode;
     470
     471typedef enum {
     472   SVGA3D_SHADEMODE_INVALID = 0,
     473   SVGA3D_SHADEMODE_FLAT    = 1,
     474   SVGA3D_SHADEMODE_SMOOTH  = 2,
     475   SVGA3D_SHADEMODE_PHONG   = 3,     /* Not supported */
     476   SVGA3D_SHADEMODE_MAX
     477} SVGA3dShadeMode;
     478
     479typedef
     480union {
     481   struct {
     482      uint16_t repeat;
     483      uint16_t pattern;
     484   } s;
     485   uint32_t uintValue;
     486} SVGA3dLinePattern;
     487
     488typedef enum {
     489   SVGA3D_BLENDOP_INVALID            = 0,
     490   SVGA3D_BLENDOP_ZERO               = 1,
     491   SVGA3D_BLENDOP_ONE                = 2,
     492   SVGA3D_BLENDOP_SRCCOLOR           = 3,
     493   SVGA3D_BLENDOP_INVSRCCOLOR        = 4,
     494   SVGA3D_BLENDOP_SRCALPHA           = 5,
     495   SVGA3D_BLENDOP_INVSRCALPHA        = 6,
     496   SVGA3D_BLENDOP_DESTALPHA          = 7,
     497   SVGA3D_BLENDOP_INVDESTALPHA       = 8,
     498   SVGA3D_BLENDOP_DESTCOLOR          = 9,
     499   SVGA3D_BLENDOP_INVDESTCOLOR       = 10,
     500   SVGA3D_BLENDOP_SRCALPHASAT        = 11,
     501   SVGA3D_BLENDOP_BLENDFACTOR        = 12,
     502   SVGA3D_BLENDOP_INVBLENDFACTOR     = 13,
     503   SVGA3D_BLENDOP_MAX
     504} SVGA3dBlendOp;
     505
     506typedef enum {
     507   SVGA3D_BLENDEQ_INVALID            = 0,
     508   SVGA3D_BLENDEQ_ADD                = 1,
     509   SVGA3D_BLENDEQ_SUBTRACT           = 2,
     510   SVGA3D_BLENDEQ_REVSUBTRACT        = 3,
     511   SVGA3D_BLENDEQ_MINIMUM            = 4,
     512   SVGA3D_BLENDEQ_MAXIMUM            = 5,
     513   SVGA3D_BLENDEQ_MAX
     514} SVGA3dBlendEquation;
     515
     516typedef enum {
     517   SVGA3D_FRONTWINDING_INVALID = 0,
     518   SVGA3D_FRONTWINDING_CW      = 1,
     519   SVGA3D_FRONTWINDING_CCW     = 2,
     520   SVGA3D_FRONTWINDING_MAX
     521} SVGA3dFrontWinding;
     522
     523typedef enum {
     524   SVGA3D_FACE_INVALID  = 0,
     525   SVGA3D_FACE_NONE     = 1,
     526   SVGA3D_FACE_FRONT    = 2,
     527   SVGA3D_FACE_BACK     = 3,
     528   SVGA3D_FACE_FRONT_BACK = 4,
     529   SVGA3D_FACE_MAX
     530} SVGA3dFace;
     531
     532/*
     533 * The order and the values should not be changed
     534 */
     535
     536typedef enum {
     537   SVGA3D_CMP_INVALID              = 0,
     538   SVGA3D_CMP_NEVER                = 1,
     539   SVGA3D_CMP_LESS                 = 2,
     540   SVGA3D_CMP_EQUAL                = 3,
     541   SVGA3D_CMP_LESSEQUAL            = 4,
     542   SVGA3D_CMP_GREATER              = 5,
     543   SVGA3D_CMP_NOTEQUAL             = 6,
     544   SVGA3D_CMP_GREATEREQUAL         = 7,
     545   SVGA3D_CMP_ALWAYS               = 8,
     546   SVGA3D_CMP_MAX
     547} SVGA3dCmpFunc;
     548
     549/*
     550 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
     551 * the fog factor to be specified in the alpha component of the specular
     552 * (a.k.a. secondary) vertex color.
     553 */
     554typedef enum {
     555   SVGA3D_FOGFUNC_INVALID          = 0,
     556   SVGA3D_FOGFUNC_EXP              = 1,
     557   SVGA3D_FOGFUNC_EXP2             = 2,
     558   SVGA3D_FOGFUNC_LINEAR           = 3,
     559   SVGA3D_FOGFUNC_PER_VERTEX       = 4
     560} SVGA3dFogFunction;
     561
     562/*
     563 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
     564 * or per-pixel basis.
     565 */
     566typedef enum {
     567   SVGA3D_FOGTYPE_INVALID          = 0,
     568   SVGA3D_FOGTYPE_VERTEX           = 1,
     569   SVGA3D_FOGTYPE_PIXEL            = 2,
     570   SVGA3D_FOGTYPE_MAX              = 3
     571} SVGA3dFogType;
     572
     573/*
     574 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
     575 * computed using the eye Z value of each pixel (or vertex), whereas range-
     576 * based fog is computed using the actual distance (range) to the eye.
     577 */
     578typedef enum {
     579   SVGA3D_FOGBASE_INVALID          = 0,
     580   SVGA3D_FOGBASE_DEPTHBASED       = 1,
     581   SVGA3D_FOGBASE_RANGEBASED       = 2,
     582   SVGA3D_FOGBASE_MAX              = 3
     583} SVGA3dFogBase;
     584
     585typedef enum {
     586   SVGA3D_STENCILOP_INVALID        = 0,
     587   SVGA3D_STENCILOP_KEEP           = 1,
     588   SVGA3D_STENCILOP_ZERO           = 2,
     589   SVGA3D_STENCILOP_REPLACE        = 3,
     590   SVGA3D_STENCILOP_INCRSAT        = 4,
     591   SVGA3D_STENCILOP_DECRSAT        = 5,
     592   SVGA3D_STENCILOP_INVERT         = 6,
     593   SVGA3D_STENCILOP_INCR           = 7,
     594   SVGA3D_STENCILOP_DECR           = 8,
     595   SVGA3D_STENCILOP_MAX
     596} SVGA3dStencilOp;
     597
     598typedef enum {
     599   SVGA3D_CLIPPLANE_0              = (1 << 0),
     600   SVGA3D_CLIPPLANE_1              = (1 << 1),
     601   SVGA3D_CLIPPLANE_2              = (1 << 2),
     602   SVGA3D_CLIPPLANE_3              = (1 << 3),
     603   SVGA3D_CLIPPLANE_4              = (1 << 4),
     604   SVGA3D_CLIPPLANE_5              = (1 << 5),
     605   SVGA3D_CLIPPLANE_MAX            = SVGA3D_CLIPPLANE_5
     606} SVGA3dClipPlanes;
     607
     608typedef enum {
     609   SVGA3D_CLEAR_COLOR              = 0x1,
     610   SVGA3D_CLEAR_DEPTH              = 0x2,
     611   SVGA3D_CLEAR_STENCIL            = 0x4
     612} SVGA3dClearFlag;
     613
     614typedef enum {
     615   SVGA3D_RT_DEPTH                 = 0,
     616   SVGA3D_RT_STENCIL               = 1,
     617   SVGA3D_RT_COLOR0                = 2,
     618   SVGA3D_RT_COLOR1                = 3,
     619   SVGA3D_RT_COLOR2                = 4,
     620   SVGA3D_RT_COLOR3                = 5,
     621   SVGA3D_RT_COLOR4                = 6,
     622   SVGA3D_RT_COLOR5                = 7,
     623   SVGA3D_RT_COLOR6                = 8,
     624   SVGA3D_RT_COLOR7                = 9,
     625   SVGA3D_RT_MAX,
     626   SVGA3D_RT_INVALID               = ((uint32_t)-1)
     627} SVGA3dRenderTargetType;
     628
     629#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
     630
     631typedef
     632union {
     633   struct {
     634      uint32_t  red   : 1;
     635      uint32_t  green : 1;
     636      uint32_t  blue  : 1;
     637      uint32_t  alpha : 1;
     638   } s;
     639   uint32_t uintValue;
     640} SVGA3dColorMask;
     641
     642typedef enum {
     643   SVGA3D_VBLEND_DISABLE            = 0,
     644   SVGA3D_VBLEND_1WEIGHT            = 1,
     645   SVGA3D_VBLEND_2WEIGHT            = 2,
     646   SVGA3D_VBLEND_3WEIGHT            = 3
     647} SVGA3dVertexBlendFlags;
     648
     649typedef enum {
     650   SVGA3D_WRAPCOORD_0   = 1 << 0,
     651   SVGA3D_WRAPCOORD_1   = 1 << 1,
     652   SVGA3D_WRAPCOORD_2   = 1 << 2,
     653   SVGA3D_WRAPCOORD_3   = 1 << 3,
     654   SVGA3D_WRAPCOORD_ALL = 0xF
     655} SVGA3dWrapFlags;
     656
     657/*
     658 * SVGA_3D_CMD_TEXTURESTATE Types.  All value types
     659 * must fit in a uint32_t.
     660 */
     661
     662typedef enum {
     663   SVGA3D_TS_INVALID                    = 0,
     664   SVGA3D_TS_BIND_TEXTURE               = 1,    /* SVGA3dSurfaceId */
     665   SVGA3D_TS_COLOROP                    = 2,    /* SVGA3dTextureCombiner */
     666   SVGA3D_TS_COLORARG1                  = 3,    /* SVGA3dTextureArgData */
     667   SVGA3D_TS_COLORARG2                  = 4,    /* SVGA3dTextureArgData */
     668   SVGA3D_TS_ALPHAOP                    = 5,    /* SVGA3dTextureCombiner */
     669   SVGA3D_TS_ALPHAARG1                  = 6,    /* SVGA3dTextureArgData */
     670   SVGA3D_TS_ALPHAARG2                  = 7,    /* SVGA3dTextureArgData */
     671   SVGA3D_TS_ADDRESSU                   = 8,    /* SVGA3dTextureAddress */
     672   SVGA3D_TS_ADDRESSV                   = 9,    /* SVGA3dTextureAddress */
     673   SVGA3D_TS_MIPFILTER                  = 10,   /* SVGA3dTextureFilter */
     674   SVGA3D_TS_MAGFILTER                  = 11,   /* SVGA3dTextureFilter */
     675   SVGA3D_TS_MINFILTER                  = 12,   /* SVGA3dTextureFilter */
     676   SVGA3D_TS_BORDERCOLOR                = 13,   /* SVGA3dColor */
     677   SVGA3D_TS_TEXCOORDINDEX              = 14,   /* uint32_t */
     678   SVGA3D_TS_TEXTURETRANSFORMFLAGS      = 15,   /* SVGA3dTexTransformFlags */
     679   SVGA3D_TS_TEXCOORDGEN                = 16,   /* SVGA3dTextureCoordGen */
     680   SVGA3D_TS_BUMPENVMAT00               = 17,   /* float */
     681   SVGA3D_TS_BUMPENVMAT01               = 18,   /* float */
     682   SVGA3D_TS_BUMPENVMAT10               = 19,   /* float */
     683   SVGA3D_TS_BUMPENVMAT11               = 20,   /* float */
     684   SVGA3D_TS_TEXTURE_MIPMAP_LEVEL       = 21,   /* uint32_t */
     685   SVGA3D_TS_TEXTURE_LOD_BIAS           = 22,   /* float */
     686   SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL  = 23,   /* uint32_t */
     687   SVGA3D_TS_ADDRESSW                   = 24,   /* SVGA3dTextureAddress */
     688
     689
     690   /*
     691    * Sampler Gamma Level
     692    *
     693    * Sampler gamma effects the color of samples taken from the sampler.  A
     694    * value of 1.0 will produce linear samples.  If the value is <= 0.0 the
     695    * gamma value is ignored and a linear space is used.
     696    */
     697
     698   SVGA3D_TS_GAMMA                      = 25,   /* float */
     699   SVGA3D_TS_BUMPENVLSCALE              = 26,   /* float */
     700   SVGA3D_TS_BUMPENVLOFFSET             = 27,   /* float */
     701   SVGA3D_TS_COLORARG0                  = 28,   /* SVGA3dTextureArgData */
     702   SVGA3D_TS_ALPHAARG0                  = 29,   /* SVGA3dTextureArgData */
     703   SVGA3D_TS_MAX
     704} SVGA3dTextureStateName;
     705
     706typedef enum {
     707   SVGA3D_TC_INVALID                   = 0,
     708   SVGA3D_TC_DISABLE                   = 1,
     709   SVGA3D_TC_SELECTARG1                = 2,
     710   SVGA3D_TC_SELECTARG2                = 3,
     711   SVGA3D_TC_MODULATE                  = 4,
     712   SVGA3D_TC_ADD                       = 5,
     713   SVGA3D_TC_ADDSIGNED                 = 6,
     714   SVGA3D_TC_SUBTRACT                  = 7,
     715   SVGA3D_TC_BLENDTEXTUREALPHA         = 8,
     716   SVGA3D_TC_BLENDDIFFUSEALPHA         = 9,
     717   SVGA3D_TC_BLENDCURRENTALPHA         = 10,
     718   SVGA3D_TC_BLENDFACTORALPHA          = 11,
     719   SVGA3D_TC_MODULATE2X                = 12,
     720   SVGA3D_TC_MODULATE4X                = 13,
     721   SVGA3D_TC_DSDT                      = 14,
     722   SVGA3D_TC_DOTPRODUCT3               = 15,
     723   SVGA3D_TC_BLENDTEXTUREALPHAPM       = 16,
     724   SVGA3D_TC_ADDSIGNED2X               = 17,
     725   SVGA3D_TC_ADDSMOOTH                 = 18,
     726   SVGA3D_TC_PREMODULATE               = 19,
     727   SVGA3D_TC_MODULATEALPHA_ADDCOLOR    = 20,
     728   SVGA3D_TC_MODULATECOLOR_ADDALPHA    = 21,
     729   SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
     730   SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
     731   SVGA3D_TC_BUMPENVMAPLUMINANCE       = 24,
     732   SVGA3D_TC_MULTIPLYADD               = 25,
     733   SVGA3D_TC_LERP                      = 26,
     734   SVGA3D_TC_MAX
     735} SVGA3dTextureCombiner;
     736
     737#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
     738
     739typedef enum {
     740   SVGA3D_TEX_ADDRESS_INVALID    = 0,
     741   SVGA3D_TEX_ADDRESS_WRAP       = 1,
     742   SVGA3D_TEX_ADDRESS_MIRROR     = 2,
     743   SVGA3D_TEX_ADDRESS_CLAMP      = 3,
     744   SVGA3D_TEX_ADDRESS_BORDER     = 4,
     745   SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
     746   SVGA3D_TEX_ADDRESS_EDGE       = 6,
     747   SVGA3D_TEX_ADDRESS_MAX
     748} SVGA3dTextureAddress;
     749
     750/*
     751 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
     752 * disabled, and the rasterizer should use the magnification filter instead.
     753 */
     754typedef enum {
     755   SVGA3D_TEX_FILTER_NONE           = 0,
     756   SVGA3D_TEX_FILTER_NEAREST        = 1,
     757   SVGA3D_TEX_FILTER_LINEAR         = 2,
     758   SVGA3D_TEX_FILTER_ANISOTROPIC    = 3,
     759   SVGA3D_TEX_FILTER_FLATCUBIC      = 4, // Deprecated, not implemented
     760   SVGA3D_TEX_FILTER_GAUSSIANCUBIC  = 5, // Deprecated, not implemented
     761   SVGA3D_TEX_FILTER_PYRAMIDALQUAD  = 6, // Not currently implemented
     762   SVGA3D_TEX_FILTER_GAUSSIANQUAD   = 7, // Not currently implemented
     763   SVGA3D_TEX_FILTER_MAX
     764} SVGA3dTextureFilter;
     765
     766typedef enum {
     767   SVGA3D_TEX_TRANSFORM_OFF    = 0,
     768   SVGA3D_TEX_TRANSFORM_S      = (1 << 0),
     769   SVGA3D_TEX_TRANSFORM_T      = (1 << 1),
     770   SVGA3D_TEX_TRANSFORM_R      = (1 << 2),
     771   SVGA3D_TEX_TRANSFORM_Q      = (1 << 3),
     772   SVGA3D_TEX_PROJECTED        = (1 << 15)
     773} SVGA3dTexTransformFlags;
     774
     775typedef enum {
     776   SVGA3D_TEXCOORD_GEN_OFF              = 0,
     777   SVGA3D_TEXCOORD_GEN_EYE_POSITION     = 1,
     778   SVGA3D_TEXCOORD_GEN_EYE_NORMAL       = 2,
     779   SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
     780   SVGA3D_TEXCOORD_GEN_SPHERE           = 4,
     781   SVGA3D_TEXCOORD_GEN_MAX
     782} SVGA3dTextureCoordGen;
     783
     784/*
     785 * Texture argument constants for texture combiner
     786 */
     787typedef enum {
     788   SVGA3D_TA_INVALID    = 0,
     789   SVGA3D_TA_CONSTANT   = 1,
     790   SVGA3D_TA_PREVIOUS   = 2,
     791   SVGA3D_TA_DIFFUSE    = 3,
     792   SVGA3D_TA_TEXTURE    = 4,
     793   SVGA3D_TA_SPECULAR   = 5,
     794   SVGA3D_TA_MAX
     795} SVGA3dTextureArgData;
     796
     797#define SVGA3D_TM_MASK_LEN 4
     798
     799/* Modifiers for texture argument constants defined above. */
     800typedef enum {
     801   SVGA3D_TM_NONE       = 0,
     802   SVGA3D_TM_ALPHA      = (1 << SVGA3D_TM_MASK_LEN),
     803   SVGA3D_TM_ONE_MINUS  = (2 << SVGA3D_TM_MASK_LEN)
     804} SVGA3dTextureArgModifier;
     805
     806#define SVGA3D_INVALID_ID         ((uint32_t)-1)
     807#define SVGA3D_MAX_CLIP_PLANES    6
     808
     809/*
     810 * This is the limit to the number of fixed-function texture
     811 * transforms and texture coordinates we can support. It does *not*
     812 * correspond to the number of texture image units (samplers) we
     813 * support!
     814 */
     815#define SVGA3D_MAX_TEXTURE_COORDS 8
     816
     817/*
     818 * Vertex declarations
     819 *
     820 * Notes:
     821 *
     822 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
     823 * draw with any POSITIONT vertex arrays, the programmable vertex
     824 * pipeline will be implicitly disabled. Drawing will take place as if
     825 * no vertex shader was bound.
     826 */
     827
     828typedef enum {
     829   SVGA3D_DECLUSAGE_POSITION     = 0,
     830   SVGA3D_DECLUSAGE_BLENDWEIGHT,       //  1
     831   SVGA3D_DECLUSAGE_BLENDINDICES,      //  2
     832   SVGA3D_DECLUSAGE_NORMAL,            //  3
     833   SVGA3D_DECLUSAGE_PSIZE,             //  4
     834   SVGA3D_DECLUSAGE_TEXCOORD,          //  5
     835   SVGA3D_DECLUSAGE_TANGENT,           //  6
     836   SVGA3D_DECLUSAGE_BINORMAL,          //  7
     837   SVGA3D_DECLUSAGE_TESSFACTOR,        //  8
     838   SVGA3D_DECLUSAGE_POSITIONT,         //  9
     839   SVGA3D_DECLUSAGE_COLOR,             // 10
     840   SVGA3D_DECLUSAGE_FOG,               // 11
     841   SVGA3D_DECLUSAGE_DEPTH,             // 12
     842   SVGA3D_DECLUSAGE_SAMPLE,            // 13
     843   SVGA3D_DECLUSAGE_MAX
     844} SVGA3dDeclUsage;
     845
     846typedef enum {
     847   SVGA3D_DECLMETHOD_DEFAULT     = 0,
     848   SVGA3D_DECLMETHOD_PARTIALU,
     849   SVGA3D_DECLMETHOD_PARTIALV,
     850   SVGA3D_DECLMETHOD_CROSSUV,          // Normal
     851   SVGA3D_DECLMETHOD_UV,
     852   SVGA3D_DECLMETHOD_LOOKUP,           // Lookup a displacement map
     853   SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED  // Lookup a pre-sampled displacement map
     854} SVGA3dDeclMethod;
     855
     856typedef enum {
     857   SVGA3D_DECLTYPE_FLOAT1        =  0,
     858   SVGA3D_DECLTYPE_FLOAT2        =  1,
     859   SVGA3D_DECLTYPE_FLOAT3        =  2,
     860   SVGA3D_DECLTYPE_FLOAT4        =  3,
     861   SVGA3D_DECLTYPE_D3DCOLOR      =  4,
     862   SVGA3D_DECLTYPE_UBYTE4        =  5,
     863   SVGA3D_DECLTYPE_SHORT2        =  6,
     864   SVGA3D_DECLTYPE_SHORT4        =  7,
     865   SVGA3D_DECLTYPE_UBYTE4N       =  8,
     866   SVGA3D_DECLTYPE_SHORT2N       =  9,
     867   SVGA3D_DECLTYPE_SHORT4N       = 10,
     868   SVGA3D_DECLTYPE_USHORT2N      = 11,
     869   SVGA3D_DECLTYPE_USHORT4N      = 12,
     870   SVGA3D_DECLTYPE_UDEC3         = 13,
     871   SVGA3D_DECLTYPE_DEC3N         = 14,
     872   SVGA3D_DECLTYPE_FLOAT16_2     = 15,
     873   SVGA3D_DECLTYPE_FLOAT16_4     = 16,
     874   SVGA3D_DECLTYPE_MAX
     875} SVGA3dDeclType;
     876
     877/*
     878 * This structure is used for the divisor for geometry instancing;
     879 * it's a direct translation of the Direct3D equivalent.
     880 */
     881typedef union {
     882   struct {
     883      /*
     884       * For index data, this number represents the number of instances to draw.
     885       * For instance data, this number represents the number of
     886       * instances/vertex in this stream
     887       */
     888      uint32_t count : 30;
     889
     890      /*
     891       * This is 1 if this is supposed to be the data that is repeated for
     892       * every instance.
     893       */
     894      uint32_t indexedData : 1;
     895
     896      /*
     897       * This is 1 if this is supposed to be the per-instance data.
     898       */
     899      uint32_t instanceData : 1;
     900   } s;
     901
     902   uint32_t value;
     903} SVGA3dVertexDivisor;
     904
     905typedef enum {
     906   SVGA3D_PRIMITIVE_INVALID                     = 0,
     907   SVGA3D_PRIMITIVE_TRIANGLELIST                = 1,
     908   SVGA3D_PRIMITIVE_POINTLIST                   = 2,
     909   SVGA3D_PRIMITIVE_LINELIST                    = 3,
     910   SVGA3D_PRIMITIVE_LINESTRIP                   = 4,
     911   SVGA3D_PRIMITIVE_TRIANGLESTRIP               = 5,
     912   SVGA3D_PRIMITIVE_TRIANGLEFAN                 = 6,
     913   SVGA3D_PRIMITIVE_MAX
     914} SVGA3dPrimitiveType;
     915
     916typedef enum {
     917   SVGA3D_COORDINATE_INVALID                   = 0,
     918   SVGA3D_COORDINATE_LEFTHANDED                = 1,
     919   SVGA3D_COORDINATE_RIGHTHANDED               = 2,
     920   SVGA3D_COORDINATE_MAX
     921} SVGA3dCoordinateType;
     922
     923typedef enum {
     924   SVGA3D_TRANSFORM_INVALID                     = 0,
     925   SVGA3D_TRANSFORM_WORLD                       = 1,
     926   SVGA3D_TRANSFORM_VIEW                        = 2,
     927   SVGA3D_TRANSFORM_PROJECTION                  = 3,
     928   SVGA3D_TRANSFORM_TEXTURE0                    = 4,
     929   SVGA3D_TRANSFORM_TEXTURE1                    = 5,
     930   SVGA3D_TRANSFORM_TEXTURE2                    = 6,
     931   SVGA3D_TRANSFORM_TEXTURE3                    = 7,
     932   SVGA3D_TRANSFORM_TEXTURE4                    = 8,
     933   SVGA3D_TRANSFORM_TEXTURE5                    = 9,
     934   SVGA3D_TRANSFORM_TEXTURE6                    = 10,
     935   SVGA3D_TRANSFORM_TEXTURE7                    = 11,
     936   SVGA3D_TRANSFORM_WORLD1                      = 12,
     937   SVGA3D_TRANSFORM_WORLD2                      = 13,
     938   SVGA3D_TRANSFORM_WORLD3                      = 14,
     939   SVGA3D_TRANSFORM_MAX
     940} SVGA3dTransformType;
     941
     942typedef enum {
     943   SVGA3D_LIGHTTYPE_INVALID                     = 0,
     944   SVGA3D_LIGHTTYPE_POINT                       = 1,
     945   SVGA3D_LIGHTTYPE_SPOT1                       = 2, /* 1-cone, in degrees */
     946   SVGA3D_LIGHTTYPE_SPOT2                       = 3, /* 2-cone, in radians */
     947   SVGA3D_LIGHTTYPE_DIRECTIONAL                 = 4,
     948   SVGA3D_LIGHTTYPE_MAX
     949} SVGA3dLightType;
     950
     951typedef enum {
     952   SVGA3D_CUBEFACE_POSX                         = 0,
     953   SVGA3D_CUBEFACE_NEGX                         = 1,
     954   SVGA3D_CUBEFACE_POSY                         = 2,
     955   SVGA3D_CUBEFACE_NEGY                         = 3,
     956   SVGA3D_CUBEFACE_POSZ                         = 4,
     957   SVGA3D_CUBEFACE_NEGZ                         = 5
     958} SVGA3dCubeFace;
     959
     960typedef enum {
     961   SVGA3D_SHADERTYPE_VS                         = 1,
     962   SVGA3D_SHADERTYPE_PS                         = 2,
     963   SVGA3D_SHADERTYPE_MAX
     964} SVGA3dShaderType;
     965
     966typedef enum {
     967   SVGA3D_CONST_TYPE_FLOAT                      = 0,
     968   SVGA3D_CONST_TYPE_INT                        = 1,
     969   SVGA3D_CONST_TYPE_BOOL                       = 2
     970} SVGA3dShaderConstType;
     971
     972#define SVGA3D_MAX_SURFACE_FACES                6
     973
     974typedef enum {
     975   SVGA3D_STRETCH_BLT_POINT                     = 0,
     976   SVGA3D_STRETCH_BLT_LINEAR                    = 1,
     977   SVGA3D_STRETCH_BLT_MAX
     978} SVGA3dStretchBltMode;
     979
     980typedef enum {
     981   SVGA3D_QUERYTYPE_OCCLUSION                   = 0,
     982   SVGA3D_QUERYTYPE_MAX
     983} SVGA3dQueryType;
     984
     985typedef enum {
     986   SVGA3D_QUERYSTATE_PENDING     = 0,      /* Waiting on the host (set by guest) */
     987   SVGA3D_QUERYSTATE_SUCCEEDED   = 1,      /* Completed successfully (set by host) */
     988   SVGA3D_QUERYSTATE_FAILED      = 2,      /* Completed unsuccessfully (set by host) */
     989   SVGA3D_QUERYSTATE_NEW         = 3       /* Never submitted (For guest use only) */
     990} SVGA3dQueryState;
     991
     992typedef enum {
     993   SVGA3D_WRITE_HOST_VRAM        = 1,
     994   SVGA3D_READ_HOST_VRAM         = 2
     995} SVGA3dTransferType;
     996
     997/*
     998 * The maximum number of vertex arrays we're guaranteed to support in
     999 * SVGA_3D_CMD_DRAWPRIMITIVES.
     1000 */
     1001#define SVGA3D_MAX_VERTEX_ARRAYS   32
     1002
     1003/*
     1004 * The maximum number of primitive ranges we're guaranteed to support
     1005 * in SVGA_3D_CMD_DRAWPRIMITIVES.
     1006 */
     1007#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
     1008
     1009/*
     1010 * Identifiers for commands in the command FIFO.
     1011 *
     1012 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
     1013 * the SVGA3D protocol and remain reserved; they should not be used in the
     1014 * future.
     1015 *
     1016 * IDs between 1040 and 1999 (inclusive) are available for use by the
     1017 * current SVGA3D protocol.
     1018 *
     1019 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
     1020 * and up.
     1021 */
     1022
    81023#define SVGA_3D_CMD_LEGACY_BASE            1000
    91024#define SVGA_3D_CMD_BASE                   1040
    101025
    11 #define SVGA_3D_CMD_SURFACE_DEFINE         SVGA_3D_CMD_BASE + 0
     1026#define SVGA_3D_CMD_SURFACE_DEFINE         SVGA_3D_CMD_BASE + 0     // Deprecated
    121027#define SVGA_3D_CMD_SURFACE_DESTROY        SVGA_3D_CMD_BASE + 1
    131028#define SVGA_3D_CMD_SURFACE_COPY           SVGA_3D_CMD_BASE + 2
    … …  
    271042#define SVGA_3D_CMD_SETCLIPPLANE           SVGA_3D_CMD_BASE + 16
    281043#define SVGA_3D_CMD_CLEAR                  SVGA_3D_CMD_BASE + 17
    29 #define SVGA_3D_CMD_PRESENT                SVGA_3D_CMD_BASE + 18
     1044#define SVGA_3D_CMD_PRESENT                SVGA_3D_CMD_BASE + 18    // Deprecated
    301045#define SVGA_3D_CMD_SHADER_DEFINE          SVGA_3D_CMD_BASE + 19
    311046#define SVGA_3D_CMD_SHADER_DESTROY         SVGA_3D_CMD_BASE + 20
    … …  
    371052#define SVGA_3D_CMD_END_QUERY              SVGA_3D_CMD_BASE + 26
    381053#define SVGA_3D_CMD_WAIT_FOR_QUERY         SVGA_3D_CMD_BASE + 27
    39 #define SVGA_3D_CMD_PRESENT_READBACK       SVGA_3D_CMD_BASE + 28
     1054#define SVGA_3D_CMD_PRESENT_READBACK       SVGA_3D_CMD_BASE + 28    // Deprecated
    401055#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
    411056#define SVGA_3D_CMD_SURFACE_DEFINE_V2      SVGA_3D_CMD_BASE + 30
    … …  
    471062#define SVGA_3D_CMD_FUTURE_MAX             2000
    481063
    49 typedef enum
    50 {
    51    SVGA3D_WRITE_HOST_VRAM        = 1,
    52    SVGA3D_READ_HOST_VRAM         = 2
    53 } SVGA3dTransferType;
     1064/*
     1065 * Common substructures used in multiple FIFO commands:
     1066 */
     1067
     1068typedef struct {
     1069   union {
     1070      struct {
     1071         uint16_t  function;       // SVGA3dFogFunction
     1072         uint8_t   type;           // SVGA3dFogType
     1073         uint8_t   base;           // SVGA3dFogBase
     1074      } s;
     1075      uint32_t     uintValue;
     1076   };
     1077} SVGA3dFogMode;
     1078
     1079/*
     1080 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
     1081 * is a surface ID as well as face/mipmap indices.
     1082 */
     1083
     1084typedef
     1085struct SVGA3dSurfaceImageId {
     1086   uint32_t               sid;
     1087   uint32_t               face;
     1088   uint32_t               mipmap;
     1089} SVGA3dSurfaceImageId;
     1090
     1091typedef
     1092struct SVGA3dGuestImage {
     1093   SVGAGuestPtr         ptr;
     1094
     1095   /*
     1096    * A note on interpretation of pitch: This value of pitch is the
     1097    * number of bytes between vertically adjacent image
     1098    * blocks. Normally this is the number of bytes between the first
     1099    * pixel of two adjacent scanlines. With compressed textures,
     1100    * however, this may represent the number of bytes between
     1101    * compression blocks rather than between rows of pixels.
     1102    *
     1103    * XXX: Compressed textures currently must be tightly packed in guest memory.
     1104    *
     1105    * If the image is 1-dimensional, pitch is ignored.
     1106    *
     1107    * If 'pitch' is zero, the SVGA3D device calculates a pitch value
     1108    * assuming each row of blocks is tightly packed.
     1109    */
     1110   uint32_t pitch;
     1111} SVGA3dGuestImage;
     1112
     1113
     1114/*
     1115 * FIFO command format definitions:
     1116 */
     1117
     1118/*
     1119 * The data size header following cmdNum for every 3d command
     1120 */
     1121typedef
     1122struct {
     1123   /* uint32_t               id; duplicate*/
     1124   uint32_t               size;
     1125} SVGA3dCmdHeader;
     1126
     1127/*
     1128 * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
     1129 * optional mipmaps and cube faces.
     1130 */
     1131
     1132typedef
     1133struct {
     1134   uint32_t               width;
     1135   uint32_t               height;
     1136   uint32_t               depth;
     1137} SVGA3dSize;
     1138
     1139typedef enum {
     1140   SVGA3D_SURFACE_CUBEMAP              = (1 << 0),
     1141   SVGA3D_SURFACE_HINT_STATIC          = (1 << 1),
     1142   SVGA3D_SURFACE_HINT_DYNAMIC         = (1 << 2),
     1143   SVGA3D_SURFACE_HINT_INDEXBUFFER     = (1 << 3),
     1144   SVGA3D_SURFACE_HINT_VERTEXBUFFER    = (1 << 4),
     1145   SVGA3D_SURFACE_HINT_TEXTURE         = (1 << 5),
     1146   SVGA3D_SURFACE_HINT_RENDERTARGET    = (1 << 6),
     1147   SVGA3D_SURFACE_HINT_DEPTHSTENCIL    = (1 << 7),
     1148   SVGA3D_SURFACE_HINT_WRITEONLY       = (1 << 8),
     1149   SVGA3D_SURFACE_MASKABLE_ANTIALIAS   = (1 << 9),
     1150   SVGA3D_SURFACE_AUTOGENMIPMAPS       = (1 << 10)
     1151} SVGA3dSurfaceFlags;
     1152
     1153typedef
     1154struct {
     1155   uint32_t               numMipLevels;
     1156} SVGA3dSurfaceFace;
     1157
     1158typedef
     1159struct {
     1160   uint32_t                      sid;
     1161   SVGA3dSurfaceFlags          surfaceFlags;
     1162   SVGA3dSurfaceFormat         format;
     1163   /*
     1164    * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
     1165    * structures must have the same value of numMipLevels field.
     1166    * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
     1167    * numMipLevels set to 0.
     1168    */
     1169   SVGA3dSurfaceFace           face[SVGA3D_MAX_SURFACE_FACES];
     1170   /*
     1171    * Followed by an SVGA3dSize structure for each mip level in each face.
     1172    *
     1173    * A note on surface sizes: Sizes are always specified in pixels,
     1174    * even if the true surface size is not a multiple of the minimum
     1175    * block size of the surface's format. For example, a 3x3x1 DXT1
     1176    * compressed texture would actually be stored as a 4x4x1 image in
     1177    * memory.
     1178    */
     1179} SVGA3dCmdDefineSurface;       /* SVGA_3D_CMD_SURFACE_DEFINE */
     1180
     1181typedef
     1182struct {
     1183   uint32_t                      sid;
     1184   SVGA3dSurfaceFlags          surfaceFlags;
     1185   SVGA3dSurfaceFormat         format;
     1186   /*
     1187    * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
     1188    * structures must have the same value of numMipLevels field.
     1189    * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
     1190    * numMipLevels set to 0.
     1191    */
     1192   SVGA3dSurfaceFace           face[SVGA3D_MAX_SURFACE_FACES];
     1193   uint32_t                      multisampleCount;
     1194   SVGA3dTextureFilter         autogenFilter;
     1195   /*
     1196    * Followed by an SVGA3dSize structure for each mip level in each face.
     1197    *
     1198    * A note on surface sizes: Sizes are always specified in pixels,
     1199    * even if the true surface size is not a multiple of the minimum
     1200    * block size of the surface's format. For example, a 3x3x1 DXT1
     1201    * compressed texture would actually be stored as a 4x4x1 image in
     1202    * memory.
     1203    */
     1204} SVGA3dCmdDefineSurface_v2;     /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
     1205
     1206typedef
     1207struct {
     1208   uint32_t               sid;
     1209} SVGA3dCmdDestroySurface;      /* SVGA_3D_CMD_SURFACE_DESTROY */
     1210
     1211typedef
     1212struct {
     1213   uint32_t               cid;
     1214} SVGA3dCmdDefineContext;       /* SVGA_3D_CMD_CONTEXT_DEFINE */
     1215
     1216typedef
     1217struct {
     1218   uint32_t               cid;
     1219} SVGA3dCmdDestroyContext;      /* SVGA_3D_CMD_CONTEXT_DESTROY */
     1220
     1221typedef
     1222struct {
     1223   uint32_t               cid;
     1224   SVGA3dClearFlag      clearFlag;
     1225   uint32_t               color;
     1226   float                depth;
     1227   uint32_t               stencil;
     1228   /* Followed by variable number of SVGA3dRect structures */
     1229} SVGA3dCmdClear;               /* SVGA_3D_CMD_CLEAR */
     1230
     1231typedef
     1232struct SVGA3dCopyRect {
     1233   uint32_t               x;
     1234   uint32_t               y;
     1235   uint32_t               w;
     1236   uint32_t               h;
     1237   uint32_t               srcx;
     1238   uint32_t               srcy;
     1239} SVGA3dCopyRect;
     1240
     1241typedef
     1242struct SVGA3dCopyBox {
     1243   uint32_t               x;
     1244   uint32_t               y;
     1245   uint32_t               z;
     1246   uint32_t               w;
     1247   uint32_t               h;
     1248   uint32_t               d;
     1249   uint32_t               srcx;
     1250   uint32_t               srcy;
     1251   uint32_t               srcz;
     1252} SVGA3dCopyBox;
     1253
     1254typedef
     1255struct {
     1256   uint32_t               x;
     1257   uint32_t               y;
     1258   uint32_t               w;
     1259   uint32_t               h;
     1260} SVGA3dRect;
     1261
     1262typedef
     1263struct {
     1264   uint32_t               x;
     1265   uint32_t               y;
     1266   uint32_t               z;
     1267   uint32_t               w;
     1268   uint32_t               h;
     1269   uint32_t               d;
     1270} SVGA3dBox;
     1271
     1272typedef
     1273struct {
     1274   uint32_t               x;
     1275   uint32_t               y;
     1276   uint32_t               z;
     1277} SVGA3dPoint;
     1278
     1279typedef
     1280struct {
     1281   SVGA3dLightType      type;
     1282   SVGA3dBool           inWorldSpace;
     1283   float                diffuse[4];
     1284   float                specular[4];
     1285   float                ambient[4];
     1286   float                position[4];
     1287   float                direction[4];
     1288   float                range;
     1289   float                falloff;
     1290   float                attenuation0;
     1291   float                attenuation1;
     1292   float                attenuation2;
     1293   float                theta;
     1294   float                phi;
     1295} SVGA3dLightData;
     1296
     1297typedef
     1298struct {
     1299   uint32_t               sid;
     1300   /* Followed by variable number of SVGA3dCopyRect structures */
     1301} SVGA3dCmdPresent;             /* SVGA_3D_CMD_PRESENT */
     1302
     1303typedef
     1304struct {
     1305   SVGA3dRenderStateName   state;
     1306   union {
     1307      uint32_t               uintValue;
     1308      float                floatValue;
     1309   };
     1310} SVGA3dRenderState;
     1311
     1312typedef
     1313struct {
     1314   uint32_t               cid;
     1315   /* Followed by variable number of SVGA3dRenderState structures */
     1316} SVGA3dCmdSetRenderState;      /* SVGA_3D_CMD_SETRENDERSTATE */
     1317
     1318typedef
     1319struct {
     1320   uint32_t                 cid;
     1321   SVGA3dRenderTargetType type;
     1322   SVGA3dSurfaceImageId   target;
     1323} SVGA3dCmdSetRenderTarget;     /* SVGA_3D_CMD_SETRENDERTARGET */
     1324
     1325typedef
     1326struct {
     1327   SVGA3dSurfaceImageId  src;
     1328   SVGA3dSurfaceImageId  dest;
     1329   /* Followed by variable number of SVGA3dCopyBox structures */
     1330} SVGA3dCmdSurfaceCopy;               /* SVGA_3D_CMD_SURFACE_COPY */
     1331
     1332typedef
     1333struct {
     1334   SVGA3dSurfaceImageId  src;
     1335   SVGA3dSurfaceImageId  dest;
     1336   SVGA3dBox             boxSrc;
     1337   SVGA3dBox             boxDest;
     1338   SVGA3dStretchBltMode  mode;
     1339} SVGA3dCmdSurfaceStretchBlt;         /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
     1340
     1341typedef
     1342struct {
     1343   /*
     1344    * If the discard flag is present in a surface DMA operation, the host may
     1345    * discard the contents of the current mipmap level and face of the target
     1346    * surface before applying the surface DMA contents.
     1347    */
     1348   uint32_t discard : 1;
     1349
     1350   /*
     1351    * If the unsynchronized flag is present, the host may perform this upload
     1352    * without syncing to pending reads on this surface.
     1353    */
     1354   uint32_t unsynchronized : 1;
     1355
     1356   /*
     1357    * Guests *MUST* set the reserved bits to 0 before submitting the command
     1358    * suffix as future flags may occupy these bits.
     1359    */
     1360   uint32_t reserved : 30;
     1361} SVGA3dSurfaceDMAFlags;
     1362
     1363typedef
     1364struct {
     1365   SVGA3dGuestImage      guest;
     1366   SVGA3dSurfaceImageId  host;
     1367   SVGA3dTransferType    transfer;
     1368   /*
     1369    * Followed by variable number of SVGA3dCopyBox structures. For consistency
     1370    * in all clipping logic and coordinate translation, we define the
     1371    * "source" in each copyBox as the guest image and the
     1372    * "destination" as the host image, regardless of transfer
     1373    * direction.
     1374    *
     1375    * For efficiency, the SVGA3D device is free to copy more data than
     1376    * specified. For example, it may round copy boxes outwards such
     1377    * that they lie on particular alignment boundaries.
     1378    */
     1379} SVGA3dCmdSurfaceDMA;                /* SVGA_3D_CMD_SURFACE_DMA */
     1380
     1381/*
     1382 * SVGA3dCmdSurfaceDMASuffix --
     1383 *
     1384 *    This is a command suffix that will appear after a SurfaceDMA command in
     1385 *    the FIFO.  It contains some extra information that hosts may use to
     1386 *    optimize performance or protect the guest.  This suffix exists to preserve
     1387 *    backwards compatibility while also allowing for new functionality to be
     1388 *    implemented.
     1389 */
     1390
     1391typedef
     1392struct {
     1393   uint32_t suffixSize;
     1394
     1395   /*
     1396    * The maximum offset is used to determine the maximum offset from the
     1397    * guestPtr base address that will be accessed or written to during this
     1398    * surfaceDMA.  If the suffix is supported, the host will respect this
     1399    * boundary while performing surface DMAs.
     1400    *
     1401    * Defaults to MAX_uint32_t
     1402    */
     1403   uint32_t maximumOffset;
     1404
     1405   /*
     1406    * A set of flags that describes optimizations that the host may perform
     1407    * while performing this surface DMA operation.  The guest should never rely
     1408    * on behaviour that is different when these flags are set for correctness.
     1409    *
     1410    * Defaults to 0
     1411    */
     1412   SVGA3dSurfaceDMAFlags flags;
     1413} SVGA3dCmdSurfaceDMASuffix;
     1414
     1415/*
     1416 * SVGA_3D_CMD_DRAW_PRIMITIVES --
     1417 *
     1418 *   This command is the SVGA3D device's generic drawing entry point.
     1419 *   It can draw multiple ranges of primitives, optionally using an
     1420 *   index buffer, using an arbitrary collection of vertex buffers.
     1421 *
     1422 *   Each SVGA3dVertexDecl defines a distinct vertex array to bind
     1423 *   during this draw call. The declarations specify which surface
     1424 *   the vertex data lives in, what that vertex data is used for,
     1425 *   and how to interpret it.
     1426 *
     1427 *   Each SVGA3dPrimitiveRange defines a collection of primitives
     1428 *   to render using the same vertex arrays. An index buffer is
     1429 *   optional.
     1430 */
     1431
     1432typedef
     1433struct {
     1434   /*
     1435    * A range hint is an optional specification for the range of indices
     1436    * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
     1437    * that the entire array will be used.
     1438    *
     1439    * These are only hints. The SVGA3D device may use them for
     1440    * performance optimization if possible, but it's also allowed to
     1441    * ignore these values.
     1442    */
     1443   uint32_t               first;
     1444   uint32_t               last;
     1445} SVGA3dArrayRangeHint;
     1446
     1447typedef
     1448struct {
     1449   /*
     1450    * Define the origin and shape of a vertex or index array. Both
     1451    * 'offset' and 'stride' are in bytes. The provided surface will be
     1452    * reinterpreted as a flat array of bytes in the same format used
     1453    * by surface DMA operations. To avoid unnecessary conversions, the
     1454    * surface should be created with the SVGA3D_BUFFER format.
     1455    *
     1456    * Index 0 in the array starts 'offset' bytes into the surface.
     1457    * Index 1 begins at byte 'offset + stride', etc. Array indices may
     1458    * not be negative.
     1459    */
     1460   uint32_t               surfaceId;
     1461   uint32_t               offset;
     1462   uint32_t               stride;
     1463} SVGA3dArray;
     1464
     1465typedef
     1466struct {
     1467   /*
     1468    * Describe a vertex array's data type, and define how it is to be
     1469    * used by the fixed function pipeline or the vertex shader. It
     1470    * isn't useful to have two VertexDecls with the same
     1471    * VertexArrayIdentity in one draw call.
     1472    */
     1473   SVGA3dDeclType       type;
     1474   SVGA3dDeclMethod     method;
     1475   SVGA3dDeclUsage      usage;
     1476   uint32_t               usageIndex;
     1477} SVGA3dVertexArrayIdentity;
     1478
     1479typedef
     1480struct {
     1481   SVGA3dVertexArrayIdentity  identity;
     1482   SVGA3dArray                array;
     1483   SVGA3dArrayRangeHint       rangeHint;
     1484} SVGA3dVertexDecl;
     1485
     1486typedef
     1487struct {
     1488   /*
     1489    * Define a group of primitives to render, from sequential indices.
     1490    *
     1491    * The value of 'primitiveType' and 'primitiveCount' imply the
     1492    * total number of vertices that will be rendered.
     1493    */
     1494   SVGA3dPrimitiveType  primType;
     1495   uint32_t               primitiveCount;
     1496
     1497   /*
     1498    * Optional index buffer. If indexArray.surfaceId is
     1499    * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
     1500    * without an index buffer is identical to rendering with an index
     1501    * buffer containing the sequence [0, 1, 2, 3, ...].
     1502    *
     1503    * If an index buffer is in use, indexWidth specifies the width in
     1504    * bytes of each index value. It must be less than or equal to
     1505    * indexArray.stride.
     1506    *
     1507    * (Currently, the SVGA3D device requires index buffers to be tightly
     1508    * packed. In other words, indexWidth == indexArray.stride)
     1509    */
     1510   SVGA3dArray          indexArray;
     1511   uint32_t               indexWidth;
     1512
     1513   /*
     1514    * Optional index bias. This number is added to all indices from
     1515    * indexArray before they are used as vertex array indices. This
     1516    * can be used in multiple ways:
     1517    *
     1518    *  - When not using an indexArray, this bias can be used to
     1519    *    specify where in the vertex arrays to begin rendering.
     1520    *
     1521    *  - A positive number here is equivalent to increasing the
     1522    *    offset in each vertex array.
     1523    *
     1524    *  - A negative number can be used to render using a small
     1525    *    vertex array and an index buffer that contains large
     1526    *    values. This may be used by some applications that
     1527    *    crop a vertex buffer without modifying their index
     1528    *    buffer.
     1529    *
     1530    * Note that rendering with a negative bias value may be slower and
     1531    * use more memory than rendering with a positive or zero bias.
     1532    */
     1533   int32_t                indexBias;
     1534} SVGA3dPrimitiveRange;
     1535
     1536typedef
     1537struct {
     1538   uint32_t               cid;
     1539   uint32_t               numVertexDecls;
     1540   uint32_t               numRanges;
     1541
     1542   /*
     1543    * There are two variable size arrays after the
     1544    * SVGA3dCmdDrawPrimitives structure. In order,
     1545    * they are:
     1546    *
     1547    * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
     1548    *    SVGA3D_MAX_VERTEX_ARRAYS;
     1549    * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
     1550    *    SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
     1551    * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
     1552    *    the frequency divisor for the corresponding vertex decl).
     1553    */
     1554} SVGA3dCmdDrawPrimitives;      /* SVGA_3D_CMD_DRAWPRIMITIVES */
     1555
     1556typedef
     1557struct {
     1558   uint32_t                   stage;
     1559   SVGA3dTextureStateName   name;
     1560   union {
     1561      uint32_t                value;
     1562      float                 floatValue;
     1563   };
     1564} SVGA3dTextureState;
     1565
     1566typedef
     1567struct {
     1568   uint32_t               cid;
     1569   /* Followed by variable number of SVGA3dTextureState structures */
     1570} SVGA3dCmdSetTextureState;      /* SVGA_3D_CMD_SETTEXTURESTATE */
     1571
     1572typedef
     1573struct {
     1574   uint32_t                   cid;
     1575   SVGA3dTransformType      type;
     1576   float                    matrix[16];
     1577} SVGA3dCmdSetTransform;          /* SVGA_3D_CMD_SETTRANSFORM */
     1578
     1579typedef
     1580struct {
     1581   float                min;
     1582   float                max;
     1583} SVGA3dZRange;
     1584
     1585typedef
     1586struct {
     1587   uint32_t               cid;
     1588   SVGA3dZRange         zRange;
     1589} SVGA3dCmdSetZRange;             /* SVGA_3D_CMD_SETZRANGE */
     1590
     1591typedef
     1592struct {
     1593   float                diffuse[4];
     1594   float                ambient[4];
     1595   float                specular[4];
     1596   float                emissive[4];
     1597   float                shininess;
     1598} SVGA3dMaterial;
     1599
     1600typedef
     1601struct {
     1602   uint32_t               cid;
     1603   SVGA3dFace           face;
     1604   SVGA3dMaterial       material;
     1605} SVGA3dCmdSetMaterial;           /* SVGA_3D_CMD_SETMATERIAL */
     1606
     1607typedef
     1608struct {
     1609   uint32_t               cid;
     1610   uint32_t               index;
     1611   SVGA3dLightData      data;
     1612} SVGA3dCmdSetLightData;           /* SVGA_3D_CMD_SETLIGHTDATA */
     1613
     1614typedef
     1615struct {
     1616   uint32_t               cid;
     1617   uint32_t               index;
     1618   uint32_t               enabled;
     1619} SVGA3dCmdSetLightEnabled;      /* SVGA_3D_CMD_SETLIGHTENABLED */
     1620
     1621typedef
     1622struct {
     1623   uint32_t               cid;
     1624   SVGA3dRect           rect;
     1625} SVGA3dCmdSetViewport;           /* SVGA_3D_CMD_SETVIEWPORT */
     1626
     1627typedef
     1628struct {
     1629   uint32_t               cid;
     1630   SVGA3dRect           rect;
     1631} SVGA3dCmdSetScissorRect;         /* SVGA_3D_CMD_SETSCISSORRECT */
     1632
     1633typedef
     1634struct {
     1635   uint32_t               cid;
     1636   uint32_t               index;
     1637   float                plane[4];
     1638} SVGA3dCmdSetClipPlane;           /* SVGA_3D_CMD_SETCLIPPLANE */
     1639
     1640typedef
     1641struct {
     1642   uint32_t               cid;
     1643   uint32_t               shid;
     1644   SVGA3dShaderType     type;
     1645   /* Followed by variable number of DWORDs for shader bycode */
     1646} SVGA3dCmdDefineShader;           /* SVGA_3D_CMD_SHADER_DEFINE */
     1647
     1648typedef
     1649struct {
     1650   uint32_t               cid;
     1651   uint32_t               shid;
     1652   SVGA3dShaderType     type;
     1653} SVGA3dCmdDestroyShader;         /* SVGA_3D_CMD_SHADER_DESTROY */
     1654
     1655typedef
     1656struct {
     1657   uint32_t                  cid;
     1658   uint32_t                  reg;     /* register number */
     1659   SVGA3dShaderType        type;
     1660   SVGA3dShaderConstType   ctype;
     1661   uint32_t                  values[4];
     1662} SVGA3dCmdSetShaderConst;        /* SVGA_3D_CMD_SET_SHADER_CONST */
     1663
     1664typedef
     1665struct {
     1666   uint32_t               cid;
     1667   SVGA3dShaderType     type;
     1668   uint32_t               shid;
     1669} SVGA3dCmdSetShader;             /* SVGA_3D_CMD_SET_SHADER */
     1670
     1671typedef
     1672struct {
     1673   uint32_t               cid;
     1674   SVGA3dQueryType      type;
     1675} SVGA3dCmdBeginQuery;           /* SVGA_3D_CMD_BEGIN_QUERY */
     1676
     1677typedef
     1678struct {
     1679   uint32_t               cid;
     1680   SVGA3dQueryType      type;
     1681   SVGAGuestPtr         guestResult;  /* Points to an SVGA3dQueryResult structure */
     1682} SVGA3dCmdEndQuery;                  /* SVGA_3D_CMD_END_QUERY */
     1683
     1684typedef
     1685struct {
     1686   uint32_t               cid;          /* Same parameters passed to END_QUERY */
     1687   SVGA3dQueryType      type;
     1688   SVGAGuestPtr         guestResult;
     1689} SVGA3dCmdWaitForQuery;              /* SVGA_3D_CMD_WAIT_FOR_QUERY */
     1690
     1691typedef
     1692struct {
     1693   uint32_t               totalSize;    /* Set by guest before query is ended. */
     1694   SVGA3dQueryState     state;        /* Set by host or guest. See SVGA3dQueryState. */
     1695   union {                            /* Set by host on exit from PENDING state */
     1696      uint32_t            result32;
     1697   };
     1698} SVGA3dQueryResult;
     1699
     1700/*
     1701 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
     1702 *
     1703 *    This is a blit from an SVGA3D surface to a Screen Object. Just
     1704 *    like GMR-to-screen blits, this blit may be directed at a
     1705 *    specific screen or to the virtual coordinate space.
     1706 *
     1707 *    The blit copies from a rectangular region of an SVGA3D surface
     1708 *    image to a rectangular region of a screen or screens.
     1709 *
     1710 *    This command takes an optional variable-length list of clipping
     1711 *    rectangles after the body of the command. If no rectangles are
     1712 *    specified, there is no clipping region. The entire destRect is
     1713 *    drawn to. If one or more rectangles are included, they describe
     1714 *    a clipping region. The clip rectangle coordinates are measured
     1715 *    relative to the top-left corner of destRect.
     1716 *
     1717 *    This clipping region serves multiple purposes:
     1718 *
     1719 *      - It can be used to perform an irregularly shaped blit more
     1720 *        efficiently than by issuing many separate blit commands.
     1721 *
     1722 *      - It is equivalent to allowing blits with non-integer
     1723 *        source coordinates. You could blit just one half-pixel
     1724 *        of a source, for example, by specifying a larger
     1725 *        destination rectangle than you need, then removing
     1726 *        part of it using a clip rectangle.
     1727 *
     1728 * Availability:
     1729 *    SVGA_FIFO_CAP_SCREEN_OBJECT
     1730 *
     1731 * Limitations:
     1732 *
     1733 *    - Currently, no backend supports blits from a mipmap or face
     1734 *      other than the first one.
     1735 */
     1736
     1737typedef
     1738struct {
     1739   SVGA3dSurfaceImageId srcImage;
     1740   SVGASignedRect       srcRect;
     1741   uint32_t               destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
     1742   SVGASignedRect       destRect;     /* Supports scaling if src/rest different size */
     1743   /* Clipping: zero or more SVGASignedRects follow */
     1744} SVGA3dCmdBlitSurfaceToScreen;         /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
     1745
     1746typedef
     1747struct {
     1748   uint32_t               sid;
     1749   SVGA3dTextureFilter  filter;
     1750} SVGA3dCmdGenerateMipmaps;             /* SVGA_3D_CMD_GENERATE_MIPMAPS */
     1751
     1752
     1753/*
     1754 * Capability query index.
     1755 *
     1756 * Notes:
     1757 *
     1758 *   1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
     1759 *      fixed-function texture units available. Each of these units
     1760 *      work in both FFP and Shader modes, and they support texture
     1761 *      transforms and texture coordinates. The host may have additional
     1762 *      texture image units that are only usable with shaders.
     1763 *
     1764 *   2. The BUFFER_FORMAT capabilities are deprecated, and they always
     1765 *      return TRUE. Even on physical hardware that does not support
     1766 *      these formats natively, the SVGA3D device will provide an emulation
     1767 *      which should be invisible to the guest OS.
     1768 *
     1769 *      In general, the SVGA3D device should support any operation on
     1770 *      any surface format, it just may perform some of these
     1771 *      operations in software depending on the capabilities of the
     1772 *      available physical hardware.
     1773 *
     1774 *      XXX: In the future, we will add capabilities that describe in
     1775 *      detail what formats are supported in hardware for what kinds
     1776 *      of operations.
     1777 */
     1778
     1779typedef enum {
     1780   SVGA3D_DEVCAP_3D                                = 0,
     1781   SVGA3D_DEVCAP_MAX_LIGHTS                        = 1,
     1782   SVGA3D_DEVCAP_MAX_TEXTURES                      = 2,  /* See note (1) */
     1783   SVGA3D_DEVCAP_MAX_CLIP_PLANES                   = 3,
     1784   SVGA3D_DEVCAP_VERTEX_SHADER_VERSION             = 4,
     1785   SVGA3D_DEVCAP_VERTEX_SHADER                     = 5,
     1786   SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION           = 6,
     1787   SVGA3D_DEVCAP_FRAGMENT_SHADER                   = 7,
     1788   SVGA3D_DEVCAP_MAX_RENDER_TARGETS                = 8,
     1789   SVGA3D_DEVCAP_S23E8_TEXTURES                    = 9,
     1790   SVGA3D_DEVCAP_S10E5_TEXTURES                    = 10,
     1791   SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND             = 11,
     1792   SVGA3D_DEVCAP_D16_BUFFER_FORMAT                 = 12, /* See note (2) */
     1793   SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT               = 13, /* See note (2) */
     1794   SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT               = 14, /* See note (2) */
     1795   SVGA3D_DEVCAP_QUERY_TYPES                       = 15,
     1796   SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING         = 16,
     1797   SVGA3D_DEVCAP_MAX_POINT_SIZE                    = 17,
     1798   SVGA3D_DEVCAP_MAX_SHADER_TEXTURES               = 18,
     1799   SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH                 = 19,
     1800   SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT                = 20,
     1801   SVGA3D_DEVCAP_MAX_VOLUME_EXTENT                 = 21,
     1802   SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT                = 22,
     1803   SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO          = 23,
     1804   SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY            = 24,
     1805   SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT               = 25,
     1806   SVGA3D_DEVCAP_MAX_VERTEX_INDEX                  = 26,
     1807   SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS    = 27,
     1808   SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS  = 28,
     1809   SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS           = 29,
     1810   SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS         = 30,
     1811   SVGA3D_DEVCAP_TEXTURE_OPS                       = 31,
     1812   SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8               = 32,
     1813   SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8               = 33,
     1814   SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10            = 34,
     1815   SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5               = 35,
     1816   SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5               = 36,
     1817   SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4               = 37,
     1818   SVGA3D_DEVCAP_SURFACEFMT_R5G6B5                 = 38,
     1819   SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16            = 39,
     1820   SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8      = 40,
     1821   SVGA3D_DEVCAP_SURFACEFMT_ALPHA8                 = 41,
     1822   SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8             = 42,
     1823   SVGA3D_DEVCAP_SURFACEFMT_Z_D16                  = 43,
     1824   SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8                = 44,
     1825   SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8                = 45,
     1826   SVGA3D_DEVCAP_SURFACEFMT_DXT1                   = 46,
     1827   SVGA3D_DEVCAP_SURFACEFMT_DXT2                   = 47,
     1828   SVGA3D_DEVCAP_SURFACEFMT_DXT3                   = 48,
     1829   SVGA3D_DEVCAP_SURFACEFMT_DXT4                   = 49,
     1830   SVGA3D_DEVCAP_SURFACEFMT_DXT5                   = 50,
     1831   SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8           = 51,
     1832   SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10            = 52,
     1833   SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8               = 53,
     1834   SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8               = 54,
     1835   SVGA3D_DEVCAP_SURFACEFMT_CxV8U8                 = 55,
     1836   SVGA3D_DEVCAP_SURFACEFMT_R_S10E5                = 56,
     1837   SVGA3D_DEVCAP_SURFACEFMT_R_S23E8                = 57,
     1838   SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5               = 58,
     1839   SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8               = 59,
     1840   SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5             = 60,
     1841   SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8             = 61,
     1842   SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES        = 63,
     1843
     1844   /*
     1845    * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
     1846    * render targets.  This does no include the depth or stencil targets.
     1847    */
     1848   SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS   = 64,
     1849
     1850   SVGA3D_DEVCAP_SURFACEFMT_V16U16                 = 65,
     1851   SVGA3D_DEVCAP_SURFACEFMT_G16R16                 = 66,
     1852   SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16           = 67,
     1853   SVGA3D_DEVCAP_SURFACEFMT_UYVY                   = 68,
     1854   SVGA3D_DEVCAP_SURFACEFMT_YUY2                   = 69,
     1855   SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES    = 70,
     1856   SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES       = 71,
     1857   SVGA3D_DEVCAP_ALPHATOCOVERAGE                   = 72,
     1858   SVGA3D_DEVCAP_SUPERSAMPLE                       = 73,
     1859   SVGA3D_DEVCAP_AUTOGENMIPMAPS                    = 74,
     1860   SVGA3D_DEVCAP_SURFACEFMT_NV12                   = 75,
     1861   SVGA3D_DEVCAP_SURFACEFMT_AYUV                   = 76,
     1862
     1863   /*
     1864    * This is the maximum number of SVGA context IDs that the guest
     1865    * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
     1866    */
     1867   SVGA3D_DEVCAP_MAX_CONTEXT_IDS                   = 77,
     1868
     1869   /*
     1870    * This is the maximum number of SVGA surface IDs that the guest
     1871    * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
     1872    */
     1873   SVGA3D_DEVCAP_MAX_SURFACE_IDS                   = 78,
     1874
     1875   SVGA3D_DEVCAP_SURFACEFMT_Z_DF16                 = 79,
     1876   SVGA3D_DEVCAP_SURFACEFMT_Z_DF24                 = 80,
     1877   SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT            = 81,
     1878
     1879   SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM              = 82,
     1880   SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM              = 83,
     1881
     1882   /*
     1883    * Don't add new caps into the previous section; the values in this
     1884    * enumeration must not change. You can put new values right before
     1885    * SVGA3D_DEVCAP_MAX.
     1886    */
     1887   SVGA3D_DEVCAP_MAX                                  /* This must be the last index. */
     1888} SVGA3dDevCapIndex;
     1889
     1890typedef union {
     1891   bool   b;
     1892   uint32_t u;
     1893   int32_t  i;
     1894   float  f;
     1895} SVGA3dDevCapResult;
    541896
    551897#endif /* _SVGA3D_REG_H_ */
    56 

  • trunk/src/VBox/Devices/Graphics/vmsvga/svga_escape.h

    r49983 r52970  
     1/**********************************************************
     2 * Copyright 2007-2009 VMware, Inc.  All rights reserved.
     3 *
     4 * Permission is hereby granted, free of charge, to any person
     5 * obtaining a copy of this software and associated documentation
     6 * files (the "Software"), to deal in the Software without
     7 * restriction, including without limitation the rights to use, copy,
     8 * modify, merge, publish, distribute, sublicense, and/or sell copies
     9 * of the Software, and to permit persons to whom the Software is
     10 * furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be
     13 * included in all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     22 * SOFTWARE.
     23 *
     24 **********************************************************/
     25
    126/*
    2  * SVGA escape commands
     27 * svga_escape.h --
     28 *
     29 *    Definitions for our own (vendor-specific) SVGA Escape commands.
    330 */
    431
    … …  
    633#define _SVGA_ESCAPE_H_
    734
     35
     36/*
     37 * Namespace IDs for the escape command
     38 */
     39
    840#define SVGA_ESCAPE_NSID_VMWARE 0x00000000
     41#define SVGA_ESCAPE_NSID_DEVEL  0xFFFFFFFF
    942
    1043
     44/*
     45 * Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to
     46 * the first DWORD of escape data (after the nsID and size). As a
     47 * guideline we're using the high word and low word as a major and
     48 * minor command number, respectively.
     49 *
     50 * Major command number allocation:
     51 *
     52 *   0000: Reserved
     53 *   0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h)
     54 *   0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h)
     55 *   0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h)
     56 */
     57
     58#define SVGA_ESCAPE_VMWARE_MAJOR_MASK  0xFFFF0000
     59
     60
     61/*
     62 * SVGA Hint commands.
     63 *
     64 * These escapes let the SVGA driver provide optional information to
     65 * he host about the state of the guest or guest applications. The
     66 * host can use these hints to make user interface or performance
     67 * decisions.
     68 *
     69 * Notes:
     70 *
     71 *   - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests
     72 *     that use the SVGA Screen Object extension. Instead of sending
     73 *     this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your
     74 *     Screen Object.
     75 */
     76
     77#define SVGA_ESCAPE_VMWARE_HINT               0x00030000
     78#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN    0x00030001  // Deprecated
     79
     80typedef
     81struct {
     82   uint32_t command;
     83   uint32_t fullscreen;
     84   struct {
     85      int32_t x, y;
     86   } monitorPosition;
     87} SVGAEscapeHintFullscreen;
     88
    1189#endif /* _SVGA_ESCAPE_H_ */

  • trunk/src/VBox/Devices/Graphics/vmsvga/svga_overlay.h

    r49983 r52970  
    1 /*
    2  * VMware SVGA video overlay definitions
     1/**********************************************************
     2 * Copyright 2007-2009 VMware, Inc.  All rights reserved.
     3 *
     4 * Permission is hereby granted, free of charge, to any person
     5 * obtaining a copy of this software and associated documentation
     6 * files (the "Software"), to deal in the Software without
     7 * restriction, including without limitation the rights to use, copy,
     8 * modify, merge, publish, distribute, sublicense, and/or sell copies
     9 * of the Software, and to permit persons to whom the Software is
     10 * furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be
     13 * included in all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     22 * SOFTWARE.
     23 *
     24 **********************************************************/
     25
     26/*
     27 * svga_overlay.h --
     28 *
     29 *    Definitions for video-overlay support.
    330 */
    431
    … …  
    633#define _SVGA_OVERLAY_H_
    734
     35#include "svga_reg.h"
     36
     37/*
     38 * Video formats we support
     39 */
     40
     41#define VMWARE_FOURCC_YV12 0x32315659 // 'Y' 'V' '1' '2'
     42#define VMWARE_FOURCC_YUY2 0x32595559 // 'Y' 'U' 'Y' '2'
     43#define VMWARE_FOURCC_UYVY 0x59565955 // 'U' 'Y' 'V' 'Y'
     44
     45typedef enum {
     46   SVGA_OVERLAY_FORMAT_INVALID = 0,
     47   SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
     48   SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
     49   SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY
     50} SVGAOverlayFormat;
     51
     52#define SVGA_VIDEO_COLORKEY_MASK             0x00ffffff
     53
     54#define SVGA_ESCAPE_VMWARE_VIDEO             0x00020000
     55
    856#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS    0x00020001
     57        /* FIFO escape layout:
     58         * Type, Stream Id, (Register Id, Value) pairs */
     59
    960#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH       0x00020002
    10 
    11 typedef struct SVGAEscapeVideoSetRegs
    12 {
    13    struct
    14    {
     61        /* FIFO escape layout:
     62         * Type, Stream Id */
     63
     64typedef
     65struct SVGAEscapeVideoSetRegs {
     66   struct {
    1567      uint32_t cmdType;
    1668      uint32_t streamId;
    1769   } header;
    1870
    19    struct
    20    {
     71   // May include zero or more items.
     72   struct {
    2173      uint32_t registerId;
    2274      uint32_t value;
    … …  
    2476} SVGAEscapeVideoSetRegs;
    2577
    26 typedef struct SVGAEscapeVideoFlush
    27 {
     78typedef
     79struct SVGAEscapeVideoFlush {
    2880   uint32_t cmdType;
    2981   uint32_t streamId;
    3082} SVGAEscapeVideoFlush;
    3183
    32 #endif /* _SVGA_OVERLAY_H_ */
     84
     85/*
     86 * Struct definitions for the video overlay commands built on
     87 * SVGAFifoCmdEscape.
     88 */
     89typedef
     90struct {
     91   uint32_t command;
     92   uint32_t overlay;
     93} SVGAFifoEscapeCmdVideoBase;
     94
     95typedef
     96struct {
     97   SVGAFifoEscapeCmdVideoBase videoCmd;
     98} SVGAFifoEscapeCmdVideoFlush;
     99
     100typedef
     101struct {
     102   SVGAFifoEscapeCmdVideoBase videoCmd;
     103   struct {
     104      uint32_t regId;
     105      uint32_t value;
     106   } items[1];
     107} SVGAFifoEscapeCmdVideoSetRegs;
     108
     109typedef
     110struct {
     111   SVGAFifoEscapeCmdVideoBase videoCmd;
     112   struct {
     113      uint32_t regId;
     114      uint32_t value;
     115   } items[SVGA_VIDEO_NUM_REGS];
     116} SVGAFifoEscapeCmdVideoSetAllRegs;
     117
     118
     119/*
     120 *----------------------------------------------------------------------
     121 *
     122 * VMwareVideoGetAttributes --
     123 *
     124 *      Computes the size, pitches and offsets for YUV frames.
     125 *
     126 * Results:
     127 *      TRUE on success; otherwise FALSE on failure.
     128 *
     129 * Side effects:
     130 *      Pitches and offsets for the given YUV frame are put in 'pitches'
     131 *      and 'offsets' respectively. They are both optional though.
     132 *
     133 *----------------------------------------------------------------------
     134 */
     135#if 0
     136static INLINE Bool
     137VMwareVideoGetAttributes(const SVGAOverlayFormat format,    // IN
     138                         uint32_t *width,                     // IN / OUT
     139                         uint32_t *height,                    // IN / OUT
     140                         uint32_t *size,                      // OUT
     141                         uint32_t *pitches,                   // OUT (optional)
     142                         uint32_t *offsets)                   // OUT (optional)
     143{
     144    int tmp;
     145
     146    *width = (*width + 1) & ~1;
     147
     148    if (offsets) {
     149        offsets[0] = 0;
     150    }
     151
     152    switch (format) {
     153    case VMWARE_FOURCC_YV12:
     154       *height = (*height + 1) & ~1;
     155       *size = (*width + 3) & ~3;
     156
     157       if (pitches) {
     158          pitches[0] = *size;
     159       }
     160
     161       *size *= *height;
     162
     163       if (offsets) {
     164          offsets[1] = *size;
     165       }
     166
     167       tmp = ((*width >> 1) + 3) & ~3;
     168
     169       if (pitches) {
     170          pitches[1] = pitches[2] = tmp;
     171       }
     172
     173       tmp *= (*height >> 1);
     174       *size += tmp;
     175
     176       if (offsets) {
     177          offsets[2] = *size;
     178       }
     179
     180       *size += tmp;
     181       break;
     182
     183    case VMWARE_FOURCC_YUY2:
     184    case VMWARE_FOURCC_UYVY:
     185       *size = *width * 2;
     186
     187       if (pitches) {
     188          pitches[0] = *size;
     189       }
     190
     191       *size *= *height;
     192       break;
     193
     194    default:
     195       return FALSE;
     196    }
     197
     198    return TRUE;
     199}
     200#endif
     201#endif // _SVGA_OVERLAY_H_

  • trunk/src/VBox/Devices/Graphics/vmsvga/svga_reg.h

    r49983 r52970  
    1 /*
    2  * VMware SVGA II hardware definitions
     1/**********************************************************
     2 * Copyright 1998-2009 VMware, Inc.  All rights reserved.
     3 *
     4 * Permission is hereby granted, free of charge, to any person
     5 * obtaining a copy of this software and associated documentation
     6 * files (the "Software"), to deal in the Software without
     7 * restriction, including without limitation the rights to use, copy,
     8 * modify, merge, publish, distribute, sublicense, and/or sell copies
     9 * of the Software, and to permit persons to whom the Software is
     10 * furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be
     13 * included in all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     22 * SOFTWARE.
     23 *
     24 **********************************************************/
     25
     26/*
     27 * svga_reg.h --
     28 *
     29 *    Virtual hardware definitions for the VMware SVGA II device.
    330 */
    431
    … …  
    633#define _SVGA_REG_H_
    734
     35/*
     36 * PCI device IDs.
     37 */
    838#define PCI_VENDOR_ID_VMWARE            0x15AD
    939#define PCI_DEVICE_ID_VMWARE_SVGA2      0x0405
    1040
    11 #define SVGA_IRQFLAG_ANY_FENCE            0x1
    12 #define SVGA_IRQFLAG_FIFO_PROGRESS        0x2
    13 #define SVGA_IRQFLAG_FENCE_GOAL           0x4
     41/*
     42 * SVGA_REG_ENABLE bit definitions.
     43 */
     44#define SVGA_REG_ENABLE_DISABLE     0
     45#define SVGA_REG_ENABLE_ENABLE      1
     46#define SVGA_REG_ENABLE_HIDE        2
     47#define SVGA_REG_ENABLE_ENABLE_HIDE (SVGA_REG_ENABLE_ENABLE |\
     48                                     SVGA_REG_ENABLE_HIDE)
     49
     50/*
     51 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
     52 * cursor bypass mode. This is still supported, but no new guest
     53 * drivers should use it.
     54 */
     55#define SVGA_CURSOR_ON_HIDE            0x0   /* Must be 0 to maintain backward compatibility */
     56#define SVGA_CURSOR_ON_SHOW            0x1   /* Must be 1 to maintain backward compatibility */
     57#define SVGA_CURSOR_ON_REMOVE_FROM_FB  0x2   /* Remove the cursor from the framebuffer because we need to see what's under it */
     58#define SVGA_CURSOR_ON_RESTORE_TO_FB   0x3   /* Put the cursor back in the framebuffer so the user can see it */
     59
     60/*
     61 * The maximum framebuffer size that can traced for e.g. guests in VESA mode.
     62 * The changeMap in the monitor is proportional to this number. Therefore, we'd
     63 * like to keep it as small as possible to reduce monitor overhead (using
     64 * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
     65 * 4k!).
     66 *
     67 * NB: For compatibility reasons, this value must be greater than 0xff0000.
     68 *     See bug 335072.
     69 */
     70#define SVGA_FB_MAX_TRACEABLE_SIZE      0x1000000
    1471
    1572#define SVGA_MAX_PSEUDOCOLOR_DEPTH      8
    … …  
    2077#define SVGA_MAKE_ID(ver)  (SVGA_MAGIC << 8 | (ver))
    2178
     79/* Version 2 let the address of the frame buffer be unsigned on Win32 */
    2280#define SVGA_VERSION_2     2
    2381#define SVGA_ID_2          SVGA_MAKE_ID(SVGA_VERSION_2)
    2482
     83/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
     84   PALETTE_BASE has moved */
    2585#define SVGA_VERSION_1     1
    2686#define SVGA_ID_1          SVGA_MAKE_ID(SVGA_VERSION_1)
    2787
     88/* Version 0 is the initial version */
    2889#define SVGA_VERSION_0     0
    2990#define SVGA_ID_0          SVGA_MAKE_ID(SVGA_VERSION_0)
    3091
     92/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
    3193#define SVGA_ID_INVALID    0xFFFFFFFF
    3294
     95/* Port offsets, relative to BAR0 */
    3396#define SVGA_INDEX_PORT         0x0
    3497#define SVGA_VALUE_PORT         0x1
    … …  
    3699#define SVGA_IRQSTATUS_PORT     0x8
    37100
    38 #define SVGA_IRQFLAG_ANY_FENCE            0x1
    39 #define SVGA_IRQFLAG_FIFO_PROGRESS        0x2
    40 #define SVGA_IRQFLAG_FENCE_GOAL           0x4
    41 
    42 enum
    43 {
     101/*
     102 * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
     103 *
     104 * Interrupts are only supported when the
     105 * SVGA_CAP_IRQMASK capability is present.
     106 */
     107#define SVGA_IRQFLAG_ANY_FENCE            0x1    /* Any fence was passed */
     108#define SVGA_IRQFLAG_FIFO_PROGRESS        0x2    /* Made forward progress in the FIFO */
     109#define SVGA_IRQFLAG_FENCE_GOAL           0x4    /* SVGA_FIFO_FENCE_GOAL reached */
     110
     111/*
     112 * Registers
     113 */
     114
     115enum {
    44116   SVGA_REG_ID = 0,
    45117   SVGA_REG_ENABLE = 1,
    … …  
    49121   SVGA_REG_MAX_HEIGHT = 5,
    50122   SVGA_REG_DEPTH = 6,
    51    SVGA_REG_BITS_PER_PIXEL = 7,
     123   SVGA_REG_BITS_PER_PIXEL = 7,       /* Current bpp in the guest */
    52124   SVGA_REG_PSEUDOCOLOR = 8,
    53125   SVGA_REG_RED_MASK = 9,
    … …  
    55127   SVGA_REG_BLUE_MASK = 11,
    56128   SVGA_REG_BYTES_PER_LINE = 12,
    57    SVGA_REG_FB_START = 13,
     129   SVGA_REG_FB_START = 13,            /* (Deprecated) */
    58130   SVGA_REG_FB_OFFSET = 14,
    59131   SVGA_REG_VRAM_SIZE = 15,
    60132   SVGA_REG_FB_SIZE = 16,
     133
     134   /* ID 0 implementation only had the above registers, then the palette */
     135
    61136   SVGA_REG_CAPABILITIES = 17,
    62    SVGA_REG_MEM_START = 18,
     137   SVGA_REG_MEM_START = 18,           /* (Deprecated) */
    63138   SVGA_REG_MEM_SIZE = 19,
    64    SVGA_REG_CONFIG_DONE = 20,
    65    SVGA_REG_SYNC = 21,
    66    SVGA_REG_BUSY = 22,
    67    SVGA_REG_GUEST_ID = 23,
    68    SVGA_REG_CURSOR_ID = 24,
    69    SVGA_REG_CURSOR_X = 25,
    70    SVGA_REG_CURSOR_Y = 26,
    71    SVGA_REG_CURSOR_ON = 27,
    72    SVGA_REG_HOST_BITS_PER_PIXEL = 28,
    73    SVGA_REG_SCRATCH_SIZE = 29,
    74    SVGA_REG_MEM_REGS = 30,
    75    SVGA_REG_NUM_DISPLAYS = 31,
    76    SVGA_REG_PITCHLOCK = 32,
    77    SVGA_REG_IRQMASK = 33,
    78    SVGA_REG_NUM_GUEST_DISPLAYS = 34,
    79    SVGA_REG_DISPLAY_ID = 35,
    80    SVGA_REG_DISPLAY_IS_PRIMARY = 36,
    81    SVGA_REG_DISPLAY_POSITION_X = 37,
    82    SVGA_REG_DISPLAY_POSITION_Y = 38,
    83    SVGA_REG_DISPLAY_WIDTH = 39,
    84    SVGA_REG_DISPLAY_HEIGHT = 40,
     139   SVGA_REG_CONFIG_DONE = 20,         /* Set when memory area configured */
     140   SVGA_REG_SYNC = 21,                /* See "FIFO Synchronization Registers" */
     141   SVGA_REG_BUSY = 22,                /* See "FIFO Synchronization Registers" */
     142   SVGA_REG_GUEST_ID = 23,            /* Set guest OS identifier */
     143   SVGA_REG_CURSOR_ID = 24,           /* (Deprecated) */
     144   SVGA_REG_CURSOR_X = 25,            /* (Deprecated) */
     145   SVGA_REG_CURSOR_Y = 26,            /* (Deprecated) */
     146   SVGA_REG_CURSOR_ON = 27,           /* (Deprecated) */
     147   SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
     148   SVGA_REG_SCRATCH_SIZE = 29,        /* Number of scratch registers */
     149   SVGA_REG_MEM_REGS = 30,            /* Number of FIFO registers */
     150   SVGA_REG_NUM_DISPLAYS = 31,        /* (Deprecated) */
     151   SVGA_REG_PITCHLOCK = 32,           /* Fixed pitch for all modes */
     152   SVGA_REG_IRQMASK = 33,             /* Interrupt mask */
     153
     154   /* Legacy multi-monitor support */
     155   SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
     156   SVGA_REG_DISPLAY_ID = 35,        /* Display ID for the following display attributes */
     157   SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
     158   SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
     159   SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
     160   SVGA_REG_DISPLAY_WIDTH = 39,     /* The display's width */
     161   SVGA_REG_DISPLAY_HEIGHT = 40,    /* The display's height */
     162
     163   /* See "Guest memory regions" below. */
    85164   SVGA_REG_GMR_ID = 41,
    86165   SVGA_REG_GMR_DESCRIPTOR = 42,
    87166   SVGA_REG_GMR_MAX_IDS = 43,
    88167   SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
    89    SVGA_REG_TRACES = 45,
    90    SVGA_REG_GMRS_MAX_PAGES = 46,
    91    SVGA_REG_MEMORY_SIZE = 47,
    92    SVGA_REG_TOP = 48,
    93    SVGA_PALETTE_BASE = 1024,
     168
     169   SVGA_REG_TRACES = 45,            /* Enable trace-based updates even when FIFO is on */
     170   SVGA_REG_GMRS_MAX_PAGES = 46,    /* Maximum number of 4KB pages for all GMRs */
     171   SVGA_REG_MEMORY_SIZE = 47,       /* Total dedicated device memory excluding FIFO */
     172   SVGA_REG_TOP = 48,               /* Must be 1 more than the last register */
     173
     174   SVGA_PALETTE_BASE = 1024,        /* Base of SVGA color map */
     175   /* Next 768 (== 256*3) registers exist for colormap */
     176
    94177   SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
     178                                    /* Base of scratch registers */
     179   /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
     180      First 4 are reserved for VESA BIOS Extension; any remaining are for
     181      the use of the current SVGA driver. */
    95182};
    96183
    97 enum
    98 {
     184
     185/*
     186 * Guest memory regions (GMRs):
     187 *
     188 * This is a new memory mapping feature available in SVGA devices
     189 * which have the SVGA_CAP_GMR bit set. Previously, there were two
     190 * fixed memory regions available with which to share data between the
     191 * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
     192 * are our name for an extensible way of providing arbitrary DMA
     193 * buffers for use between the driver and the SVGA device. They are a
     194 * new alternative to framebuffer memory, usable for both 2D and 3D
     195 * graphics operations.
     196 *
     197 * Since GMR mapping must be done synchronously with guest CPU
     198 * execution, we use a new pair of SVGA registers:
     199 *
     200 *   SVGA_REG_GMR_ID --
     201 *
     202 *     Read/write.
     203 *     This register holds the 32-bit ID (a small positive integer)
     204 *     of a GMR to create, delete, or redefine. Writing this register
     205 *     has no side-effects.
     206 *
     207 *   SVGA_REG_GMR_DESCRIPTOR --
     208 *
     209 *     Write-only.
     210 *     Writing this register will create, delete, or redefine the GMR
     211 *     specified by the above ID register. If this register is zero,
     212 *     the GMR is deleted. Any pointers into this GMR (including those
     213 *     currently being processed by FIFO commands) will be
     214 *     synchronously invalidated.
     215 *
     216 *     If this register is nonzero, it must be the physical page
     217 *     number (PPN) of a data structure which describes the physical
     218 *     layout of the memory region this GMR should describe. The
     219 *     descriptor structure will be read synchronously by the SVGA
     220 *     device when this register is written. The descriptor need not
     221 *     remain allocated for the lifetime of the GMR.
     222 *
     223 *     The guest driver should write SVGA_REG_GMR_ID first, then
     224 *     SVGA_REG_GMR_DESCRIPTOR.
     225 *
     226 *   SVGA_REG_GMR_MAX_IDS --
     227 *
     228 *     Read-only.
     229 *     The SVGA device may choose to support a maximum number of
     230 *     user-defined GMR IDs. This register holds the number of supported
     231 *     IDs. (The maximum supported ID plus 1)
     232 *
     233 *   SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
     234 *
     235 *     Read-only.
     236 *     The SVGA device may choose to put a limit on the total number
     237 *     of SVGAGuestMemDescriptor structures it will read when defining
     238 *     a single GMR.
     239 *
     240 * The descriptor structure is an array of SVGAGuestMemDescriptor
     241 * structures. Each structure may do one of three things:
     242 *
     243 *   - Terminate the GMR descriptor list.
     244 *     (ppn==0, numPages==0)
     245 *
     246 *   - Add a PPN or range of PPNs to the GMR's virtual address space.
     247 *     (ppn != 0, numPages != 0)
     248 *
     249 *   - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
     250 *     support multi-page GMR descriptor tables without forcing the
     251 *     driver to allocate physically contiguous memory.
     252 *     (ppn != 0, numPages == 0)
     253 *
     254 * Note that each physical page of SVGAGuestMemDescriptor structures
     255 * can describe at least 2MB of guest memory. If the driver needs to
     256 * use more than one page of descriptor structures, it must use one of
     257 * its SVGAGuestMemDescriptors to point to an additional page.  The
     258 * device will never automatically cross a page boundary.
     259 *
     260 * Once the driver has described a GMR, it is immediately available
     261 * for use via any FIFO command that uses an SVGAGuestPtr structure.
     262 * These pointers include a GMR identifier plus an offset into that
     263 * GMR.
     264 *
     265 * The driver must check the SVGA_CAP_GMR bit before using the GMR
     266 * registers.
     267 */
     268
     269/*
     270 * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
     271 * memory as well.  In the future, these IDs could even be used to
     272 * allow legacy memory regions to be redefined by the guest as GMRs.
     273 *
     274 * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
     275 * is being phased out. Please try to use user-defined GMRs whenever
     276 * possible.
     277 */
     278#define SVGA_GMR_NULL         ((uint32_t) -1)
     279#define SVGA_GMR_FRAMEBUFFER  ((uint32_t) -2)  // Guest Framebuffer (GFB)
     280
     281typedef
     282struct SVGAGuestMemDescriptor {
     283   uint32_t ppn;
     284   uint32_t numPages;
     285} SVGAGuestMemDescriptor;
     286
     287typedef
     288struct SVGAGuestPtr {
     289   uint32_t gmrId;
     290   uint32_t offset;
     291} SVGAGuestPtr;
     292
     293
     294/*
     295 * SVGAGMRImageFormat --
     296 *
     297 *    This is a packed representation of the source 2D image format
     298 *    for a GMR-to-screen blit. Currently it is defined as an encoding
     299 *    of the screen's color depth and bits-per-pixel, however, 16 bits
     300 *    are reserved for future use to identify other encodings (such as
     301 *    RGBA or higher-precision images).
     302 *
     303 *    Currently supported formats:
     304 *
     305 *       bpp depth  Format Name
     306 *       --- -----  -----------
     307 *        32    24  32-bit BGRX
     308 *        24    24  24-bit BGR
     309 *        16    16  RGB 5-6-5
     310 *        16    15  RGB 5-5-5
     311 *
     312 */
     313
     314typedef
     315struct SVGAGMRImageFormat {
     316   union {
     317      struct {
     318         uint32_t bitsPerPixel : 8;
     319         uint32_t colorDepth   : 8;
     320         uint32_t reserved     : 16;  // Must be zero
     321      } s;
     322
     323      uint32_t value;
     324   };
     325} SVGAGMRImageFormat;
     326
     327typedef
     328struct SVGAGuestImage {
     329   SVGAGuestPtr         ptr;
     330
     331   /*
     332    * A note on interpretation of pitch: This value of pitch is the
     333    * number of bytes between vertically adjacent image
     334    * blocks. Normally this is the number of bytes between the first
     335    * pixel of two adjacent scanlines. With compressed textures,
     336    * however, this may represent the number of bytes between
     337    * compression blocks rather than between rows of pixels.
     338    *
     339    * XXX: Compressed textures currently must be tightly packed in guest memory.
     340    *
     341    * If the image is 1-dimensional, pitch is ignored.
     342    *
     343    * If 'pitch' is zero, the SVGA3D device calculates a pitch value
     344    * assuming each row of blocks is tightly packed.
     345    */
     346   uint32_t pitch;
     347} SVGAGuestImage;
     348
     349/*
     350 * SVGAColorBGRX --
     351 *
     352 *    A 24-bit color format (BGRX), which does not depend on the
     353 *    format of the legacy guest framebuffer (GFB) or the current
     354 *    GMRFB state.
     355 */
     356
     357typedef
     358struct SVGAColorBGRX {
     359   union {
     360      struct {
     361         uint32_t b : 8;
     362         uint32_t g : 8;
     363         uint32_t r : 8;
     364         uint32_t x : 8;  // Unused
     365      } s;
     366
     367      uint32_t value;
     368   };
     369} SVGAColorBGRX;
     370
     371
     372/*
     373 * SVGASignedRect --
     374 * SVGASignedPoint --
     375 *
     376 *    Signed rectangle and point primitives. These are used by the new
     377 *    2D primitives for drawing to Screen Objects, which can occupy a
     378 *    signed virtual coordinate space.
     379 *
     380 *    SVGASignedRect specifies a half-open interval: the (left, top)
     381 *    pixel is part of the rectangle, but the (right, bottom) pixel is
     382 *    not.
     383 */
     384
     385typedef
     386struct SVGASignedRect {
     387   int32_t  left;
     388   int32_t  top;
     389   int32_t  right;
     390   int32_t  bottom;
     391} SVGASignedRect;
     392
     393typedef
     394struct SVGASignedPoint {
     395   int32_t  x;
     396   int32_t  y;
     397} SVGASignedPoint;
     398
     399
     400/*
     401 *  Capabilities
     402 *
     403 *  Note the holes in the bitfield. Missing bits have been deprecated,
     404 *  and must not be reused. Those capabilities will never be reported
     405 *  by new versions of the SVGA device.
     406 *
     407 * SVGA_CAP_GMR2 --
     408 *    Provides asynchronous commands to define and remap guest memory
     409 *    regions.  Adds device registers SVGA_REG_GMRS_MAX_PAGES and
     410 *    SVGA_REG_MEMORY_SIZE.
     411 *
     412 * SVGA_CAP_SCREEN_OBJECT_2 --
     413 *    Allow screen object support, and require backing stores from the
     414 *    guest for each screen object.
     415 */
     416
     417#define SVGA_CAP_NONE               0x00000000
     418#define SVGA_CAP_RECT_COPY          0x00000002
     419#define SVGA_CAP_CURSOR             0x00000020
     420#define SVGA_CAP_CURSOR_BYPASS      0x00000040   // Legacy (Use Cursor Bypass 3 instead)
     421#define SVGA_CAP_CURSOR_BYPASS_2    0x00000080   // Legacy (Use Cursor Bypass 3 instead)
     422#define SVGA_CAP_8BIT_EMULATION     0x00000100
     423#define SVGA_CAP_ALPHA_CURSOR       0x00000200
     424#define SVGA_CAP_3D                 0x00004000
     425#define SVGA_CAP_EXTENDED_FIFO      0x00008000
     426#define SVGA_CAP_MULTIMON           0x00010000   // Legacy multi-monitor support
     427#define SVGA_CAP_PITCHLOCK          0x00020000
     428#define SVGA_CAP_IRQMASK            0x00040000
     429#define SVGA_CAP_DISPLAY_TOPOLOGY   0x00080000   // Legacy multi-monitor support
     430#define SVGA_CAP_GMR                0x00100000
     431#define SVGA_CAP_TRACES             0x00200000
     432#define SVGA_CAP_GMR2               0x00400000
     433#define SVGA_CAP_SCREEN_OBJECT_2    0x00800000
     434
     435
     436/*
     437 * FIFO register indices.
     438 *
     439 * The FIFO is a chunk of device memory mapped into guest physmem.  It
     440 * is always treated as 32-bit words.
     441 *
     442 * The guest driver gets to decide how to partition it between
     443 * - FIFO registers (there are always at least 4, specifying where the
     444 *   following data area is and how much data it contains; there may be
     445 *   more registers following these, depending on the FIFO protocol
     446 *   version in use)
     447 * - FIFO data, written by the guest and slurped out by the VMX.
     448 * These indices are 32-bit word offsets into the FIFO.
     449 */
     450
     451enum {
     452   /*
     453    * Block 1 (basic registers): The originally defined FIFO registers.
     454    * These exist and are valid for all versions of the FIFO protocol.
     455    */
     456
    99457   SVGA_FIFO_MIN = 0,
    100    SVGA_FIFO_MAX,
     458   SVGA_FIFO_MAX,       /* The distance from MIN to MAX must be at least 10K */
    101459   SVGA_FIFO_NEXT_CMD,
    102460   SVGA_FIFO_STOP,
     461
     462   /*
     463    * Block 2 (extended registers): Mandatory registers for the extended
     464    * FIFO.  These exist if the SVGA caps register includes
     465    * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
     466    * associated capability bit is enabled.
     467    *
     468    * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
     469    * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
     470    * This means that the guest has to test individually (in most cases
     471    * using FIFO caps) for the presence of registers after this; the VMX
     472    * can define "extended FIFO" to mean whatever it wants, and currently
     473    * won't enable it unless there's room for that set and much more.
     474    */
     475
    103476   SVGA_FIFO_CAPABILITIES = 4,
    104477   SVGA_FIFO_FLAGS,
     478   // Valid with SVGA_FIFO_CAP_FENCE:
    105479   SVGA_FIFO_FENCE,
    106    SVGA_FIFO_3D_HWVERSION,
     480
     481   /*
     482    * Block 3a (optional extended registers): Additional registers for the
     483    * extended FIFO, whose presence isn't actually implied by
     484    * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
     485    * leave room for them.
     486    *
     487    * These in block 3a, the VMX currently considers mandatory for the
     488    * extended FIFO.
     489    */
     490
     491   // Valid if exists (i.e. if extended FIFO enabled):
     492   SVGA_FIFO_3D_HWVERSION,       /* See SVGA3dHardwareVersion in svga3d_reg.h */
     493   // Valid with SVGA_FIFO_CAP_PITCHLOCK:
    107494   SVGA_FIFO_PITCHLOCK,
    108    SVGA_FIFO_CURSOR_ON,
    109    SVGA_FIFO_CURSOR_X,
    110    SVGA_FIFO_CURSOR_Y,
    111    SVGA_FIFO_CURSOR_COUNT,
    112    SVGA_FIFO_CURSOR_LAST_UPDATED,
    113    SVGA_FIFO_RESERVED,
     495
     496   // Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3:
     497   SVGA_FIFO_CURSOR_ON,          /* Cursor bypass 3 show/hide register */
     498   SVGA_FIFO_CURSOR_X,           /* Cursor bypass 3 x register */
     499   SVGA_FIFO_CURSOR_Y,           /* Cursor bypass 3 y register */
     500   SVGA_FIFO_CURSOR_COUNT,       /* Incremented when any of the other 3 change */
     501   SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
     502
     503   // Valid with SVGA_FIFO_CAP_RESERVE:
     504   SVGA_FIFO_RESERVED,           /* Bytes past NEXT_CMD with real contents */
     505
     506   /*
     507    * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
     508    *
     509    * By default this is SVGA_ID_INVALID, to indicate that the cursor
     510    * coordinates are specified relative to the virtual root. If this
     511    * is set to a specific screen ID, cursor position is reinterpreted
     512    * as a signed offset relative to that screen's origin.
     513    */
    114514   SVGA_FIFO_CURSOR_SCREEN_ID,
     515
     516   /*
     517    * Valid with SVGA_FIFO_CAP_DEAD
     518    *
     519    * An arbitrary value written by the host, drivers should not use it.
     520    */
    115521   SVGA_FIFO_DEAD,
     522
     523   /*
     524    * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
     525    *
     526    * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
     527    * on platforms that can enforce graphics resource limits.
     528    */
    116529   SVGA_FIFO_3D_HWVERSION_REVISED,
     530
     531   /*
     532    * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
     533    * registers, but this must be done carefully and with judicious use of
     534    * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
     535    * enough to tell you whether the register exists: we've shipped drivers
     536    * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
     537    * the earlier ones.  The actual order of introduction was:
     538    * - PITCHLOCK
     539    * - 3D_CAPS
     540    * - CURSOR_* (cursor bypass 3)
     541    * - RESERVED
     542    * So, code that wants to know whether it can use any of the
     543    * aforementioned registers, or anything else added after PITCHLOCK and
     544    * before 3D_CAPS, needs to reason about something other than
     545    * SVGA_FIFO_MIN.
     546    */
     547
     548   /*
     549    * 3D caps block space; valid with 3D hardware version >=
     550    * SVGA3D_HWVERSION_WS6_B1.
     551    */
    117552   SVGA_FIFO_3D_CAPS      = 32,
    118553   SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
    119    SVGA_FIFO_GUEST_3D_HWVERSION,
    120    SVGA_FIFO_FENCE_GOAL,
    121    SVGA_FIFO_BUSY,
    122    SVGA_FIFO_NUM_REGS
     554
     555   /*
     556    * End of VMX's current definition of "extended-FIFO registers".
     557    * Registers before here are always enabled/disabled as a block; either
     558    * the extended FIFO is enabled and includes all preceding registers, or
     559    * it's disabled entirely.
     560    *
     561    * Block 3b (truly optional extended registers): Additional registers for
     562    * the extended FIFO, which the VMX already knows how to enable and
     563    * disable with correct granularity.
     564    *
     565    * Registers after here exist if and only if the guest SVGA driver
     566    * sets SVGA_FIFO_MIN high enough to leave room for them.
     567    */
     568
     569   // Valid if register exists:
     570   SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
     571   SVGA_FIFO_FENCE_GOAL,         /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
     572   SVGA_FIFO_BUSY,               /* See "FIFO Synchronization Registers" */
     573
     574   /*
     575    * Always keep this last.  This defines the maximum number of
     576    * registers we know about.  At power-on, this value is placed in
     577    * the SVGA_REG_MEM_REGS register, and we expect the guest driver
     578    * to allocate this much space in FIFO memory for registers.
     579    */
     580    SVGA_FIFO_NUM_REGS
    123581};
    124582
    125 typedef enum
    126 {
     583
     584/*
     585 * Definition of registers included in extended FIFO support.
     586 *
     587 * The guest SVGA driver gets to allocate the FIFO between registers
     588 * and data.  It must always allocate at least 4 registers, but old
     589 * drivers stopped there.
     590 *
     591 * The VMX will enable extended FIFO support if and only if the guest
     592 * left enough room for all registers defined as part of the mandatory
     593 * set for the extended FIFO.
     594 *
     595 * Note that the guest drivers typically allocate the FIFO only at
     596 * initialization time, not at mode switches, so it's likely that the
     597 * number of FIFO registers won't change without a reboot.
     598 *
     599 * All registers less than this value are guaranteed to be present if
     600 * svgaUser->fifo.extended is set. Any later registers must be tested
     601 * individually for compatibility at each use (in the VMX).
     602 *
     603 * This value is used only by the VMX, so it can change without
     604 * affecting driver compatibility; keep it that way?
     605 */
     606#define SVGA_FIFO_EXTENDED_MANDATORY_REGS  (SVGA_FIFO_3D_CAPS_LAST + 1)
     607
     608
     609/*
     610 * FIFO Synchronization Registers
     611 *
     612 *  This explains the relationship between the various FIFO
     613 *  sync-related registers in IOSpace and in FIFO space.
     614 *
     615 *  SVGA_REG_SYNC --
     616 *
     617 *       The SYNC register can be used in two different ways by the guest:
     618 *
     619 *         1. If the guest wishes to fully sync (drain) the FIFO,
     620 *            it will write once to SYNC then poll on the BUSY
     621 *            register. The FIFO is sync'ed once BUSY is zero.
     622 *
     623 *         2. If the guest wants to asynchronously wake up the host,
     624 *            it will write once to SYNC without polling on BUSY.
     625 *            Ideally it will do this after some new commands have
     626 *            been placed in the FIFO, and after reading a zero
     627 *            from SVGA_FIFO_BUSY.
     628 *
     629 *       (1) is the original behaviour that SYNC was designed to
     630 *       support.  Originally, a write to SYNC would implicitly
     631 *       trigger a read from BUSY. This causes us to synchronously
     632 *       process the FIFO.
     633 *
     634 *       This behaviour has since been changed so that writing SYNC
     635 *       will *not* implicitly cause a read from BUSY. Instead, it
     636 *       makes a channel call which asynchronously wakes up the MKS
     637 *       thread.
     638 *
     639 *       New guests can use this new behaviour to implement (2)
     640 *       efficiently. This lets guests get the host's attention
     641 *       without waiting for the MKS to poll, which gives us much
     642 *       better CPU utilization on SMP hosts and on UP hosts while
     643 *       we're blocked on the host GPU.
     644 *
     645 *       Old guests shouldn't notice the behaviour change. SYNC was
     646 *       never guaranteed to process the entire FIFO, since it was
     647 *       bounded to a particular number of CPU cycles. Old guests will
     648 *       still loop on the BUSY register until the FIFO is empty.
     649 *
     650 *       Writing to SYNC currently has the following side-effects:
     651 *
     652 *         - Sets SVGA_REG_BUSY to TRUE (in the monitor)
     653 *         - Asynchronously wakes up the MKS thread for FIFO processing
     654 *         - The value written to SYNC is recorded as a "reason", for
     655 *           stats purposes.
     656 *
     657 *       If SVGA_FIFO_BUSY is available, drivers are advised to only
     658 *       write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
     659 *       SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
     660 *       eventually set SVGA_FIFO_BUSY on its own, but this approach
     661 *       lets the driver avoid sending multiple asynchronous wakeup
     662 *       messages to the MKS thread.
     663 *
     664 *  SVGA_REG_BUSY --
     665 *
     666 *       This register is set to TRUE when SVGA_REG_SYNC is written,
     667 *       and it reads as FALSE when the FIFO has been completely
     668 *       drained.
     669 *
     670 *       Every read from this register causes us to synchronously
     671 *       process FIFO commands. There is no guarantee as to how many
     672 *       commands each read will process.
     673 *
     674 *       CPU time spent processing FIFO commands will be billed to
     675 *       the guest.
     676 *
     677 *       New drivers should avoid using this register unless they
     678 *       need to guarantee that the FIFO is completely drained. It
     679 *       is overkill for performing a sync-to-fence. Older drivers
     680 *       will use this register for any type of synchronization.
     681 *
     682 *  SVGA_FIFO_BUSY --
     683 *
     684 *       This register is a fast way for the guest driver to check
     685 *       whether the FIFO is already being processed. It reads and
     686 *       writes at normal RAM speeds, with no monitor intervention.
     687 *
     688 *       If this register reads as TRUE, the host is guaranteeing that
     689 *       any new commands written into the FIFO will be noticed before
     690 *       the MKS goes back to sleep.
     691 *
     692 *       If this register reads as FALSE, no such guarantee can be
     693 *       made.
     694 *
     695 *       The guest should use this register to quickly determine
     696 *       whether or not it needs to wake up the host. If the guest
     697 *       just wrote a command or group of commands that it would like
     698 *       the host to begin processing, it should:
     699 *
     700 *         1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
     701 *            action is necessary.
     702 *
     703 *         2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
     704 *            code that we've already sent a SYNC to the host and we
     705 *            don't need to send a duplicate.
     706 *
     707 *         3. Write a reason to SVGA_REG_SYNC. This will send an
     708 *            asynchronous wakeup to the MKS thread.
     709 */
     710
     711
     712/*
     713 * FIFO Capabilities
     714 *
     715 *      Fence -- Fence register and command are supported
     716 *      Accel Front -- Front buffer only commands are supported
     717 *      Pitch Lock -- Pitch lock register is supported
     718 *      Video -- SVGA Video overlay units are supported
     719 *      Escape -- Escape command is supported
     720 *
     721 * XXX: Add longer descriptions for each capability, including a list
     722 *      of the new features that each capability provides.
     723 *
     724 * SVGA_FIFO_CAP_SCREEN_OBJECT --
     725 *
     726 *    Provides dynamic multi-screen rendering, for improved Unity and
     727 *    multi-monitor modes. With Screen Object, the guest can
     728 *    dynamically create and destroy 'screens', which can represent
     729 *    Unity windows or virtual monitors. Screen Object also provides
     730 *    strong guarantees that DMA operations happen only when
     731 *    guest-initiated. Screen Object deprecates the BAR1 guest
     732 *    framebuffer (GFB) and all commands that work only with the GFB.
     733 *
     734 *    New registers:
     735 *       FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
     736 *
     737 *    New 2D commands:
     738 *       DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
     739 *       BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
     740 *
     741 *    New 3D commands:
     742 *       BLIT_SURFACE_TO_SCREEN
     743 *
     744 *    New guarantees:
     745 *
     746 *       - The host will not read or write guest memory, including the GFB,
     747 *         except when explicitly initiated by a DMA command.
     748 *
     749 *       - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
     750 *         is guaranteed to complete before any subsequent FENCEs.
     751 *
     752 *       - All legacy commands which affect a Screen (UPDATE, PRESENT,
     753 *         PRESENT_READBACK) as well as new Screen blit commands will
     754 *         all behave consistently as blits, and memory will be read
     755 *         or written in FIFO order.
     756 *
     757 *         For example, if you PRESENT from one SVGA3D surface to multiple
     758 *         places on the screen, the data copied will always be from the
     759 *         SVGA3D surface at the time the PRESENT was issued in the FIFO.
     760 *         This was not necessarily true on devices without Screen Object.
     761 *
     762 *         This means that on devices that support Screen Object, the
     763 *         PRESENT_READBACK command should not be necessary unless you
     764 *         actually want to read back the results of 3D rendering into
     765 *         system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
     766 *         command provides a strict superset of functionality.)
     767 *
     768 *       - When a screen is resized, either using Screen Object commands or
     769 *         legacy multimon registers, its contents are preserved.
     770 *
     771 * SVGA_FIFO_CAP_GMR2 --
     772 *
     773 *    Provides new commands to define and remap guest memory regions (GMR).
     774 *
     775 *    New 2D commands:
     776 *       DEFINE_GMR2, REMAP_GMR2.
     777 *
     778 * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
     779 *
     780 *    Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
     781 *    This register may replace SVGA_FIFO_3D_HWVERSION on platforms
     782 *    that enforce graphics resource limits.  This allows the platform
     783 *    to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
     784 *    drivers that do not limit their resources.
     785 *
     786 *    Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
     787 *    are codependent (and thus we use a single capability bit).
     788 *
     789 * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
     790 *
     791 *    Modifies the DEFINE_SCREEN command to include a guest provided
     792 *    backing store in GMR memory and the bytesPerLine for the backing
     793 *    store.  This capability requires the use of a backing store when
     794 *    creating screen objects.  However if SVGA_FIFO_CAP_SCREEN_OBJECT
     795 *    is present then backing stores are optional.
     796 *
     797 * SVGA_FIFO_CAP_DEAD --
     798 *
     799 *    Drivers should not use this cap bit.  This cap bit can not be
     800 *    reused since some hosts already expose it.
     801 */
     802
     803#define SVGA_FIFO_CAP_NONE                  0
     804#define SVGA_FIFO_CAP_FENCE             (1<<0)
     805#define SVGA_FIFO_CAP_ACCELFRONT        (1<<1)
     806#define SVGA_FIFO_CAP_PITCHLOCK         (1<<2)
     807#define SVGA_FIFO_CAP_VIDEO             (1<<3)
     808#define SVGA_FIFO_CAP_CURSOR_BYPASS_3   (1<<4)
     809#define SVGA_FIFO_CAP_ESCAPE            (1<<5)
     810#define SVGA_FIFO_CAP_RESERVE           (1<<6)
     811#define SVGA_FIFO_CAP_SCREEN_OBJECT     (1<<7)
     812#define SVGA_FIFO_CAP_GMR2              (1<<8)
     813#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED  SVGA_FIFO_CAP_GMR2
     814#define SVGA_FIFO_CAP_SCREEN_OBJECT_2   (1<<9)
     815#define SVGA_FIFO_CAP_DEAD              (1<<10)
     816
     817
     818/*
     819 * FIFO Flags
     820 *
     821 *      Accel Front -- Driver should use front buffer only commands
     822 */
     823
     824#define SVGA_FIFO_FLAG_NONE                 0
     825#define SVGA_FIFO_FLAG_ACCELFRONT       (1<<0)
     826#define SVGA_FIFO_FLAG_RESERVED        (1<<31) // Internal use only
     827
     828/*
     829 * FIFO reservation sentinel value
     830 */
     831
     832#define SVGA_FIFO_RESERVED_UNKNOWN      0xffffffff
     833
     834
     835/*
     836 * Video overlay support
     837 */
     838
     839#define SVGA_NUM_OVERLAY_UNITS 32
     840
     841
     842/*
     843 * Video capabilities that the guest is currently using
     844 */
     845
     846#define SVGA_VIDEO_FLAG_COLORKEY        0x0001
     847
     848
     849/*
     850 * Offsets for the video overlay registers
     851 */
     852
     853enum {
     854   SVGA_VIDEO_ENABLED = 0,
     855   SVGA_VIDEO_FLAGS,
     856   SVGA_VIDEO_DATA_OFFSET,
     857   SVGA_VIDEO_FORMAT,
     858   SVGA_VIDEO_COLORKEY,
     859   SVGA_VIDEO_SIZE,          // Deprecated
     860   SVGA_VIDEO_WIDTH,
     861   SVGA_VIDEO_HEIGHT,
     862   SVGA_VIDEO_SRC_X,
     863   SVGA_VIDEO_SRC_Y,
     864   SVGA_VIDEO_SRC_WIDTH,
     865   SVGA_VIDEO_SRC_HEIGHT,
     866   SVGA_VIDEO_DST_X,         // Signed int32
     867   SVGA_VIDEO_DST_Y,         // Signed int32
     868   SVGA_VIDEO_DST_WIDTH,
     869   SVGA_VIDEO_DST_HEIGHT,
     870   SVGA_VIDEO_PITCH_1,
     871   SVGA_VIDEO_PITCH_2,
     872   SVGA_VIDEO_PITCH_3,
     873   SVGA_VIDEO_DATA_GMRID,    // Optional, defaults to SVGA_GMR_FRAMEBUFFER
     874   SVGA_VIDEO_DST_SCREEN_ID, // Optional, defaults to virtual coords (SVGA_ID_INVALID)
     875   SVGA_VIDEO_NUM_REGS
     876};
     877
     878
     879/*
     880 * SVGA Overlay Units
     881 *
     882 *      width and height relate to the entire source video frame.
     883 *      srcX, srcY, srcWidth and srcHeight represent subset of the source
     884 *      video frame to be displayed.
     885 */
     886
     887typedef struct SVGAOverlayUnit {
     888   uint32_t enabled;
     889   uint32_t flags;
     890   uint32_t dataOffset;
     891   uint32_t format;
     892   uint32_t colorKey;
     893   uint32_t size;
     894   uint32_t width;
     895   uint32_t height;
     896   uint32_t srcX;
     897   uint32_t srcY;
     898   uint32_t srcWidth;
     899   uint32_t srcHeight;
     900   int32_t  dstX;
     901   int32_t  dstY;
     902   uint32_t dstWidth;
     903   uint32_t dstHeight;
     904   uint32_t pitches[3];
     905   uint32_t dataGMRId;
     906   uint32_t dstScreenId;
     907} SVGAOverlayUnit;
     908
     909
     910/*
     911 * SVGAScreenObject --
     912 *
     913 *    This is a new way to represent a guest's multi-monitor screen or
     914 *    Unity window. Screen objects are only supported if the
     915 *    SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
     916 *
     917 *    If Screen Objects are supported, they can be used to fully
     918 *    replace the functionality provided by the framebuffer registers
     919 *    (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
     920 *
     921 *    The screen object is a struct with guaranteed binary
     922 *    compatibility. New flags can be added, and the struct may grow,
     923 *    but existing fields must retain their meaning.
     924 *
     925 *    Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
     926 *    a SVGAGuestPtr that is used to back the screen contents.  This
     927 *    memory must come from the GFB.  The guest is not allowed to
     928 *    access the memory and doing so will have undefined results.  The
     929 *    backing store is required to be page aligned and the size is
     930 *    padded to the next page boundry.  The number of pages is:
     931 *       (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
     932 *
     933 *    The pitch in the backingStore is required to be at least large
     934 *    enough to hold a 32bbp scanline.  It is recommended that the
     935 *    driver pad bytesPerLine for a potential performance win.
     936 *
     937 *    The cloneCount field is treated as a hint from the guest that
     938 *    the user wants this display to be cloned, countCount times.  A
     939 *    value of zero means no cloning should happen.
     940 */
     941
     942#define SVGA_SCREEN_MUST_BE_SET     (1 << 0) // Must be set or results undefined
     943#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET // Deprecated
     944#define SVGA_SCREEN_IS_PRIMARY      (1 << 1) // Guest considers this screen to be 'primary'
     945#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)  // Guest is running a fullscreen app here
     946
     947/*
     948 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When the screen is
     949 * deactivated the base layer is defined to lose all contents and
     950 * become black.  When a screen is deactivated the backing store is
     951 * optional.  When set backingPtr and bytesPerLine will be ignored.
     952 */
     953#define SVGA_SCREEN_DEACTIVATE  (1 << 3)
     954
     955/*
     956 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When this flag is set
     957 * the screen contents will be outputted as all black to the user
     958 * though the base layer contents is preserved.  The screen base layer
     959 * can still be read and written to like normal though the no visible
     960 * effect will be seen by the user.  When the flag is changed the
     961 * screen will be blanked or redrawn to the current contents as needed
     962 * without any extra commands from the driver.  This flag only has an
     963 * effect when the screen is not deactivated.
     964 */
     965#define SVGA_SCREEN_BLANKING (1 << 4)
     966
     967typedef
     968struct SVGAScreenObject {
     969   uint32_t structSize;   // sizeof(SVGAScreenObject)
     970   uint32_t id;
     971   uint32_t flags;
     972   struct {
     973      uint32_t width;
     974      uint32_t height;
     975   } size;
     976   struct {
     977      int32_t x;
     978      int32_t y;
     979   } root;
     980
     981   /*
     982    * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
     983    * with SVGA_FIFO_CAP_SCREEN_OBJECT.
     984    */
     985   SVGAGuestImage backingStore;
     986   uint32_t cloneCount;
     987} SVGAScreenObject;
     988
     989
     990/*
     991 *  Commands in the command FIFO:
     992 *
     993 *  Command IDs defined below are used for the traditional 2D FIFO
     994 *  communication (not all commands are available for all versions of the
     995 *  SVGA FIFO protocol).
     996 *
     997 *  Note the holes in the command ID numbers: These commands have been
     998 *  deprecated, and the old IDs must not be reused.
     999 *
     1000 *  Command IDs from 1000 to 1999 are reserved for use by the SVGA3D
     1001 *  protocol.
     1002 *
     1003 *  Each command's parameters are described by the comments and
     1004 *  structs below.
     1005 */
     1006
     1007typedef enum {
    1271008   SVGA_CMD_INVALID_CMD           = 0,
    1281009   SVGA_CMD_UPDATE                = 1,
    … …  
    1461027} SVGAFifoCmdId;
    1471028
    148 typedef struct SVGAColorBGRX
    149 {
    150    union
    151    {
    152       struct
    153       {
    154          uint32_t b : 8;
    155          uint32_t g : 8;
    156          uint32_t r : 8;
    157          uint32_t x : 8;
    158       } s;
    159 
    160       uint32_t value;
    161    };
    162 } SVGAColorBGRX;
    163 
    164 typedef struct SVGASignedPoint
    165 {
    166    int32_t  x;
    167    int32_t  y;
    168 } SVGASignedPoint;
    169 
    170 #define SVGA_CAP_NONE               0x00000000
    171 #define SVGA_CAP_RECT_COPY          0x00000002
    172 #define SVGA_CAP_CURSOR             0x00000020
    173 #define SVGA_CAP_CURSOR_BYPASS      0x00000040
    174 #define SVGA_CAP_CURSOR_BYPASS_2    0x00000080
    175 #define SVGA_CAP_8BIT_EMULATION     0x00000100
    176 #define SVGA_CAP_ALPHA_CURSOR       0x00000200
    177 #define SVGA_CAP_3D                 0x00004000
    178 #define SVGA_CAP_EXTENDED_FIFO      0x00008000
    179 #define SVGA_CAP_MULTIMON           0x00010000
    180 #define SVGA_CAP_PITCHLOCK          0x00020000
    181 #define SVGA_CAP_IRQMASK            0x00040000
    182 #define SVGA_CAP_DISPLAY_TOPOLOGY   0x00080000
    183 #define SVGA_CAP_GMR                0x00100000
    184 #define SVGA_CAP_TRACES             0x00200000
    185 #define SVGA_CAP_GMR2               0x00400000
    186 #define SVGA_CAP_SCREEN_OBJECT_2    0x00800000
    187 
    188 #define SVGA_GMR_NULL         ((uint32_t) -1)
    189 #define SVGA_GMR_FRAMEBUFFER  ((uint32_t) -2)
    190 
    191 typedef struct SVGAGuestPtr
    192 {
    193    uint32_t gmrId;
    194    uint32_t offset;
    195 } SVGAGuestPtr;
    196 
    197 typedef struct SVGAGMRImageFormat
    198 {
    199    union
    200    {
    201       struct
    202       {
    203          uint32_t bitsPerPixel : 8;
    204          uint32_t colorDepth   : 8;
    205          uint32_t reserved     : 16;
    206       } s;
    207 
    208       uint32_t value;
    209    };
    210 } SVGAGMRImageFormat;
    211 
    212 typedef struct SVGAGuestImage
    213 {
    214    SVGAGuestPtr         ptr;
    215    uint32_t pitch;
    216 } SVGAGuestImage;
    217 
    218 #define SVGA_SCREEN_MUST_BE_SET     (1 << 0)
    219 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET
    220 #define SVGA_SCREEN_IS_PRIMARY      (1 << 1)
    221 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
    222 #define SVGA_SCREEN_DEACTIVATE  (1 << 3)
    223 #define SVGA_SCREEN_BLANKING (1 << 4)
    224 
    225 typedef struct SVGAScreenObject
    226 {
    227    uint32_t structSize;
    228    uint32_t id;
    229    uint32_t flags;
    230    struct
    231    {
    232       uint32_t width;
    233       uint32_t height;
    234    } size;
    235    struct
    236    {
    237       int32_t x;
    238       int32_t y;
    239    } root;
    240    SVGAGuestImage backingStore;
    241    uint32_t cloneCount;
    242 } SVGAScreenObject;
    243 
    244 typedef struct
    245 {
    246    uint32_t screenId;
    247 } SVGAFifoCmdDestroyScreen;
    248 
    249 typedef struct
    250 {
     1029#define SVGA_CMD_MAX_DATASIZE       (256 * 1024)
     1030#define SVGA_CMD_MAX_ARGS           64
     1031
     1032
     1033/*
     1034 * SVGA_CMD_UPDATE --
     1035 *
     1036 *    This is a DMA transfer which copies from the Guest Framebuffer
     1037 *    (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
     1038 *    intersect with the provided virtual rectangle.
     1039 *
     1040 *    This command does not support using arbitrary guest memory as a
     1041 *    data source- it only works with the pre-defined GFB memory.
     1042 *    This command also does not support signed virtual coordinates.
     1043 *    If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
     1044 *    negative root x/y coordinates, the negative portion of those
     1045 *    screens will not be reachable by this command.
     1046 *
     1047 *    This command is not necessary when using framebuffer
     1048 *    traces. Traces are automatically enabled if the SVGA FIFO is
     1049 *    disabled, and you may explicitly enable/disable traces using
     1050 *    SVGA_REG_TRACES. With traces enabled, any write to the GFB will
     1051 *    automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
     1052 *
     1053 *    Traces and SVGA_CMD_UPDATE are the only supported ways to render
     1054 *    pseudocolor screen updates. The newer Screen Object commands
     1055 *    only support true color formats.
     1056 *
     1057 * Availability:
     1058 *    Always available.
     1059 */
     1060
     1061typedef
     1062struct {
    2511063   uint32_t x;
    2521064   uint32_t y;
    … …  
    2551067} SVGAFifoCmdUpdate;
    2561068
    257 typedef struct
    258 {
    259    uint32_t fence;
    260 } SVGAFifoCmdFence;
    261 
    262 typedef struct
    263 {
    264    uint32_t nsid;
    265    uint32_t size;
    266 } SVGAFifoCmdEscape;
    267 
    268 typedef struct
    269 {
    270    uint32_t id;
     1069
     1070/*
     1071 * SVGA_CMD_RECT_COPY --
     1072 *
     1073 *    Perform a rectangular DMA transfer from one area of the GFB to
     1074 *    another, and copy the result to any screens which intersect it.
     1075 *
     1076 * Availability:
     1077 *    SVGA_CAP_RECT_COPY
     1078 */
     1079
     1080typedef
     1081struct {
     1082   uint32_t srcX;
     1083   uint32_t srcY;
     1084   uint32_t destX;
     1085   uint32_t destY;
     1086   uint32_t width;
     1087   uint32_t height;
     1088} SVGAFifoCmdRectCopy;
     1089
     1090
     1091/*
     1092 * SVGA_CMD_DEFINE_CURSOR --
     1093 *
     1094 *    Provide a new cursor image, as an AND/XOR mask.
     1095 *
     1096 *    The recommended way to position the cursor overlay is by using
     1097 *    the SVGA_FIFO_CURSOR_* registers, supported by the
     1098 *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
     1099 *
     1100 * Availability:
     1101 *    SVGA_CAP_CURSOR
     1102 */
     1103
     1104typedef
     1105struct {
     1106   uint32_t id;             // Reserved, must be zero.
    2711107   uint32_t hotspotX;
    2721108   uint32_t hotspotY;
    2731109   uint32_t width;
    2741110   uint32_t height;
    275    uint32_t andMaskDepth;
    276    uint32_t xorMaskDepth;
     1111   uint32_t andMaskDepth;   // Value must be 1 or equal to BITS_PER_PIXEL
     1112   uint32_t xorMaskDepth;   // Value must be 1 or equal to BITS_PER_PIXEL
     1113   /*
     1114    * Followed by scanline data for AND mask, then XOR mask.
     1115    * Each scanline is padded to a 32-bit boundary.
     1116   */
    2771117} SVGAFifoCmdDefineCursor;
    2781118
    279 typedef struct
    280 {
    281    uint32_t id;
     1119
     1120/*
     1121 * SVGA_CMD_DEFINE_ALPHA_CURSOR --
     1122 *
     1123 *    Provide a new cursor image, in 32-bit BGRA format.
     1124 *
     1125 *    The recommended way to position the cursor overlay is by using
     1126 *    the SVGA_FIFO_CURSOR_* registers, supported by the
     1127 *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
     1128 *
     1129 * Availability:
     1130 *    SVGA_CAP_ALPHA_CURSOR
     1131 */
     1132
     1133typedef
     1134struct {
     1135   uint32_t id;             // Reserved, must be zero.
    2821136   uint32_t hotspotX;
    2831137   uint32_t hotspotY;
    2841138   uint32_t width;
    2851139   uint32_t height;
     1140   /* Followed by scanline data */
    2861141} SVGAFifoCmdDefineAlphaCursor;
    2871142
    288 typedef struct
    289 {
    290    SVGAScreenObject screen;
     1143
     1144/*
     1145 * SVGA_CMD_UPDATE_VERBOSE --
     1146 *
     1147 *    Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
     1148 *    'reason' value, an opaque cookie which is used by internal
     1149 *    debugging tools. Third party drivers should not use this
     1150 *    command.
     1151 *
     1152 * Availability:
     1153 *    SVGA_CAP_EXTENDED_FIFO
     1154 */
     1155
     1156typedef
     1157struct {
     1158   uint32_t x;
     1159   uint32_t y;
     1160   uint32_t width;
     1161   uint32_t height;
     1162   uint32_t reason;
     1163} SVGAFifoCmdUpdateVerbose;
     1164
     1165
     1166/*
     1167 * SVGA_CMD_FRONT_ROP_FILL --
     1168 *
     1169 *    This is a hint which tells the SVGA device that the driver has
     1170 *    just filled a rectangular region of the GFB with a solid
     1171 *    color. Instead of reading these pixels from the GFB, the device
     1172 *    can assume that they all equal 'color'. This is primarily used
     1173 *    for remote desktop protocols.
     1174 *
     1175 * Availability:
     1176 *    SVGA_FIFO_CAP_ACCELFRONT
     1177 */
     1178
     1179#define  SVGA_ROP_COPY                    0x03
     1180
     1181typedef
     1182struct {
     1183   uint32_t color;     // In the same format as the GFB
     1184   uint32_t x;
     1185   uint32_t y;
     1186   uint32_t width;
     1187   uint32_t height;
     1188   uint32_t rop;       // Must be SVGA_ROP_COPY
     1189} SVGAFifoCmdFrontRopFill;
     1190
     1191
     1192/*
     1193 * SVGA_CMD_FENCE --
     1194 *
     1195 *    Insert a synchronization fence.  When the SVGA device reaches
     1196 *    this command, it will copy the 'fence' value into the
     1197 *    SVGA_FIFO_FENCE register. It will also compare the fence against
     1198 *    SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
     1199 *    SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
     1200 *    raise this interrupt.
     1201 *
     1202 * Availability:
     1203 *    SVGA_FIFO_FENCE for this command,
     1204 *    SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
     1205 */
     1206
     1207typedef
     1208struct {
     1209   uint32_t fence;
     1210} SVGAFifoCmdFence;
     1211
     1212
     1213/*
     1214 * SVGA_CMD_ESCAPE --
     1215 *
     1216 *    Send an extended or vendor-specific variable length command.
     1217 *    This is used for video overlay, third party plugins, and
     1218 *    internal debugging tools. See svga_escape.h
     1219 *
     1220 * Availability:
     1221 *    SVGA_FIFO_CAP_ESCAPE
     1222 */
     1223
     1224typedef
     1225struct {
     1226   uint32_t nsid;
     1227   uint32_t size;
     1228   /* followed by 'size' bytes of data */
     1229} SVGAFifoCmdEscape;
     1230
     1231
     1232/*
     1233 * SVGA_CMD_DEFINE_SCREEN --
     1234 *
     1235 *    Define or redefine an SVGAScreenObject. See the description of
     1236 *    SVGAScreenObject above.  The video driver is responsible for
     1237 *    generating new screen IDs. They should be small positive
     1238 *    integers. The virtual device will have an implementation
     1239 *    specific upper limit on the number of screen IDs
     1240 *    supported. Drivers are responsible for recycling IDs. The first
     1241 *    valid ID is zero.
     1242 *
     1243 *    - Interaction with other registers:
     1244 *
     1245 *    For backwards compatibility, when the GFB mode registers (WIDTH,
     1246 *    HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
     1247 *    deletes all screens other than screen #0, and redefines screen
     1248 *    #0 according to the specified mode. Drivers that use
     1249 *    SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
     1250 *
     1251 *    If you use screen objects, do not use the legacy multi-mon
     1252 *    registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
     1253 *
     1254 * Availability:
     1255 *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
     1256 */
     1257
     1258typedef
     1259struct {
     1260   SVGAScreenObject screen;   // Variable-length according to version
    2911261} SVGAFifoCmdDefineScreen;
    2921262
    293 typedef struct
    294 {
     1263
     1264/*
     1265 * SVGA_CMD_DESTROY_SCREEN --
     1266 *
     1267 *    Destroy an SVGAScreenObject. Its ID is immediately available for
     1268 *    re-use.
     1269 *
     1270 * Availability:
     1271 *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
     1272 */
     1273
     1274typedef
     1275struct {
     1276   uint32_t screenId;
     1277} SVGAFifoCmdDestroyScreen;
     1278
     1279
     1280/*
     1281 * SVGA_CMD_DEFINE_GMRFB --
     1282 *
     1283 *    This command sets a piece of SVGA device state called the
     1284 *    Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
     1285 *    piece of light-weight state which identifies the location and
     1286 *    format of an image in guest memory or in BAR1. The GMRFB has
     1287 *    an arbitrary size, and it doesn't need to match the geometry
     1288 *    of the GFB or any screen object.
     1289 *
     1290 *    The GMRFB can be redefined as often as you like. You could
     1291 *    always use the same GMRFB, you could redefine it before
     1292 *    rendering from a different guest screen, or you could even
     1293 *    redefine it before every blit.
     1294 *
     1295 *    There are multiple ways to use this command. The simplest way is
     1296 *    to use it to move the framebuffer either to elsewhere in the GFB
     1297 *    (BAR1) memory region, or to a user-defined GMR. This lets a
     1298 *    driver use a framebuffer allocated entirely out of normal system
     1299 *    memory, which we encourage.
     1300 *
     1301 *    Another way to use this command is to set up a ring buffer of
     1302 *    updates in GFB memory. If a driver wants to ensure that no
     1303 *    frames are skipped by the SVGA device, it is important that the
     1304 *    driver not modify the source data for a blit until the device is
     1305 *    done processing the command. One efficient way to accomplish
     1306 *    this is to use a ring of small DMA buffers. Each buffer is used
     1307 *    for one blit, then we move on to the next buffer in the
     1308 *    ring. The FENCE mechanism is used to protect each buffer from
     1309 *    re-use until the device is finished with that buffer's
     1310 *    corresponding blit.
     1311 *
     1312 *    This command does not affect the meaning of SVGA_CMD_UPDATE.
     1313 *    UPDATEs always occur from the legacy GFB memory area. This
     1314 *    command has no support for pseudocolor GMRFBs. Currently only
     1315 *    true-color 15, 16, and 24-bit depths are supported. Future
     1316 *    devices may expose capabilities for additional framebuffer
     1317 *    formats.
     1318 *
     1319 *    The default GMRFB value is undefined. Drivers must always send
     1320 *    this command at least once before performing any blit from the
     1321 *    GMRFB.
     1322 *
     1323 * Availability:
     1324 *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
     1325 */
     1326
     1327typedef
     1328struct {
     1329   SVGAGuestPtr        ptr;
     1330   uint32_t              bytesPerLine;
     1331   SVGAGMRImageFormat  format;
     1332} SVGAFifoCmdDefineGMRFB;
     1333
     1334
     1335/*
     1336 * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
     1337 *
     1338 *    This is a guest-to-host blit. It performs a DMA operation to
     1339 *    copy a rectangular region of pixels from the current GMRFB to
     1340 *    one or more Screen Objects.
     1341 *
     1342 *    The destination coordinate may be specified relative to a
     1343 *    screen's origin (if a screen ID is specified) or relative to the
     1344 *    virtual coordinate system's origin (if the screen ID is
     1345 *    SVGA_ID_INVALID). The actual destination may span zero or more
     1346 *    screens, in the case of a virtual destination rect or a rect
     1347 *    which extends off the edge of the specified screen.
     1348 *
     1349 *    This command writes to the screen's "base layer": the underlying
     1350 *    framebuffer which exists below any cursor or video overlays. No
     1351 *    action is necessary to explicitly hide or update any overlays
     1352 *    which exist on top of the updated region.
     1353 *
     1354 *    The SVGA device is guaranteed to finish reading from the GMRFB
     1355 *    by the time any subsequent FENCE commands are reached.
     1356 *
     1357 *    This command consumes an annotation. See the
     1358 *    SVGA_CMD_ANNOTATION_* commands for details.
     1359 *
     1360 * Availability:
     1361 *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
     1362 */
     1363
     1364typedef
     1365struct {
     1366   SVGASignedPoint  srcOrigin;
     1367   SVGASignedRect   destRect;
     1368   uint32_t           destScreenId;
     1369} SVGAFifoCmdBlitGMRFBToScreen;
     1370
     1371
     1372/*
     1373 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
     1374 *
     1375 *    This is a host-to-guest blit. It performs a DMA operation to
     1376 *    copy a rectangular region of pixels from a single Screen Object
     1377 *    back to the current GMRFB.
     1378 *
     1379 *    Usage note: This command should be used rarely. It will
     1380 *    typically be inefficient, but it is necessary for some types of
     1381 *    synchronization between 3D (GPU) and 2D (CPU) rendering into
     1382 *    overlapping areas of a screen.
     1383 *
     1384 *    The source coordinate is specified relative to a screen's
     1385 *    origin. The provided screen ID must be valid. If any parameters
     1386 *    are invalid, the resulting pixel values are undefined.
     1387 *
     1388 *    This command reads the screen's "base layer". Overlays like
     1389 *    video and cursor are not included, but any data which was sent
     1390 *    using a blit-to-screen primitive will be available, no matter
     1391 *    whether the data's original source was the GMRFB or the 3D
     1392 *    acceleration hardware.
     1393 *
     1394 *    Note that our guest-to-host blits and host-to-guest blits aren't
     1395 *    symmetric in their current implementation. While the parameters
     1396 *    are identical, host-to-guest blits are a lot less featureful.
     1397 *    They do not support clipping: If the source parameters don't
     1398 *    fully fit within a screen, the blit fails. They must originate
     1399 *    from exactly one screen. Virtual coordinates are not directly
     1400 *    supported.
     1401 *
     1402 *    Host-to-guest blits do support the same set of GMRFB formats
     1403 *    offered by guest-to-host blits.
     1404 *
     1405 *    The SVGA device is guaranteed to finish writing to the GMRFB by
     1406 *    the time any subsequent FENCE commands are reached.
     1407 *
     1408 * Availability:
     1409 *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
     1410 */
     1411
     1412typedef
     1413struct {
     1414   SVGASignedPoint  destOrigin;
     1415   SVGASignedRect   srcRect;
     1416   uint32_t           srcScreenId;
     1417} SVGAFifoCmdBlitScreenToGMRFB;
     1418
     1419
     1420/*
     1421 * SVGA_CMD_ANNOTATION_FILL --
     1422 *
     1423 *    This is a blit annotation. This command stores a small piece of
     1424 *    device state which is consumed by the next blit-to-screen
     1425 *    command. The state is only cleared by commands which are
     1426 *    specifically documented as consuming an annotation. Other
     1427 *    commands (such as ESCAPEs for debugging) may intervene between
     1428 *    the annotation and its associated blit.
     1429 *
     1430 *    This annotation is a promise about the contents of the next
     1431 *    blit: The video driver is guaranteeing that all pixels in that
     1432 *    blit will have the same value, specified here as a color in
     1433 *    SVGAColorBGRX format.
     1434 *
     1435 *    The SVGA device can still render the blit correctly even if it
     1436 *    ignores this annotation, but the annotation may allow it to
     1437 *    perform the blit more efficiently, for example by ignoring the
     1438 *    source data and performing a fill in hardware.
     1439 *
     1440 *    This annotation is most important for performance when the
     1441 *    user's display is being remoted over a network connection.
     1442 *
     1443 * Availability:
     1444 *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
     1445 */
     1446
     1447typedef
     1448struct {
    2951449   SVGAColorBGRX  color;
    2961450} SVGAFifoCmdAnnotationFill;
    2971451
    298 typedef struct
    299 {
     1452
     1453/*
     1454 * SVGA_CMD_ANNOTATION_COPY --
     1455 *
     1456 *    This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
     1457 *    information about annotations.
     1458 *
     1459 *    This annotation is a promise about the contents of the next
     1460 *    blit: The video driver is guaranteeing that all pixels in that
     1461 *    blit will have the same value as those which already exist at an
     1462 *    identically-sized region on the same or a different screen.
     1463 *
     1464 *    Note that the source pixels for the COPY in this annotation are
     1465 *    sampled before applying the anqnotation's associated blit. They
     1466 *    are allowed to overlap with the blit's destination pixels.
     1467 *
     1468 *    The copy source rectangle is specified the same way as the blit
     1469 *    destination: it can be a rectangle which spans zero or more
     1470 *    screens, specified relative to either a screen or to the virtual
     1471 *    coordinate system's origin. If the source rectangle includes
     1472 *    pixels which are not from exactly one screen, the results are
     1473 *    undefined.
     1474 *
     1475 * Availability:
     1476 *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
     1477 */
     1478
     1479typedef
     1480struct {
    3001481   SVGASignedPoint  srcOrigin;
    3011482   uint32_t           srcScreenId;
    3021483} SVGAFifoCmdAnnotationCopy;
    3031484
    304 #define SVGA_FIFO_CAP_NONE                  0
    305 #define SVGA_FIFO_CAP_FENCE             (1<<0)
    306 #define SVGA_FIFO_CAP_ACCELFRONT        (1<<1)
    307 #define SVGA_FIFO_CAP_PITCHLOCK         (1<<2)
    308 #define SVGA_FIFO_CAP_VIDEO             (1<<3)
    309 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3   (1<<4)
    310 #define SVGA_FIFO_CAP_ESCAPE            (1<<5)
    311 #define SVGA_FIFO_CAP_RESERVE           (1<<6)
    312 #define SVGA_FIFO_CAP_SCREEN_OBJECT     (1<<7)
    313 #define SVGA_FIFO_CAP_GMR2              (1<<8)
    314 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED  SVGA_FIFO_CAP_GMR2
    315 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2   (1<<9)
    316 #define SVGA_FIFO_CAP_DEAD              (1<<10)
    317 
    318 #endif /* _SVGA_REG_H_ */
     1485
     1486/*
     1487 * SVGA_CMD_DEFINE_GMR2 --
     1488 *
     1489 *    Define guest memory region v2.  See the description of GMRs above.
     1490 *
     1491 * Availability:
     1492 *    SVGA_CAP_GMR2
     1493 */
     1494
     1495typedef
     1496struct {
     1497   uint32_t gmrId;
     1498   uint32_t numPages;
     1499}
     1500SVGAFifoCmdDefineGMR2;
     1501
     1502
     1503/*
     1504 * SVGA_CMD_REMAP_GMR2 --
     1505 *
     1506 *    Remap guest memory region v2.  See the description of GMRs above.
     1507 *
     1508 *    This command allows guest to modify a portion of an existing GMR by
     1509 *    invalidating it or reassigning it to different guest physical pages.
     1510 *    The pages are identified by physical page number (PPN).  The pages
     1511 *    are assumed to be pinned and valid for DMA operations.
     1512 *
     1513 *    Description of command flags:
     1514 *
     1515 *    SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
     1516 *       The PPN list must not overlap with the remap region (this can be
     1517 *       handled trivially by referencing a separate GMR).  If flag is
     1518 *       disabled, PPN list is appended to SVGARemapGMR command.
     1519 *
     1520 *    SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
     1521 *       it is in PPN32 format.
     1522 *
     1523 *    SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
     1524 *       A single PPN can be used to invalidate a portion of a GMR or
     1525 *       map it to to a single guest scratch page.
     1526 *
     1527 * Availability:
     1528 *    SVGA_CAP_GMR2
     1529 */
     1530
     1531typedef enum {
     1532   SVGA_REMAP_GMR2_PPN32         = 0,
     1533   SVGA_REMAP_GMR2_VIA_GMR       = (1 << 0),
     1534   SVGA_REMAP_GMR2_PPN64         = (1 << 1),
     1535   SVGA_REMAP_GMR2_SINGLE_PPN    = (1 << 2)
     1536} SVGARemapGMR2Flags;
     1537
     1538typedef
     1539struct {
     1540   uint32_t gmrId;
     1541   SVGARemapGMR2Flags flags;
     1542   uint32_t offsetPages; // offset in pages to begin remap
     1543   uint32_t numPages; // number of pages to remap
     1544   /*
     1545    * Followed by additional data depending on SVGARemapGMR2Flags.
     1546    *
     1547    * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
     1548    * Otherwise an array of page descriptors in PPN32 or PPN64 format
     1549    * (according to flag SVGA_REMAP_GMR2_PPN64) follows.  If flag
     1550    * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
     1551    */
     1552}
     1553SVGAFifoCmdRemapGMR2;
     1554
     1555#endif
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