Changeset 53007 in vbox
- Timestamp:
- Oct 9, 2014 9:13:24 AM (11 years ago)
- svn:sync-xref-src-repo-rev:
- 96472
- Location:
- trunk
- Files:
-
- 6 edited
-
include/VBox/disopcode.h (modified) (6 diffs)
-
src/VBox/Disassembler/DisasmCore.cpp (modified) (6 diffs)
-
src/VBox/Disassembler/DisasmFormatYasm.cpp (modified) (2 diffs)
-
src/VBox/Disassembler/DisasmInternal.h (modified) (2 diffs)
-
src/VBox/Disassembler/DisasmTables.cpp (modified) (8 diffs)
-
src/VBox/Disassembler/testcase/tstDisasm-1A.asm (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
TabularUnified trunk/include/VBox/disopcode.h ¶
r47412 r53007 41 41 * @{ 42 42 */ 43 43 enum OPCODES { 44 44 /** @name Full Intel X86 opcode list 45 45 * @{ */ 46 #define OP_INVALID 0 47 #define OP_OPSIZE 1 48 #define OP_ADDRSIZE 2 49 #define OP_SEG 3 50 #define OP_REPNE 4 51 #define OP_REPE 5 52 #define OP_REX 6 53 #define OP_LOCK 7 54 #define OP_LAST_PREFIX OP_LOCK /* disassembler assumes this is the last prefix byte value!!!! */ 55 #define OP_AND 8 56 #define OP_OR 9 57 #define OP_DAA 10 58 #define OP_SUB 11 59 #define OP_DAS 12 60 #define OP_XOR 13 61 #define OP_AAA 14 62 #define OP_CMP 15 63 #define OP_IMM_GRP1 16 64 #define OP_AAS 17 65 #define OP_INC 18 66 #define OP_DEC 19 67 #define OP_PUSHA 20 68 #define OP_POPA 21 69 #define OP_BOUND 22 70 #define OP_ARPL 23 71 #define OP_PUSH 24 72 #define OP_POP 25 73 #define OP_IMUL 26 74 #define OP_INSB 27 75 #define OP_INSWD 28 76 #define OP_OUTSB 29 77 #define OP_OUTSWD 30 78 #define OP_JO 31 79 #define OP_JNO 32 80 #define OP_JC 33 81 #define OP_JNC 34 82 #define OP_JE 35 83 #define OP_JNE 36 84 #define OP_JBE 37 85 #define OP_JNBE 38 86 #define OP_JS 39 87 #define OP_JNS 40 88 #define OP_JP 41 89 #define OP_JNP 42 90 #define OP_JL 43 91 #define OP_JNL 44 92 #define OP_JLE 45 93 #define OP_JNLE 46 94 #define OP_ADD 47 95 #define OP_TEST 48 96 #define OP_XCHG 49 97 #define OP_MOV 50 98 #define OP_LEA 51 99 #define OP_NOP 52 100 #define OP_CBW 53 101 #define OP_CWD 54 102 #define OP_CALL 55 103 #define OP_WAIT 56 104 #define OP_PUSHF 57 105 #define OP_POPF 58 106 #define OP_SAHF 59 107 #define OP_LAHF 60 108 #define OP_MOVSB 61 109 #define OP_MOVSWD 62 110 #define OP_CMPSB 63 111 #define OP_CMPWD 64 112 #define OP_STOSB 65 113 #define OP_STOSWD 66 114 #define OP_LODSB 67 115 #define OP_LODSWD 68 116 #define OP_SCASB 69 117 #define OP_SCASWD 70 118 #define OP_SHIFT_GRP2 71 119 #define OP_RETN 72 120 #define OP_LES 73 121 #define OP_LDS 74 122 #define OP_ENTER 75 123 #define OP_LEAVE 76 124 #define OP_RETF 77 125 #define OP_INT3 78 126 #define OP_INT 79 127 #define OP_INTO 80 128 #define OP_IRET 81 129 #define OP_AAM 82 130 #define OP_AAD 83 131 #define OP_XLAT 84 132 #define OP_ESCF0 85 133 #define OP_ESCF1 86 134 #define OP_ESCF2 87 135 #define OP_ESCF3 88 136 #define OP_ESCF4 89 137 #define OP_ESCF5 90 138 #define OP_ESCF6 91 139 #define OP_ESCF7 92 140 #define OP_LOOPNE 93 141 #define OP_LOOPE 94 142 #define OP_LOOP 95 143 #define OP_JECXZ 96 144 #define OP_IN 97 145 #define OP_OUT 98 146 #define OP_JMP 99 147 #define OP_2B_ESC 100 148 #define OP_ADC 101 149 #define OP_SBB 102 150 #define OP_HLT 103 151 #define OP_CMC 104 152 #define OP_UNARY_GRP3 105 153 #define OP_CLC 106 154 #define OP_STC 107 155 #define OP_CLI 108 156 #define OP_STI 109 157 #define OP_CLD 110 158 #define OP_STD 111 159 #define OP_INC_GRP4 112 160 #define OP_IND_GRP5 113 161 #define OP_GRP6 114 162 #define OP_GRP7 115 163 #define OP_LAR 116 164 #define OP_LSL 117 165 #define OP_SYSCALL 118 166 #define OP_CLTS 119 167 #define OP_SYSRET 120 168 #define OP_INVD 121 169 #define OP_WBINVD 122 170 #define OP_ILLUD2 123 171 #define OP_FEMMS 124 172 #define OP_3DNOW 125 173 #define OP_MOVUPS 126 174 #define OP_MOVLPS 127 175 #define OP_UNPCKLPS 128 176 #define OP_MOVHPS 129 177 #define OP_UNPCKHPS 130 178 #define OP_PREFETCH_GRP16 131 179 #define OP_MOV_CR 132 180 #define OP_MOVAPS 133 181 #define OP_CVTPI2PS 134 182 #define OP_MOVNTPS 135 183 #define OP_CVTTPS2PI 136 184 #define OP_CVTPS2PI 137 185 #define OP_UCOMISS 138 186 #define OP_COMISS 139 187 #define OP_WRMSR 140 188 #define OP_RDTSC 141 189 #define OP_RDMSR 142 190 #define OP_RDPMC 143 191 #define OP_SYSENTER 144 192 #define OP_SYSEXIT 145 193 #define OP_PAUSE 146 194 #define OP_CMOVO 147 195 #define OP_CMOVNO 148 196 #define OP_CMOVC 149 197 #define OP_CMOVNC 150 198 #define OP_CMOVZ 151 199 #define OP_CMOVNZ 152 200 #define OP_CMOVBE 153 201 #define OP_CMOVNBE 154 202 #define OP_CMOVS 155 203 #define OP_CMOVNS 156 204 #define OP_CMOVP 157 205 #define OP_CMOVNP 158 206 #define OP_CMOVL 159 207 #define OP_CMOVNL 160 208 #define OP_CMOVLE 161 209 #define OP_CMOVNLE 162 210 #define OP_MOVMSKPS 163 211 #define OP_SQRTPS 164 212 #define OP_RSQRTPS 165 213 #define OP_RCPPS 166 214 #define OP_ANDPS 167 215 #define OP_ANDNPS 168 216 #define OP_ORPS 169 217 #define OP_XORPS 170 218 #define OP_ADDPS 171 219 #define OP_MULPS 172 220 #define OP_CVTPS2PD 173 221 #define OP_CVTDQ2PS 174 222 #define OP_SUBPS 175 223 #define OP_MINPS 176 224 #define OP_DIVPS 177 225 #define OP_MAXPS 178 226 #define OP_PUNPCKLBW 179 227 #define OP_PUNPCKLWD 180 228 #define OP_PUNPCKLDQ 181 229 #define OP_PACKSSWB 182 230 #define OP_PCMPGTB 183 231 #define OP_PCMPGTW 184 232 #define OP_PCMPGTD 185 233 #define OP_PACKUSWB 186 234 #define OP_PUNPCKHBW 187 235 #define OP_PUNPCKHWD 188 236 #define OP_PUNPCKHDQ 189 237 #define OP_PACKSSDW 190 238 #define OP_MOVD 191 239 #define OP_MOVQ 192 240 #define OP_PSHUFW 193 241 #define OP_3B_ESC4 194 242 #define OP_3B_ESC5 195 243 244 #define OP_PCMPEQB 196 245 #define OP_PCMPEQW 197 246 #define OP_PCMPEQD 198 247 #define OP_SETO 199 248 #define OP_SETNO 200 249 #define OP_SETC 201 250 #define OP_SETNC 202 251 #define OP_SETE 203 252 #define OP_SETNE 204 253 #define OP_SETBE 205 254 #define OP_SETNBE 206 255 #define OP_SETS 207 256 #define OP_SETNS 208 257 #define OP_SETP 209 258 #define OP_SETNP 210 259 #define OP_SETL 211 260 #define OP_SETNL 212 261 #define OP_SETLE 213 262 #define OP_SETNLE 214 263 #define OP_CPUID 215 264 #define OP_BT 216 265 #define OP_SHLD 217 266 #define OP_RSM 218 267 #define OP_BTS 219 268 #define OP_SHRD 220 269 #define OP_GRP15 221 270 #define OP_CMPXCHG 222 271 #define OP_LSS 223 272 #define OP_BTR 224 273 #define OP_LFS 225 274 #define OP_LGS 226 275 #define OP_MOVZX 227 276 #define OP_GRP10_INV 228 277 #define OP_GRP8 229 278 #define OP_BTC 230 279 #define OP_BSF 231 280 #define OP_BSR 232 281 #define OP_MOVSX 233 282 #define OP_XADD 234 283 #define OP_CMPPS 235 284 #define OP_MOVNTI 236 285 #define OP_PINSRW 237 286 #define OP_PEXTRW 238 287 #define OP_SHUFPS 239 288 #define OP_GRP9 240 289 #define OP_BSWAP 241 290 #define OP_PSRLW 242 291 #define OP_PSRLD 243 292 #define OP_PSRLQ 244 293 #define OP_PADDQ 245 294 #define OP_PMULLW 246 295 #define OP_PMOVMSKB 247 296 #define OP_PSUBUSB 248 297 #define OP_PSUBUSW 249 298 #define OP_PMINUB 250 299 #define OP_PAND 251 300 #define OP_PADDUSB 252 301 #define OP_PADDUSW 253 302 #define OP_PMAXUB 254 303 #define OP_PANDN 255 304 #define OP_PAVGN 256 305 #define OP_PSRAW 257 306 #define OP_PSRAD 258 307 #define OP_PAVGW 259 308 #define OP_PMULHUW 260 309 #define OP_PMULHW 261 310 #define OP_MOVNTQ 262 311 #define OP_PSUBSB 263 312 #define OP_PSUBSW 264 313 #define OP_PMINSW 265 314 #define OP_POR 266 315 #define OP_PADDSB 267 316 #define OP_PADDSW 268 317 #define OP_PMAXSW 269 318 #define OP_PXOR 270 319 #define OP_PSLLW 271 320 #define OP_PSLLD 272 321 #define OP_PSSQ 273 322 #define OP_PMULUDQ 274 323 #define OP_PADDWD 275 324 #define OP_PADBW 276 325 #define OP_PMASKMOVQ 277 326 #define OP_PSUBB 278 327 #define OP_PSUBW 279 328 329 #define OP_PSUBD 281 330 #define OP_PADDB 282 331 #define OP_PADDW 283 332 #define OP_PADDD 284 333 #define OP_MOVUPD 285 334 #define OP_MOVLPD 286 335 #define OP_UNPCKLPD 287 336 #define OP_UNPCKHPD 288 337 #define OP_MOVHPD 289 338 339 #define OP_MOVAPD 291 340 #define OP_CVTPI2PD 292 341 #define OP_MOVNTPD 293 342 #define OP_CVTTPD2PI 294 343 #define OP_CVTPD2PI 295 344 #define OP_UCOMISD 296 345 #define OP_COMISD 297 346 #define OP_MOVMSKPD 298 347 #define OP_SQRTPD 299 348 #define OP_ANDPD 301 349 #define OP_ANDNPD 302 350 #define OP_ORPD 303 351 #define OP_XORPD 304 352 #define OP_ADDPD 305 353 #define OP_MULPD 306 354 #define OP_CVTPD2PS 307 355 #define OP_CVTPS2DQ 308 356 #define OP_SUBPD 309 357 #define OP_MINPD 310 358 #define OP_DIVPD 311 359 #define OP_MAXPD 312 360 361 #define OP_GRP12 313 362 #define OP_GRP13 314 363 #define OP_GRP14 315 364 #define OP_EMMS 316 365 #define OP_MMX_UD78 317 366 #define OP_MMX_UD79 318 367 #define OP_MMX_UD7A 319 368 #define OP_MMX_UD7B 320 369 #define OP_MMX_UD7C 321 370 #define OP_MMX_UD7D 322 371 372 373 #define OP_PUNPCKLQDQ 325 374 #define OP_PUNPCKHQD 326 375 376 #define OP_MOVDQA 328 377 #define OP_PSHUFD 329 378 379 380 381 #define OP_CMPPD 334 382 #define OP_SHUFPD 337 383 384 385 #define OP_CVTTPD2DQ 353 386 #define OP_MOVNTDQ 354 387 388 #define OP_PSHUFB 355 389 #define OP_PHADDW 356 390 #define OP_PHADDD 357 391 #define OP_PHADDSW 358 392 #define OP_PMADDUBSW 359 393 #define OP_PHSUBW 360 394 #define OP_PHSUBD 361 395 #define OP_PHSUBSW 362 396 #define OP_PSIGNB 363 397 #define OP_PSIGNW 364 398 #define OP_PSIGND 365 399 #define OP_PMULHRSW 366 400 #define OP_PBLENDVB 367 401 #define OP_BLENDVPS 368 402 #define OP_BLENDVPD 369 403 #define OP_PTEST 370 404 #define OP_PABSB 371 405 #define OP_PABSW 372 406 #define OP_PABSD 373 407 408 #define OP_PMASKMOVDQU 376 409 #define OP_MOVSD 377 410 #define OP_CVTSI2SD 378 411 #define OP_CVTTSD2SI 379 412 #define OP_CVTSD2SI 380 413 #define OP_SQRTSD 381 414 #define OP_ADDSD 382 415 #define OP_MULSD 383 416 #define OP_CVTSD2SS 384 417 #define OP_SUBSD 385 418 #define OP_MINSD 386 419 #define OP_DIVSD 387 420 #define OP_MAXSD 388 421 #define OP_PSHUFLW 389 422 #define OP_CMPSD 390 423 #define OP_MOVDQ2Q 391 424 #define OP_CVTPD2DQ 392 425 #define OP_MOVSS 393 426 #define OP_CVTSI2SS 394 427 #define OP_CVTTSS2SI 395 428 #define OP_CVTSS2SI 396 429 #define OP_SQRTSS 397 430 #define OP_RSQRTSS 398 431 #define OP_ADDSS 399 432 #define OP_MULSS 401 433 #define OP_CVTTPS2DQ 403 434 #define OP_SUBSS 404 435 #define OP_MINSS 405 436 #define OP_DIVSS 406 437 #define OP_MAXSS 407 438 #define OP_MOVDQU 408 439 #define OP_PSHUFHW 409 440 #define OP_CMPSS 410 441 #define OP_MOVQ2DQ 411 442 #define OP_CVTDQ2PD 412 46 OP_INVALID, 47 OP_OPSIZE, 48 OP_ADDRSIZE, 49 OP_SEG, 50 OP_REPNE, 51 OP_REPE, 52 OP_REX, 53 OP_LOCK, 54 OP_LAST_PREFIX = OP_LOCK, /* Last prefix for disassembler */ 55 OP_AND, 56 OP_OR, 57 OP_DAA, 58 OP_SUB, 59 OP_DAS, 60 OP_XOR, 61 OP_AAA, 62 OP_CMP, 63 OP_IMM_GRP1, 64 OP_AAS, 65 OP_INC, 66 OP_DEC, 67 OP_PUSHA, 68 OP_POPA, 69 OP_BOUND, 70 OP_ARPL, 71 OP_PUSH, 72 OP_POP, 73 OP_IMUL, 74 OP_INSB, 75 OP_INSWD, 76 OP_OUTSB, 77 OP_OUTSWD, 78 OP_JO, 79 OP_JNO, 80 OP_JC, 81 OP_JNC, 82 OP_JE, 83 OP_JNE, 84 OP_JBE, 85 OP_JNBE, 86 OP_JS, 87 OP_JNS, 88 OP_JP, 89 OP_JNP, 90 OP_JL, 91 OP_JNL, 92 OP_JLE, 93 OP_JNLE, 94 OP_ADD, 95 OP_TEST, 96 OP_XCHG, 97 OP_MOV, 98 OP_LEA, 99 OP_NOP, 100 OP_CBW, 101 OP_CWD, 102 OP_CALL, 103 OP_WAIT, 104 OP_PUSHF, 105 OP_POPF, 106 OP_SAHF, 107 OP_LAHF, 108 OP_MOVSB, 109 OP_MOVSWD, 110 OP_CMPSB, 111 OP_CMPWD, 112 OP_STOSB, 113 OP_STOSWD, 114 OP_LODSB, 115 OP_LODSWD, 116 OP_SCASB, 117 OP_SCASWD, 118 OP_SHIFT_GRP2, 119 OP_RETN, 120 OP_LES, 121 OP_LDS, 122 OP_ENTER, 123 OP_LEAVE, 124 OP_RETF, 125 OP_INT3, 126 OP_INT, 127 OP_INTO, 128 OP_IRET, 129 OP_AAM, 130 OP_AAD, 131 OP_XLAT, 132 OP_ESCF0, 133 OP_ESCF1, 134 OP_ESCF2, 135 OP_ESCF3, 136 OP_ESCF4, 137 OP_ESCF5, 138 OP_ESCF6, 139 OP_ESCF7, 140 OP_LOOPNE, 141 OP_LOOPE, 142 OP_LOOP, 143 OP_JECXZ, 144 OP_IN, 145 OP_OUT, 146 OP_JMP, 147 OP_2B_ESC, 148 OP_ADC, 149 OP_SBB, 150 OP_HLT, 151 OP_CMC, 152 OP_UNARY_GRP3, 153 OP_CLC, 154 OP_STC, 155 OP_CLI, 156 OP_STI, 157 OP_CLD, 158 OP_STD, 159 OP_INC_GRP4, 160 OP_IND_GRP5, 161 OP_GRP6, 162 OP_GRP7, 163 OP_LAR, 164 OP_LSL, 165 OP_SYSCALL, 166 OP_CLTS, 167 OP_SYSRET, 168 OP_INVD, 169 OP_WBINVD, 170 OP_ILLUD2, 171 OP_FEMMS, 172 OP_3DNOW, 173 OP_MOVUPS, 174 OP_MOVLPS, 175 OP_UNPCKLPS, 176 OP_MOVHPS, 177 OP_UNPCKHPS, 178 OP_PREFETCH_GRP16, 179 OP_MOV_CR, 180 OP_MOVAPS, 181 OP_CVTPI2PS, 182 OP_MOVNTPS, 183 OP_CVTTPS2PI, 184 OP_CVTPS2PI, 185 OP_UCOMISS, 186 OP_COMISS, 187 OP_WRMSR, 188 OP_RDTSC, 189 OP_RDMSR, 190 OP_RDPMC, 191 OP_SYSENTER, 192 OP_SYSEXIT, 193 OP_PAUSE, 194 OP_CMOVO, 195 OP_CMOVNO, 196 OP_CMOVC, 197 OP_CMOVNC, 198 OP_CMOVZ, 199 OP_CMOVNZ, 200 OP_CMOVBE, 201 OP_CMOVNBE, 202 OP_CMOVS, 203 OP_CMOVNS, 204 OP_CMOVP, 205 OP_CMOVNP, 206 OP_CMOVL, 207 OP_CMOVNL, 208 OP_CMOVLE, 209 OP_CMOVNLE, 210 OP_MOVMSKPS, 211 OP_SQRTPS, 212 OP_RSQRTPS, 213 OP_RCPPS, 214 OP_ANDPS, 215 OP_ANDNPS, 216 OP_ORPS, 217 OP_XORPS, 218 OP_ADDPS, 219 OP_MULPS, 220 OP_CVTPS2PD, 221 OP_CVTDQ2PS, 222 OP_SUBPS, 223 OP_MINPS, 224 OP_DIVPS, 225 OP_MAXPS, 226 OP_PUNPCKLBW, 227 OP_PUNPCKLWD, 228 OP_PUNPCKLDQ, 229 OP_PACKSSWB, 230 OP_PCMPGTB, 231 OP_PCMPGTW, 232 OP_PCMPGTD, 233 OP_PACKUSWB, 234 OP_PUNPCKHBW, 235 OP_PUNPCKHWD, 236 OP_PUNPCKHDQ, 237 OP_PACKSSDW, 238 OP_MOVD, 239 OP_MOVQ, 240 OP_PSHUFW, 241 OP_3B_ESC4, 242 OP_3B_ESC5, 243 OP_PCMPEQB, 244 OP_PCMPEQW, 245 OP_PCMPEQD, 246 OP_SETO, 247 OP_SETNO, 248 OP_SETC, 249 OP_SETNC, 250 OP_SETE, 251 OP_SETNE, 252 OP_SETBE, 253 OP_SETNBE, 254 OP_SETS, 255 OP_SETNS, 256 OP_SETP, 257 OP_SETNP, 258 OP_SETL, 259 OP_SETNL, 260 OP_SETLE, 261 OP_SETNLE, 262 OP_CPUID, 263 OP_BT, 264 OP_SHLD, 265 OP_RSM, 266 OP_BTS, 267 OP_SHRD, 268 OP_GRP15, 269 OP_CMPXCHG, 270 OP_LSS, 271 OP_BTR, 272 OP_LFS, 273 OP_LGS, 274 OP_MOVZX, 275 OP_GRP10_INV, 276 OP_GRP8, 277 OP_BTC, 278 OP_BSF, 279 OP_BSR, 280 OP_MOVSX, 281 OP_XADD, 282 OP_CMPPS, 283 OP_MOVNTI, 284 OP_PINSRW, 285 OP_PEXTRW, 286 OP_SHUFPS, 287 OP_GRP9, 288 OP_BSWAP, 289 OP_PSRLW, 290 OP_PSRLD, 291 OP_PSRLQ, 292 OP_PADDQ, 293 OP_PMULLW, 294 OP_PMOVMSKB, 295 OP_PSUBUSB, 296 OP_PSUBUSW, 297 OP_PMINUB, 298 OP_PAND, 299 OP_PADDUSB, 300 OP_PADDUSW, 301 OP_PMAXUB, 302 OP_PANDN, 303 OP_PAVGN, 304 OP_PSRAW, 305 OP_PSRAD, 306 OP_PAVGW, 307 OP_PMULHUW, 308 OP_PMULHW, 309 OP_MOVNTQ, 310 OP_PSUBSB, 311 OP_PSUBSW, 312 OP_PMINSW, 313 OP_POR, 314 OP_PADDSB, 315 OP_PADDSW, 316 OP_PMAXSW, 317 OP_PXOR, 318 OP_PSLLW, 319 OP_PSLLD, 320 OP_PSSQ, 321 OP_PMULUDQ, 322 OP_PADDWD, 323 OP_PADBW, 324 OP_PMASKMOVQ, 325 OP_PSUBB, 326 OP_PSUBW, 327 OP_PSUBD, 328 OP_PADDB, 329 OP_PADDW, 330 OP_PADDD, 331 OP_MOVUPD, 332 OP_MOVLPD, 333 OP_UNPCKLPD, 334 OP_UNPCKHPD, 335 OP_MOVHPD, 336 OP_MOVAPD, 337 OP_CVTPI2PD, 338 OP_MOVNTPD, 339 OP_CVTTPD2PI, 340 OP_CVTPD2PI, 341 OP_UCOMISD, 342 OP_COMISD, 343 OP_MOVMSKPD, 344 OP_SQRTPD, 345 OP_ANDPD, 346 OP_ANDNPD, 347 OP_ORPD, 348 OP_XORPD, 349 OP_ADDPD, 350 OP_MULPD, 351 OP_CVTPD2PS, 352 OP_CVTPS2DQ, 353 OP_SUBPD, 354 OP_MINPD, 355 OP_DIVPD, 356 OP_MAXPD, 357 OP_GRP12, 358 OP_GRP13, 359 OP_GRP14, 360 OP_EMMS, 361 OP_MMX_UD78, 362 OP_MMX_UD79, 363 OP_MMX_UD7A, 364 OP_MMX_UD7B, 365 OP_MMX_UD7C, 366 OP_MMX_UD7D, 367 OP_PUNPCKLQDQ, 368 OP_PUNPCKHQD, 369 OP_MOVDQA, 370 OP_PSHUFD, 371 OP_CMPPD, 372 OP_SHUFPD, 373 OP_CVTTPD2DQ, 374 OP_MOVNTDQ, 375 OP_PSHUFB, 376 OP_PHADDW, 377 OP_PHADDD, 378 OP_PHADDSW, 379 OP_PMADDUBSW, 380 OP_PHSUBW, 381 OP_PHSUBD, 382 OP_PHSUBSW, 383 OP_PSIGNB, 384 OP_PSIGNW, 385 OP_PSIGND, 386 OP_PMULHRSW, 387 OP_PBLENDVB, 388 OP_BLENDVPS, 389 OP_BLENDVPD, 390 OP_PTEST, 391 OP_PABSB, 392 OP_PABSW, 393 OP_PABSD, 394 OP_MOVBEGM, 395 OP_MOVBEMG, 396 OP_CRC32GDEB, 397 OP_CRC32GDEY, 398 OP_POPCNT, 399 OP_TZCNT, 400 OP_LZCNT, 401 OP_ADCX, 402 OP_ADOX, 403 OP_ANDN, 404 OP_BZHI, 405 OP_BEXTR, 406 OP_PMASKMOVDQU, 407 OP_MOVSD, 408 OP_CVTSI2SD, 409 OP_CVTTSD2SI, 410 OP_CVTSD2SI, 411 OP_SQRTSD, 412 OP_ADDSD, 413 OP_MULSD, 414 OP_CVTSD2SS, 415 OP_SUBSD, 416 OP_MINSD, 417 OP_DIVSD, 418 OP_MAXSD, 419 OP_PSHUFLW, 420 OP_CMPSD, 421 OP_MOVDQ2Q, 422 OP_CVTPD2DQ, 423 OP_MOVSS, 424 OP_CVTSI2SS, 425 OP_CVTTSS2SI, 426 OP_CVTSS2SI, 427 OP_SQRTSS, 428 OP_RSQRTSS, 429 OP_ADDSS, 430 OP_MULSS, 431 OP_CVTTPS2DQ, 432 OP_SUBSS, 433 OP_MINSS, 434 OP_DIVSS, 435 OP_MAXSS, 436 OP_MOVDQU, 437 OP_PSHUFHW, 438 OP_CMPSS, 439 OP_MOVQ2DQ, 440 OP_CVTDQ2PD, 443 441 /** @} */ 444 442 445 443 /** @name Floating point ops 446 * @{ 447 */ 448 #define OP_FADD 413 449 #define OP_FMUL 414 450 #define OP_FCOM 415 451 #define OP_FCOMP 416 452 #define OP_FSUB 417 453 #define OP_FSUBR 418 454 #define OP_FDIV 419 455 #define OP_FDIVR 420 456 #define OP_FLD 421 457 #define OP_FST 422 458 #define OP_FSTP 423 459 #define OP_FLDENV 424 460 461 #define OP_FSTENV 426 462 #define OP_FSTCW 427 463 #define OP_FXCH 428 464 #define OP_FNOP 429 465 #define OP_FCHS 430 466 #define OP_FABS 431 467 468 #define OP_FLD1 433 469 #define OP_FLDL2T 434 470 #define OP_FLDL2E 435 471 #define OP_FLDPI 436 472 #define OP_FLDLG2 437 473 #define OP_FLDLN2 438 474 #define OP_FLDZ 439 475 #define OP_F2XM1 440 476 #define OP_FYL2X 441 477 #define OP_FPTAN 442 478 #define OP_FPATAN 443 479 #define OP_FXTRACT 444 480 #define OP_FREM1 445 481 #define OP_FDECSTP 446 482 #define OP_FINCSTP 447 483 #define OP_FPREM 448 484 #define OP_FYL2XP1 449 485 #define OP_FSQRT 450 486 #define OP_FSINCOS 451 487 #define OP_FRNDINT 452 488 #define OP_FSCALE 453 489 #define OP_FSIN 454 490 #define OP_FCOS 455 491 #define OP_FIADD 456 492 #define OP_FIMUL 457 493 #define OP_FISUB 460 494 #define OP_FISUBR 461 495 #define OP_FIDIV 462 496 #define OP_FIDIVR 463 497 #define OP_FCMOVB 464 498 #define OP_FCMOVE 465 499 #define OP_FCMOVBE 466 500 #define OP_FCMOVU 467 501 #define OP_FUCOMPP 468 502 #define OP_FILD 469 503 #define OP_FIST 470 504 #define OP_FISTP 471 505 #define OP_FCMOVNB 474 506 #define OP_FCMOVNE 475 507 #define OP_FCMOVNBE 476 508 #define OP_FCMOVNU 477 509 #define OP_FCLEX 478 510 #define OP_FINIT 479 511 #define OP_FUCOMI 480 512 #define OP_FCOMI 481 513 #define OP_FRSTOR 482 514 #define OP_FSAVE 483 515 #define OP_FNSTSW 484 516 #define OP_FFREE 485 517 #define OP_FUCOM 486 518 #define OP_FUCOMP 487 519 #define OP_FICOM 490 520 #define OP_FICOMP 491 521 #define OP_FADDP 496 522 #define OP_FMULP 497 523 #define OP_FCOMPP 498 524 #define OP_FSUBRP 499 525 #define OP_FSUBP 500 526 #define OP_FDIVRP 501 527 #define OP_FDIVP 502 528 #define OP_FBLD 503 529 #define OP_FBSTP 504 530 #define OP_FCOMIP 506 531 #define OP_FUCOMIP 507 444 * @{ */ 445 OP_FADD, 446 OP_FMUL, 447 OP_FCOM, 448 OP_FCOMP, 449 OP_FSUB, 450 OP_FSUBR, 451 OP_FDIV, 452 OP_FDIVR, 453 OP_FLD, 454 OP_FST, 455 OP_FSTP, 456 OP_FLDENV, 457 OP_FSTENV, 458 OP_FSTCW, 459 OP_FXCH, 460 OP_FNOP, 461 OP_FCHS, 462 OP_FABS, 463 OP_FLD1, 464 OP_FLDL2T, 465 OP_FLDL2E, 466 OP_FLDPI, 467 OP_FLDLG2, 468 OP_FLDLN2, 469 OP_FLDZ, 470 OP_F2XM1, 471 OP_FYL2X, 472 OP_FPTAN, 473 OP_FPATAN, 474 OP_FXTRACT, 475 OP_FREM1, 476 OP_FDECSTP, 477 OP_FINCSTP, 478 OP_FPREM, 479 OP_FYL2XP1, 480 OP_FSQRT, 481 OP_FSINCOS, 482 OP_FRNDINT, 483 OP_FSCALE, 484 OP_FSIN, 485 OP_FCOS, 486 OP_FIADD, 487 OP_FIMUL, 488 OP_FISUB, 489 OP_FISUBR, 490 OP_FIDIV, 491 OP_FIDIVR, 492 OP_FCMOVB, 493 OP_FCMOVE, 494 OP_FCMOVBE, 495 OP_FCMOVU, 496 OP_FUCOMPP, 497 OP_FILD, 498 OP_FIST, 499 OP_FISTP, 500 OP_FCMOVNB, 501 OP_FCMOVNE, 502 OP_FCMOVNBE, 503 OP_FCMOVNU, 504 OP_FCLEX, 505 OP_FINIT, 506 OP_FUCOMI, 507 OP_FCOMI, 508 OP_FRSTOR, 509 OP_FSAVE, 510 OP_FNSTSW, 511 OP_FFREE, 512 OP_FUCOM, 513 OP_FUCOMP, 514 OP_FICOM, 515 OP_FICOMP, 516 OP_FADDP, 517 OP_FMULP, 518 OP_FCOMPP, 519 OP_FSUBRP, 520 OP_FSUBP, 521 OP_FDIVRP, 522 OP_FDIVP, 523 OP_FBLD, 524 OP_FBSTP, 525 OP_FCOMIP, 526 OP_FUCOMIP, 532 527 /** @} */ 533 528 534 529 /** @name 3DNow! 535 * @{ 536 */ 537 #define OP_PI2FW 508 538 #define OP_PI2FD 509 539 #define OP_PF2IW 510 540 #define OP_PF2ID 511 541 #define OP_PFPNACC 512 542 #define OP_PFCMPGE 513 543 #define OP_PFMIN 514 544 #define OP_PFRCP 515 545 #define OP_PFRSQRT 516 546 #define OP_PFSUB 517 547 #define OP_PFADD 518 548 #define OP_PFCMPGT 519 549 #define OP_PFMAX 520 550 #define OP_PFRCPIT1 521 551 #define OP_PFRSQRTIT1 522 552 #define OP_PFSUBR 523 553 #define OP_PFACC 524 554 #define OP_PFCMPEQ 525 555 #define OP_PFMUL 526 556 #define OP_PFRCPIT2 527 557 #define OP_PFMULHRW 528 558 #define OP_PFSWAPD 529 559 #define OP_PAVGUSB 530 560 #define OP_PFNACC 531 561 #define OP_ROL 532 562 #define OP_ROR 533 563 #define OP_RCL 534 564 #define OP_RCR 535 565 #define OP_SHL 536 566 #define OP_SHR 537 567 #define OP_SAR 538 568 #define OP_NOT 539 569 #define OP_NEG 540 570 #define OP_MUL 541 571 #define OP_DIV 542 572 #define OP_IDIV 543 573 #define OP_SLDT 544 574 #define OP_STR 545 575 #define OP_LLDT 546 576 #define OP_LTR 547 577 #define OP_VERR 548 578 #define OP_VERW 549 579 #define OP_SGDT 550 580 #define OP_LGDT 551 581 #define OP_SIDT 552 582 #define OP_LIDT 553 583 #define OP_SMSW 554 584 #define OP_LMSW 555 585 #define OP_INVLPG 556 586 #define OP_CMPXCHG8B 557 587 #define OP_PSLLQ 558 588 #define OP_PSRLDQ 559 589 #define OP_PSLLDQ 560 590 #define OP_FXSAVE 561 591 #define OP_FXRSTOR 562 592 #define OP_LDMXCSR 563 593 #define OP_STMXCSR 564 594 #define OP_LFENCE 565 595 #define OP_MFENCE 566 596 #define OP_SFENCE 567 597 #define OP_PREFETCH 568 598 #define OP_MONITOR 569 599 #define OP_MWAIT 570 600 #define OP_CLFLUSH 571 601 602 #define OP_MOV_DR 600 603 #define OP_MOV_TR 601 604 605 #define OP_SWAPGS 610 606 530 * @{ */ 531 OP_PI2FW, 532 OP_PI2FD, 533 OP_PF2IW, 534 OP_PF2ID, 535 OP_PFPNACC, 536 OP_PFCMPGE, 537 OP_PFMIN, 538 OP_PFRCP, 539 OP_PFRSQRT, 540 OP_PFSUB, 541 OP_PFADD, 542 OP_PFCMPGT, 543 OP_PFMAX, 544 OP_PFRCPIT1, 545 OP_PFRSQRTIT1, 546 OP_PFSUBR, 547 OP_PFACC, 548 OP_PFCMPEQ, 549 OP_PFMUL, 550 OP_PFRCPIT2, 551 OP_PFMULHRW, 552 OP_PFSWAPD, 553 OP_PAVGUSB, 554 OP_PFNACC, 555 OP_ROL, 556 OP_ROR, 557 OP_RCL, 558 OP_RCR, 559 OP_SHL, 560 OP_SHR, 561 OP_SAR, 562 OP_NOT, 563 OP_NEG, 564 OP_MUL, 565 OP_DIV, 566 OP_IDIV, 567 OP_SLDT, 568 OP_STR, 569 OP_LLDT, 570 OP_LTR, 571 OP_VERR, 572 OP_VERW, 573 OP_SGDT, 574 OP_LGDT, 575 OP_SIDT, 576 OP_LIDT, 577 OP_SMSW, 578 OP_LMSW, 579 OP_INVLPG, 580 OP_CMPXCHG8B, 581 OP_PSLLQ, 582 OP_PSRLDQ, 583 OP_PSLLDQ, 584 OP_FXSAVE, 585 OP_FXRSTOR, 586 OP_LDMXCSR, 587 OP_STMXCSR, 588 OP_LFENCE, 589 OP_MFENCE, 590 OP_SFENCE, 591 OP_PREFETCH, 592 OP_MONITOR, 593 OP_MWAIT, 594 OP_CLFLUSH, 595 OP_MOV_DR, 596 OP_MOV_TR, 597 OP_SWAPGS, 607 598 /** @name VT-x instructions 608 609 #define OP_VMREAD 650 610 #define OP_VMWRITE 651 611 #define OP_VMCALL 652 612 #define OP_VMXON 653 613 #define OP_VMXOFF 654 614 #define OP_VMCLEAR 655 615 #define OP_VMLAUNCH 656 616 #define OP_VMRESUME 657 617 #define OP_VMPTRLD 658 618 #define OP_VMPTRST 659 619 #define OP_INVEPT 660 620 #define OP_INVVPID 661 599 * @{ */ 600 OP_VMREAD, 601 OP_VMWRITE, 602 OP_VMCALL, 603 OP_VMXON, 604 OP_VMXOFF, 605 OP_VMCLEAR, 606 OP_VMLAUNCH, 607 OP_VMRESUME, 608 OP_VMPTRLD, 609 OP_VMPTRST, 610 OP_INVEPT, 611 OP_INVVPID, 621 612 /** @} */ 622 623 613 /** @name 64 bits instruction 624 614 * @{ */ 625 #define OP_MOVSXD 700 626 /** @} */ 627 615 616 OP_MOVSXD 628 617 /** @} */ 629 618 }; 619 /** @} */ 630 620 631 621 /** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1, … … 636 626 637 627 /* NOTE: Register order is important for translations!! */ 638 #define OP_PARM_NONE 0 639 #define OP_PARM_REG_EAX 1 640 #define OP_PARM_REG_GEN32_START OP_PARM_REG_EAX 641 #define OP_PARM_REG_ECX 2 642 #define OP_PARM_REG_EDX 3 643 #define OP_PARM_REG_EBX 4 644 #define OP_PARM_REG_ESP 5 645 #define OP_PARM_REG_EBP 6 646 #define OP_PARM_REG_ESI 7 647 #define OP_PARM_REG_EDI 8 648 #define OP_PARM_REG_GEN32_END OP_PARM_REG_EDI 649 650 #define OP_PARM_REG_ES 9 651 #define OP_PARM_REG_SEG_START OP_PARM_REG_ES 652 #define OP_PARM_REG_CS 10 653 #define OP_PARM_REG_SS 11 654 #define OP_PARM_REG_DS 12 655 #define OP_PARM_REG_FS 13 656 #define OP_PARM_REG_GS 14 657 #define OP_PARM_REG_SEG_END OP_PARM_REG_GS 658 659 #define OP_PARM_REG_AX 15 660 #define OP_PARM_REG_GEN16_START OP_PARM_REG_AX 661 #define OP_PARM_REG_CX 16 662 #define OP_PARM_REG_DX 17 663 #define OP_PARM_REG_BX 18 664 #define OP_PARM_REG_SP 19 665 #define OP_PARM_REG_BP 20 666 #define OP_PARM_REG_SI 21 667 #define OP_PARM_REG_DI 22 668 #define OP_PARM_REG_GEN16_END OP_PARM_REG_DI 669 670 #define OP_PARM_REG_AL 23 671 #define OP_PARM_REG_GEN8_START OP_PARM_REG_AL 672 #define OP_PARM_REG_CL 24 673 #define OP_PARM_REG_DL 25 674 #define OP_PARM_REG_BL 26 675 #define OP_PARM_REG_AH 27 676 #define OP_PARM_REG_CH 28 677 #define OP_PARM_REG_DH 29 678 #define OP_PARM_REG_BH 30 679 #define OP_PARM_REG_GEN8_END OP_PARM_REG_BH 680 681 #define OP_PARM_REGFP_0 31 682 #define OP_PARM_REG_FP_START OP_PARM_REGFP_0 683 #define OP_PARM_REGFP_1 32 684 #define OP_PARM_REGFP_2 33 685 #define OP_PARM_REGFP_3 34 686 #define OP_PARM_REGFP_4 35 687 #define OP_PARM_REGFP_5 36 688 #define OP_PARM_REGFP_6 37 689 #define OP_PARM_REGFP_7 38 690 #define OP_PARM_REG_FP_END OP_PARM_REGFP_7 691 692 #define OP_PARM_NTA 39 693 #define OP_PARM_T0 40 694 #define OP_PARM_T1 41 695 #define OP_PARM_T2 42 696 697 #define OP_PARM_1 43 698 699 #define OP_PARM_REX 50 700 #define OP_PARM_REX_START OP_PARM_REX 701 #define OP_PARM_REX_B 51 702 #define OP_PARM_REX_X 52 703 #define OP_PARM_REX_XB 53 704 #define OP_PARM_REX_R 54 705 #define OP_PARM_REX_RB 55 706 #define OP_PARM_REX_RX 56 707 #define OP_PARM_REX_RXB 57 708 #define OP_PARM_REX_W 58 709 #define OP_PARM_REX_WB 59 710 #define OP_PARM_REX_WX 60 711 #define OP_PARM_REX_WXB 61 712 #define OP_PARM_REX_WR 62 713 #define OP_PARM_REX_WRB 63 714 #define OP_PARM_REX_WRX 64 715 #define OP_PARM_REX_WRXB 65 716 717 #define OP_PARM_REG_RAX 100 718 #define OP_PARM_REG_GEN64_START OP_PARM_REG_RAX 719 #define OP_PARM_REG_RCX 101 720 #define OP_PARM_REG_RDX 102 721 #define OP_PARM_REG_RBX 103 722 #define OP_PARM_REG_RSP 104 723 #define OP_PARM_REG_RBP 105 724 #define OP_PARM_REG_RSI 106 725 #define OP_PARM_REG_RDI 107 726 #define OP_PARM_REG_R8 108 727 #define OP_PARM_REG_R9 109 728 #define OP_PARM_REG_R10 110 729 #define OP_PARM_REG_R11 111 730 #define OP_PARM_REG_R12 112 731 #define OP_PARM_REG_R13 113 732 #define OP_PARM_REG_R14 114 733 #define OP_PARM_REG_R15 115 734 #define OP_PARM_REG_GEN64_END OP_PARM_REG_R15 735 628 enum OP_PARM 629 { 630 OP_PARM_NONE, 631 632 OP_PARM_REG_EAX, 633 OP_PARM_REG_GEN32_START = OP_PARM_REG_EAX, 634 OP_PARM_REG_ECX, 635 OP_PARM_REG_EDX, 636 OP_PARM_REG_EBX, 637 OP_PARM_REG_ESP, 638 OP_PARM_REG_EBP, 639 OP_PARM_REG_ESI, 640 OP_PARM_REG_EDI, 641 OP_PARM_REG_GEN32_END = OP_PARM_REG_EDI, 642 643 OP_PARM_REG_ES, 644 OP_PARM_REG_SEG_START = OP_PARM_REG_ES, 645 OP_PARM_REG_CS, 646 OP_PARM_REG_SS, 647 OP_PARM_REG_DS, 648 OP_PARM_REG_FS, 649 OP_PARM_REG_GS, 650 OP_PARM_REG_SEG_END = OP_PARM_REG_GS, 651 652 OP_PARM_REG_AX, 653 OP_PARM_REG_GEN16_START = OP_PARM_REG_AX, 654 OP_PARM_REG_CX, 655 OP_PARM_REG_DX, 656 OP_PARM_REG_BX, 657 OP_PARM_REG_SP, 658 OP_PARM_REG_BP, 659 OP_PARM_REG_SI, 660 OP_PARM_REG_DI, 661 OP_PARM_REG_GEN16_END = OP_PARM_REG_DI, 662 663 OP_PARM_REG_AL, 664 OP_PARM_REG_GEN8_START = OP_PARM_REG_AL, 665 OP_PARM_REG_CL, 666 OP_PARM_REG_DL, 667 OP_PARM_REG_BL, 668 OP_PARM_REG_AH, 669 OP_PARM_REG_CH, 670 OP_PARM_REG_DH, 671 OP_PARM_REG_BH, 672 OP_PARM_REG_GEN8_END = OP_PARM_REG_BH, 673 674 OP_PARM_REGFP_0, 675 OP_PARM_REG_FP_START = OP_PARM_REGFP_0, 676 OP_PARM_REGFP_1, 677 OP_PARM_REGFP_2, 678 OP_PARM_REGFP_3, 679 OP_PARM_REGFP_4, 680 OP_PARM_REGFP_5, 681 OP_PARM_REGFP_6, 682 OP_PARM_REGFP_7, 683 OP_PARM_REG_FP_END = OP_PARM_REGFP_7, 684 685 OP_PARM_NTA, 686 OP_PARM_T0, 687 OP_PARM_T1, 688 OP_PARM_T2, 689 OP_PARM_1, 690 691 OP_PARM_REX, 692 OP_PARM_REX_START = OP_PARM_REX, 693 OP_PARM_REX_B, 694 OP_PARM_REX_X, 695 OP_PARM_REX_XB, 696 OP_PARM_REX_R, 697 OP_PARM_REX_RB, 698 OP_PARM_REX_RX, 699 OP_PARM_REX_RXB, 700 OP_PARM_REX_W, 701 OP_PARM_REX_WB, 702 OP_PARM_REX_WX, 703 OP_PARM_REX_WXB, 704 OP_PARM_REX_WR, 705 OP_PARM_REX_WRB, 706 OP_PARM_REX_WRX, 707 OP_PARM_REX_WRXB, 708 709 OP_PARM_REG_RAX, 710 OP_PARM_REG_GEN64_START = OP_PARM_REG_RAX, 711 OP_PARM_REG_RCX, 712 OP_PARM_REG_RDX, 713 OP_PARM_REG_RBX, 714 OP_PARM_REG_RSP, 715 OP_PARM_REG_RBP, 716 OP_PARM_REG_RSI, 717 OP_PARM_REG_RDI, 718 OP_PARM_REG_R8, 719 OP_PARM_REG_R9, 720 OP_PARM_REG_R10, 721 OP_PARM_REG_R11, 722 OP_PARM_REG_R12, 723 OP_PARM_REG_R13, 724 OP_PARM_REG_R14, 725 OP_PARM_REG_R15, 726 OP_PARM_REG_GEN64_END = OP_PARM_REG_R15 727 }; 736 728 737 729 #define OP_PARM_VTYPE(a) ((unsigned)a & 0xFE0) … … 779 771 #define OP_PARM_w 0xF 780 772 #define OP_PARM_z 0x10 773 #define OP_PARM_y 0x11 781 774 782 775 … … 789 782 #define OP_PARM_Ev (OP_PARM_E+OP_PARM_v) 790 783 #define OP_PARM_Ew (OP_PARM_E+OP_PARM_w) 784 #define OP_PARM_Ey (OP_PARM_E+OP_PARM_y) 791 785 #define OP_PARM_Fv (OP_PARM_F+OP_PARM_v) 792 786 #define OP_PARM_Gb (OP_PARM_G+OP_PARM_b) … … 794 788 #define OP_PARM_Gv (OP_PARM_G+OP_PARM_v) 795 789 #define OP_PARM_Gw (OP_PARM_G+OP_PARM_w) 790 #define OP_PARM_Gy (OP_PARM_G+OP_PARM_y) 796 791 #define OP_PARM_Ib (OP_PARM_I+OP_PARM_b) 797 792 #define OP_PARM_Id (OP_PARM_I+OP_PARM_d) … … 810 805 #define OP_PARM_Mdq (OP_PARM_M+OP_PARM_dq) 811 806 #define OP_PARM_Ms (OP_PARM_M+OP_PARM_s) 807 #define OP_PARM_My (OP_PARM_M+OP_PARM_y) 812 808 #define OP_PARM_Ob (OP_PARM_O+OP_PARM_b) 813 809 #define OP_PARM_Ov (OP_PARM_O+OP_PARM_v) -
TabularUnified trunk/src/VBox/Disassembler/DisasmCore.cpp ¶
r49480 r53007 813 813 subtype = (pDis->uAddrMode == DISCPUMODE_64BIT) ? OP_PARM_q : OP_PARM_d; 814 814 else 815 if (subtype == OP_PARM_v || subtype == OP_PARM_NONE )815 if (subtype == OP_PARM_v || subtype == OP_PARM_NONE || subtype == OP_PARM_y) 816 816 { 817 817 switch (pDis->uOpMode) … … 824 824 break; 825 825 case DISCPUMODE_16BIT: 826 subtype = OP_PARM_w; 826 if (subtype != OP_PARM_y) 827 subtype = OP_PARM_w; 827 828 break; 828 829 default: … … 1915 1916 /* Cancel prefix changes. */ 1916 1917 pDis->fPrefix &= ~DISPREFIX_OPSIZE; 1917 pDis->uOpMode = pDis->uCpuMode; 1918 1919 if (pDis->uCpuMode == DISCPUMODE_64BIT) 1920 { 1921 pDis->uOpMode = (pDis->fRexPrefix & DISPREFIX_REX_FLAGS_W ? DISCPUMODE_64BIT : DISCPUMODE_32BIT); 1922 } 1923 else 1924 pDis->uOpMode = pDis->uCpuMode; 1918 1925 } 1919 1926 break; … … 1981 1988 /* Cancel prefix changes. */ 1982 1989 pDis->fPrefix &= ~DISPREFIX_OPSIZE; 1983 pDis->uOpMode = pDis->uCpuMode; 1990 if (pDis->uCpuMode == DISCPUMODE_64BIT) 1991 { 1992 pDis->uOpMode = (pDis->fRexPrefix & DISPREFIX_REX_FLAGS_W ? DISCPUMODE_64BIT : DISCPUMODE_32BIT); 1993 } 1994 else 1995 pDis->uOpMode = pDis->uCpuMode; 1996 1984 1997 } 1985 1998 } … … 2001 2014 } 2002 2015 break; 2016 2017 case OP_REPE: /* 0xF3 */ 2018 if (g_apThreeByteMapX86_F30F38[pDis->bOpCode >> 4]) 2019 { 2020 pOpcode = g_apThreeByteMapX86_F30F38[pDis->bOpCode >> 4]; 2021 pOpcode = &pOpcode[pDis->bOpCode & 0xf]; 2022 2023 if (pOpcode->uOpcode != OP_INVALID) 2024 { 2025 /* Table entry is valid, so use the extension table. */ 2026 2027 /* Cancel prefix changes. */ 2028 pDis->fPrefix &= ~DISPREFIX_REP; 2029 } 2030 } 2003 2031 } 2004 2032 … … 2031 2059 /* Cancel prefix changes. */ 2032 2060 pDis->fPrefix &= ~DISPREFIX_OPSIZE; 2033 pDis->uOpMode = pDis->uCpuMode; 2061 if (pDis->uCpuMode == DISCPUMODE_64BIT) 2062 { 2063 pDis->uOpMode = (pDis->fRexPrefix & DISPREFIX_REX_FLAGS_W ? DISCPUMODE_64BIT : DISCPUMODE_32BIT); 2064 } 2065 else 2066 pDis->uOpMode = pDis->uCpuMode; 2067 2034 2068 } 2035 2069 } -
TabularUnified trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp ¶
r48948 r53007 603 603 { \ 604 604 case OP_PARM_v: \ 605 case OP_PARM_y: \ 605 606 switch (pDis->uOpMode) \ 606 607 { \ … … 617 618 case OP_PARM_dq: \ 618 619 if (OP_PARM_VTYPE(pParam->fParam) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \ 619 PUT_SZ(" qword "); \620 PUT_SZ("dqword "); \ 620 621 break; \ 621 622 case OP_PARM_p: break; /* see PUT_FAR */ \ -
TabularUnified trunk/src/VBox/Disassembler/DisasmInternal.h ¶
r41796 r53007 30 30 /** @name Index into g_apfnCalcSize and g_apfnFullDisasm. 31 31 * @{ */ 32 #define IDX_ParseNop 0 33 #define IDX_ParseModRM 1 34 #define IDX_UseModRM 2 35 #define IDX_ParseImmByte 3 36 #define IDX_ParseImmBRel 4 37 #define IDX_ParseImmUshort 5 38 #define IDX_ParseImmV 6 39 #define IDX_ParseImmVRel 7 40 #define IDX_ParseImmAddr 8 41 #define IDX_ParseFixedReg 9 42 #define IDX_ParseImmUlong 10 43 #define IDX_ParseImmQword 11 44 #define IDX_ParseTwoByteEsc 12 45 #define IDX_ParseImmGrpl 13 46 #define IDX_ParseShiftGrp2 14 47 #define IDX_ParseGrp3 15 48 #define IDX_ParseGrp4 16 49 #define IDX_ParseGrp5 17 50 #define IDX_Parse3DNow 18 51 #define IDX_ParseGrp6 19 52 #define IDX_ParseGrp7 20 53 #define IDX_ParseGrp8 21 54 #define IDX_ParseGrp9 22 55 #define IDX_ParseGrp10 23 56 #define IDX_ParseGrp12 24 57 #define IDX_ParseGrp13 25 58 #define IDX_ParseGrp14 26 59 #define IDX_ParseGrp15 27 60 #define IDX_ParseGrp16 28 61 #define IDX_ParseModFence 29 62 #define IDX_ParseYv 30 63 #define IDX_ParseYb 31 64 #define IDX_ParseXv 32 65 #define IDX_ParseXb 33 66 #define IDX_ParseEscFP 34 67 #define IDX_ParseNopPause 35 68 #define IDX_ParseImmByteSX 36 69 #define IDX_ParseImmZ 37 70 #define IDX_ParseThreeByteEsc4 38 71 #define IDX_ParseThreeByteEsc5 39 72 #define IDX_ParseImmAddrF 40 73 #define IDX_ParseInvOpModRM 41 74 #define IDX_ParseMax (IDX_ParseInvOpModRM+1) 32 enum IDX_Parse 33 { 34 IDX_ParseNop = 0, 35 IDX_ParseModRM, 36 IDX_UseModRM, 37 IDX_ParseImmByte, 38 IDX_ParseImmBRel, 39 IDX_ParseImmUshort, 40 IDX_ParseImmV, 41 IDX_ParseImmVRel, 42 IDX_ParseImmAddr, 43 IDX_ParseFixedReg, 44 IDX_ParseImmUlong, 45 IDX_ParseImmQword, 46 IDX_ParseTwoByteEsc, 47 IDX_ParseImmGrpl, 48 IDX_ParseShiftGrp2, 49 IDX_ParseGrp3, 50 IDX_ParseGrp4, 51 IDX_ParseGrp5, 52 IDX_Parse3DNow, 53 IDX_ParseGrp6, 54 IDX_ParseGrp7, 55 IDX_ParseGrp8, 56 IDX_ParseGrp9, 57 IDX_ParseGrp10, 58 IDX_ParseGrp12, 59 IDX_ParseGrp13, 60 IDX_ParseGrp14, 61 IDX_ParseGrp15, 62 IDX_ParseGrp16, 63 IDX_ParseModFence, 64 IDX_ParseYv, 65 IDX_ParseYb, 66 IDX_ParseXv, 67 IDX_ParseXb, 68 IDX_ParseEscFP, 69 IDX_ParseNopPause, 70 IDX_ParseImmByteSX, 71 IDX_ParseImmZ, 72 IDX_ParseThreeByteEsc4, 73 IDX_ParseThreeByteEsc5, 74 IDX_ParseImmAddrF, 75 IDX_ParseInvOpModRM, 76 IDX_ParseMax 77 }; 75 78 /** @} */ 76 79 … … 101 104 /** Three byte opcode map with prefix 0xF2 (0xF 0x38) */ 102 105 extern PCDISOPCODE const g_apThreeByteMapX86_F20F38[16]; 106 107 /** Three byte opcode map with prefix 0xF3 (0xF 0x38) */ 108 extern PCDISOPCODE const g_apThreeByteMapX86_F30F38[16]; 103 109 104 110 /** Three byte opcode map with prefix 0x66 (0xF 0x3A) */ -
TabularUnified trunk/src/VBox/Disassembler/DisasmTables.cpp ¶
r47453 r53007 529 529 OP("pcmpeqd %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQD, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, DISOPTYPE_HARMLESS), 530 530 OP("emms", 0, 0, 0, OP_EMMS, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 531 OP(" MMX UD 0x78", 0, 0, 0, OP_MMX_UD78,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), /** @todo 0x0f 0x78 VMREAD */532 OP(" MMX UD 0x79", 0, 0, 0, OP_MMX_UD79,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), /** @todo 0x0f 0x79 VMWRITE */531 OP("vmread %Ey,%Gy", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMREAD, OP_PARM_Ey, OP_PARM_Gy, OP_PARM_NONE, DISOPTYPE_HARMLESS|DISOPTYPE_FORCED_64_OP_SIZE), 532 OP("vmwrite %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMWRITE, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS|DISOPTYPE_FORCED_64_OP_SIZE), 533 533 OP("MMX UD 0x7A", 0, 0, 0, OP_MMX_UD7A,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 534 534 OP("MMX UD 0x7B", 0, 0, 0, OP_MMX_UD7B,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), … … 792 792 OP("pcmpeqd %Vdq,%Wdq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQD, OP_PARM_Vdq, OP_PARM_Vdq, OP_PARM_NONE, DISOPTYPE_HARMLESS), 793 793 INVALID_OPCODE, 794 OP("vmread %Ed,%Gd", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMREAD, OP_PARM_Ed, OP_PARM_Gd, OP_PARM_NONE, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED),795 OP("vmwrite %Gd,%Ed", IDX_ParseModRM, IDX_UseModRM, 0, OP_VMWRITE, OP_PARM_Gd, OP_PARM_Ed, OP_PARM_NONE, DISOPTYPE_DANGEROUS | DISOPTYPE_PRIVILEGED),794 INVALID_OPCODE, 795 INVALID_OPCODE, 796 796 INVALID_OPCODE, 797 797 INVALID_OPCODE, … … 1172 1172 1173 1173 /* b */ 1174 INVALID_OPCODE_BLOCK 1174 INVALID_OPCODE, 1175 INVALID_OPCODE, 1176 INVALID_OPCODE, 1177 INVALID_OPCODE, 1178 INVALID_OPCODE, 1179 INVALID_OPCODE, 1180 INVALID_OPCODE, 1181 INVALID_OPCODE, 1182 OP("popcnt %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_POPCNT, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1183 INVALID_OPCODE, 1184 INVALID_OPCODE, 1185 INVALID_OPCODE, 1186 OP("tzcnt %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_TZCNT, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1187 OP("lzcnt %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_LZCNT, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1188 INVALID_OPCODE, 1189 INVALID_OPCODE, 1175 1190 1176 1191 /* c */ … … 1276 1291 }; 1277 1292 1293 /** Three byte opcode map (0x0F 0x38 0xFx) */ 1294 const DISOPCODE g_aThreeByteMapX86_0F38_F[16] = 1295 { 1296 /* F */ 1297 OP("movbe %Gy,%My", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEGM, OP_PARM_Gy, OP_PARM_My, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1298 OP("movbe %My,%Gy", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEMG, OP_PARM_My, OP_PARM_Gy, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1299 INVALID_OPCODE, 1300 INVALID_OPCODE, 1301 INVALID_OPCODE, 1302 INVALID_OPCODE, 1303 INVALID_OPCODE, 1304 INVALID_OPCODE, 1305 INVALID_OPCODE, 1306 INVALID_OPCODE, 1307 INVALID_OPCODE, 1308 INVALID_OPCODE, 1309 INVALID_OPCODE, 1310 INVALID_OPCODE, 1311 INVALID_OPCODE, 1312 INVALID_OPCODE, 1313 }; 1314 1278 1315 /** These tables are mostly sparse, so use another level of indirection to save space. */ 1279 1316 PCDISOPCODE const g_apThreeByteMapX86_0F38[16] = … … 1310 1347 NULL, 1311 1348 /* f */ 1312 NULL,1349 &g_aThreeByteMapX86_0F38_F[0], 1313 1350 }; 1314 1351 … … 1381 1418 }; 1382 1419 1420 const DISOPCODE g_aThreeByteMapX86_660F38_F[16] = 1421 { 1422 /* 8 */ 1423 OP("movbe %Gw,%Mw", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEGM, OP_PARM_Gw, OP_PARM_Mw, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1424 OP("movbe %Mw,%Gw", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVBEMG, OP_PARM_Mw, OP_PARM_Gw, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1425 INVALID_OPCODE, 1426 INVALID_OPCODE, 1427 INVALID_OPCODE, 1428 INVALID_OPCODE, 1429 OP("adcx %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADCX, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1430 INVALID_OPCODE, 1431 INVALID_OPCODE, 1432 INVALID_OPCODE, 1433 INVALID_OPCODE, 1434 INVALID_OPCODE, 1435 INVALID_OPCODE, 1436 INVALID_OPCODE, 1437 INVALID_OPCODE, 1438 INVALID_OPCODE, 1439 }; 1440 1383 1441 /** Three byte opcode map with prefix 0x66 (0xF 0x38) */ 1384 1442 PCDISOPCODE const g_apThreeByteMapX86_660F38[16] = … … 1415 1473 NULL, 1416 1474 /* f */ 1417 NULL, 1475 &g_aThreeByteMapX86_660F38_F[0], 1476 }; 1477 1478 const DISOPCODE g_aThreeByteMapX86_F20F38_F[16] = 1479 { 1480 /* According to Intel opcodes map in Intel® 64 and IA-32 Architectures Software Developer’s Manual dated September 2014 1481 it should be %Gd (always dword regardless of operand-size attribute), but from the description of the command 1482 it is clear that REX.W prefix can change this size to 64 bit, therefore it is set to %Gy. Seems to be a mistake. */ 1483 OP("crc32 %Gy,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEB, OP_PARM_Gy, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1484 OP("crc32 %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEY, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1485 INVALID_OPCODE, 1486 INVALID_OPCODE, 1487 INVALID_OPCODE, 1488 INVALID_OPCODE, 1489 INVALID_OPCODE, 1490 INVALID_OPCODE, 1491 INVALID_OPCODE, 1492 INVALID_OPCODE, 1493 INVALID_OPCODE, 1494 INVALID_OPCODE, 1495 INVALID_OPCODE, 1496 INVALID_OPCODE, 1497 INVALID_OPCODE, 1498 INVALID_OPCODE, 1499 }; 1500 1501 const DISOPCODE g_aThreeByteMapX86_66F20F38_F[16] = 1502 { 1503 /* According to Intel opcodes map in Intel® 64 and IA-32 Architectures Software Developer’s Manual dated September 2014 1504 it should be %Gd (always dword regardless of operand-size attribute), but from the description of the command 1505 it is clear that REX.W prefix can change this size to 64 bit, therefore it is set to %Gy. Seems to be a mistake. */ 1506 OP("crc32 %Gy,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEB, OP_PARM_Gy, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1507 OP("crc32 %Gy,%Ew", IDX_ParseModRM, IDX_UseModRM, 0, OP_CRC32GDEY, OP_PARM_Gy, OP_PARM_Ew, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1508 INVALID_OPCODE, 1509 INVALID_OPCODE, 1510 INVALID_OPCODE, 1511 INVALID_OPCODE, 1512 INVALID_OPCODE, 1513 INVALID_OPCODE, 1514 INVALID_OPCODE, 1515 INVALID_OPCODE, 1516 INVALID_OPCODE, 1517 INVALID_OPCODE, 1518 INVALID_OPCODE, 1519 INVALID_OPCODE, 1520 INVALID_OPCODE, 1521 INVALID_OPCODE, 1418 1522 }; 1419 1523 … … 1453 1557 NULL, 1454 1558 /* f */ 1455 NULL, 1559 &g_aThreeByteMapX86_F20F38_F[0], 1560 }; 1561 1562 const DISOPCODE g_aThreeByteMapX86_F30F38_F[16] = 1563 { 1564 INVALID_OPCODE, 1565 INVALID_OPCODE, 1566 INVALID_OPCODE, 1567 INVALID_OPCODE, 1568 INVALID_OPCODE, 1569 INVALID_OPCODE, 1570 OP("adox %Gy,%Ey", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADOX, OP_PARM_Gy, OP_PARM_Ey, OP_PARM_NONE, DISOPTYPE_HARMLESS), 1571 INVALID_OPCODE, 1572 INVALID_OPCODE, 1573 INVALID_OPCODE, 1574 INVALID_OPCODE, 1575 INVALID_OPCODE, 1576 INVALID_OPCODE, 1577 INVALID_OPCODE, 1578 INVALID_OPCODE, 1579 INVALID_OPCODE, 1580 }; 1581 1582 /** Three byte opcode map with prefix 0xF3 (0xF 0x38) */ 1583 PCDISOPCODE const g_apThreeByteMapX86_F30F38[16] = 1584 { 1585 /* 0 */ 1586 NULL, 1587 /* 1 */ 1588 NULL, 1589 /* 2 */ 1590 NULL, 1591 /* 3 */ 1592 NULL, 1593 /* 4 */ 1594 NULL, 1595 /* 5 */ 1596 NULL, 1597 /* 6 */ 1598 NULL, 1599 /* 7 */ 1600 NULL, 1601 /* 8 */ 1602 NULL, 1603 /* 9 */ 1604 NULL, 1605 /* a */ 1606 NULL, 1607 /* b */ 1608 NULL, 1609 /* c */ 1610 NULL, 1611 /* d */ 1612 NULL, 1613 /* e */ 1614 NULL, 1615 /* f */ 1616 &g_aThreeByteMapX86_F30F38_F[0], 1456 1617 }; 1457 1618 -
TabularUnified trunk/src/VBox/Disassembler/testcase/tstDisasm-1A.asm ¶
r49346 r53007 51 51 DB 0xF0, 0x0F, 0x20, 0xC0 52 52 smsw word [edx+16] 53 ; invept eax, qword [ecx]53 ; invept eax, dqword [ecx] 54 54 DB 0x66, 0x0F, 0x38, 0x80, 0x1 55 ; invept eax, qword [ecx]55 ; invept eax, dqword [ecx] 56 56 DB 0x66, 0x0F, 0x38, 0x81, 0x1 57 57 mov eax, dword [ecx] … … 148 148 paddd mm1, mm3 149 149 paddd xmm1, xmm3 150 151 %if __YASM_VERSION_ID__ >= 001030000h ; Old yasm doesn't support the instructions below 152 adcx eax, ebx 153 adcx eax, [edi] 154 155 adox eax, ebx 156 adox eax, [edi] 157 adox eax, [edi + 1000h] 158 159 tzcnt ax, bx 160 tzcnt eax, ebx 161 tzcnt ax, [edi] 162 tzcnt eax, [edi] 163 tzcnt eax, [edi + 1000h] 164 %endif 165 166 movbe eax, [edi] 167 movbe ebx, [edi + 1000h] 168 movbe ax, [edi] 169 movbe [edi], eax 170 171 crc32 eax, bl 172 ;crc32 eax, bx 173 crc32 eax, ebx 174 crc32 eax, byte [edi] 175 ;crc32 eax, word [edi] 176 crc32 eax, dword [edi] 177 178 popcnt ax, bx 179 popcnt eax, ebx 180 popcnt ax, [edi] 181 popcnt eax, [edi] 182 popcnt eax, [edi + 1000h] 183 184 lzcnt ax, bx 185 lzcnt eax, ebx 186 lzcnt ax, [edi] 187 lzcnt eax, [edi] 188 lzcnt eax, [edi + 1000h] 189 190 vmread eax, ebx 191 vmwrite eax, ebx 192 150 193 ENDPROC TestProc32 151 194 … … 164 207 mov rbx, [0xfffe0080] 165 208 divsd xmm1, xmm0 166 ; invept rdi, qword [rsi]209 ; invept rdi, dqword [rsi] 167 210 DB 0x66, 0x0F, 0x38, 0x80, 0x3E 168 ; invept rcx, qword [rdx]211 ; invept rcx, dqword [rdx] 169 212 DB 0x66, 0x0F, 0x38, 0x80, 0xA 170 ;invvpid rdi, qword [rsi]213 ;invvpid rdi, dqword [rsi] 171 214 DB 0x66, 0x0F, 0x38, 0x81, 0x3E 172 ; invvpid rcx, qword [rdx]215 ; invvpid rcx, dqword [rdx] 173 216 DB 0x66, 0x0F, 0x38, 0x81, 0xA 174 217 mov rdi, [rsi] … … 234 277 movsd xmm6, xmm1 235 278 279 movbe eax, [rdi] 280 movbe ax, [rdi] 281 movbe rax, [rdi] 282 283 crc32 eax, bl 284 ;crc32 eax, bx 285 crc32 eax, ebx 286 crc32 eax, byte [edi] 287 ;crc32 eax, word [edi] 288 crc32 eax, dword [edi] 289 290 crc32 rax, bl 291 crc32 rax, byte [rdi] 292 crc32 rax, qword [rdi] 293 294 %if __YASM_VERSION_ID__ >= 001030000h ; Old yasm doesn't support the instructions below 295 296 adcx eax, ebx 297 adcx rax, rbx 298 adcx r8, r11 299 adcx r8d, edx 300 301 adox eax, ebx 302 adox eax, [edi] 303 adox eax, [edi + 1000h] 304 305 adox rax, rbx 306 adox rax, [rdi] 307 adox rax, [rdi + 1000h] 308 adox rax, [edi + 1000h] 309 310 tzcnt ax, bx 311 tzcnt eax, ebx 312 tzcnt rax, rbx 313 tzcnt ax, [edi] 314 tzcnt eax, [edi] 315 tzcnt eax, [edi + 1000h] 316 %endif 317 318 popcnt ax, bx 319 popcnt eax, ebx 320 popcnt rax, rbx 321 popcnt ax, [edi] 322 popcnt eax, [edi] 323 popcnt eax, [edi + 1000h] 324 popcnt rax, [rdi + 1000h] 325 326 lzcnt ax, bx 327 lzcnt eax, ebx 328 lzcnt rax, rbx 329 lzcnt ax, [edi] 330 lzcnt eax, [edi] 331 lzcnt eax, [edi + 1000h] 332 lzcnt eax, [rdi] 333 lzcnt ax, [rdi] 334 lzcnt rax, [rdi] 335 lzcnt r8d, [rdi] 336 337 vmread rax, rbx 338 vmwrite rax, rbx 339 236 340 ret 237 341 ENDPROC TestProc64
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