Changeset 53085 in vbox for trunk/src

Timestamp:

Oct 17, 2014 12:23:54 PM (10 years ago)

Author:

vboxsync

Message:

HostDrivers/Support: Fixes to TSC frequency measurement. Also adds available TSC delta while taking the measurement if possible.

File:

• trunk/src/VBox/HostDrivers/Support/SUPDrv.c (modified) (10 diffs)

trunk/src/VBox/HostDrivers/Support/SUPDrv.c

@@ -162 +162 @@
 static bool                 supdrvIsInvariantTsc(void);
 static void                 supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys,
-                                          uint64_t u64NanoTS, unsigned uUpdateHz, unsigned cCpus);
+                                          uint64_t u64NanoTS, unsigned uUpdateHz, unsigned uUpdateIntervalNS, unsigned cCpus);
 static DECLCALLBACK(void)   supdrvGipInitOnCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2);
 static void                 supdrvGipTerm(PSUPGLOBALINFOPAGE pGip);
@@ -5919 +5919 @@
     uint32_t            u32SystemResolution;
     uint32_t            u32Interval;
+    uint32_t            u32MinInterval;
+    uint32_t            uMod;
     unsigned            cCpus;
     int                 rc;
@@ -5954 +5956 @@
     /*
      * Find a reasonable update interval and initialize the structure.
-     */
-    u32Interval = u32SystemResolution = RTTimerGetSystemGranularity();
-    while (u32Interval < 10000000 /* 10 ms */)
-        u32Interval += u32SystemResolution;
-
-    supdrvGipInit(pDevExt, pGip, HCPhysGip, RTTimeSystemNanoTS(), 1000000000 / u32Interval /*=Hz*/, cCpus);
+     *
+     * If we have an invariant TSC, use a larger update interval as then
+     * we get better accuracy along with lower host load.
+     */
+    u32MinInterval      = supdrvIsInvariantTsc() ? RT_NS_100MS : RT_NS_10MS;
+    u32SystemResolution = RTTimerGetSystemGranularity();
+    u32Interval         = u32MinInterval;
+    uMod                = u32MinInterval % u32SystemResolution;
+    if (uMod)
+        u32Interval += u32SystemResolution - uMod;
+
+    supdrvGipInit(pDevExt, pGip, HCPhysGip, RTTimeSystemNanoTS(), RT_NS_1SEC / u32Interval /*=Hz*/, u32Interval, cCpus);
 
 #ifdef SUPDRV_USE_TSC_DELTA_THREAD
@@ -6104 +6112 @@
 {
     RTCCUINTREG     fOldFlags = ASMIntDisableFlags(); /* No interruptions please (real problem on S10). */
-    PSUPDRVDEVEXT   pDevExt   = (PSUPDRVDEVEXT)pvUser;
     uint64_t        u64TSC    = ASMReadTSC();
     uint64_t        NanoTS    = RTTimeSystemNanoTS();
+    PSUPDRVDEVEXT   pDevExt   = (PSUPDRVDEVEXT)pvUser;
+
+    if (supdrvIsInvariantTsc())
+    {
+        PSUPGIPCPU         pGipCpu;
+        PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
+        unsigned           iCpu = pGip->aiCpuFromApicId[ASMGetApicId()];
+        AssertReturnVoid(iCpu < pGip->cCpus);
+        pGipCpu = &pGip->aCPUs[iCpu];
+        AssertReturnVoid(pGipCpu->idCpu == RTMpCpuId());
+
+        /*
+         * The calculations in supdrvGipUpdate() is very timing sensitive and doesn't handle
+         * missed timer ticks. So for now it is better to use a delta of 0 and have the TSC rate
+         * affected a bit until we get proper TSC deltas than implementing options like
+         * rescheduling the tick to be delivered on the right CPU or missing the tick entirely.
+         */
+        if (pGipCpu->i64TSCDelta != INT64_MAX)
+            u64TSC += pGipCpu->i64TSCDelta;
+    }
 
     supdrvGipUpdate(pDevExt, NanoTS, u64TSC, NIL_RTCPUID, iTick);
@@ -6898 +6925 @@
 static SUPGIPMODE supdrvGipDeterminTscMode(PSUPDRVDEVEXT pDevExt)
 {
+    if (supdrvIsInvariantTsc())
+        return SUPGIPMODE_SYNC_TSC;     /** @todo Switch to SUPGIPMODE_INVARIANT_TSC later. */
+
     /*
      * On SMP we're faced with two problems:
@@ -6988 +7018 @@
  * Initializes the GIP data.
  *
- * @param   pDevExt     Pointer to the device instance data.
- * @param   pGip        Pointer to the read-write kernel mapping of the GIP.
- * @param   HCPhys      The physical address of the GIP.
- * @param   u64NanoTS   The current nanosecond timestamp.
- * @param   uUpdateHz   The update frequency.
- * @param   cCpus       The CPU count.
+ * @param   pDevExt             Pointer to the device instance data.
+ * @param   pGip                Pointer to the read-write kernel mapping of the GIP.
+ * @param   HCPhys              The physical address of the GIP.
+ * @param   u64NanoTS           The current nanosecond timestamp.
+ * @param   uUpdateHz           The update frequency.
+ * @param   uUpdateIntervalNS   The update interval in nanoseconds.
+ * @param   cCpus               The CPU count.
  */
 static void supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys,
-                          uint64_t u64NanoTS, unsigned uUpdateHz, unsigned cCpus)
+                          uint64_t u64NanoTS, unsigned uUpdateHz, unsigned uUpdateIntervalNS, unsigned cCpus)
 {
     size_t const    cbGip = RT_ALIGN_Z(RT_OFFSETOF(SUPGLOBALINFOPAGE, aCPUs[cCpus]), PAGE_SIZE);
@@ -7016 +7047 @@
     pGip->cPages                = (uint16_t)(cbGip / PAGE_SIZE);
     pGip->u32UpdateHz           = uUpdateHz;
-    pGip->u32UpdateIntervalNS   = 1000000000 / uUpdateHz;
+    pGip->u32UpdateIntervalNS   = uUpdateIntervalNS;
     pGip->u64NanoTSLastUpdateHz = u64NanoTS;
     RTCpuSetEmpty(&pGip->OnlineCpuSet);
@@ -7160 +7191 @@
 
     /*
+     * For invariant TSC support, we take only 1 interval as there is a problem on
+     * Windows where we have an occasional (but reccurring) sour value that messes up
+     * the history. Also, since the update interval is pretty long with the invariant
+     * TSC case this works accurately enough.
+     */
+    if (supdrvIsInvariantTsc())
+    {
+        u32UpdateIntervalTSC = (uint32_t)u64TSCDelta;
+        u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 6;
+    }
+    /*
      * UpdateIntervalTSC = average of last 8,2,1 intervals depending on update HZ.
      */
-    if (pGip->u32UpdateHz >= 1000)
+    else if (pGip->u32UpdateHz >= 1000)
     {
         uint32_t u32;
@@ -7202 +7244 @@
      * CpuHz.
      */
-    u64CpuHz = ASMMult2xU32RetU64(u32UpdateIntervalTSC, pGip->u32UpdateHz);
+    u64CpuHz = ASMMult2xU32RetU64(u32UpdateIntervalTSC, RT_NS_1SEC_64);
+    u64CpuHz /= pGip->u32UpdateIntervalNS;
     ASMAtomicWriteU64(&pGipCpu->u64CpuHz, u64CpuHz);
 }
@@ -7258 +7301 @@
 #ifdef RT_ARCH_AMD64 /** @todo fix 64-bit div here to work on x86 linux. */
             uint64_t u64Delta = u64NanoTS - pGip->u64NanoTSLastUpdateHz;
-            uint32_t u32UpdateHz = (uint32_t)((UINT64_C(1000000000) * GIP_UPDATEHZ_RECALC_FREQ) / u64Delta);
+            uint32_t u32UpdateHz = (uint32_t)((RT_NS_1SEC_64 * GIP_UPDATEHZ_RECALC_FREQ) / u64Delta);
             if (u32UpdateHz <= 2000 && u32UpdateHz >= 30)
             {
                 ASMAtomicWriteU32(&pGip->u32UpdateHz, u32UpdateHz);
-                ASMAtomicWriteU32(&pGip->u32UpdateIntervalNS, 1000000000 / u32UpdateHz);
+                ASMAtomicWriteU32(&pGip->u32UpdateIntervalNS, RT_NS_1SEC / u32UpdateHz);
             }
 #endif