Changeset 53187 in vbox for trunk/include/iprt

Timestamp:

Nov 3, 2014 9:27:48 PM (10 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

96733

Message:

x86.h: Found some documentation of DR7 bits 12, 14 and 15. Tentatively added defines for them.

File:

• trunk/include/iprt/x86.h (modified) (2 diffs)

trunk/include/iprt/x86.h

@@ -862 +862 @@
 #define X86_DR7_GE_ALL                      UINT64_C(0x00000000000000aa)
 
+/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium.  When set, the in
+ * Circut Emulator (ICE) will break emulation on breakpoints and stuff.
+ * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
+ * instruction is executed.
+ * @see http://www.rcollins.org/secrets/DR7.html  */
+#define X86_DR7_ICE_IR                      RT_BIT(12)
 /** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
  * any DR register is accessed. */
 #define X86_DR7_GD                          RT_BIT(13)
+/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
+ *  Pentium. */
+#define X86_DR7_ICE_TR1                     RT_BIT(14)
+/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
+#define X86_DR7_ICE_TR2                     RT_BIT(15)
 /** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
 #define X86_DR7_RW0_MASK                    (3 << 16)
@@ -884 +895 @@
 /** Bits which reads as 1s. */
 #define X86_DR7_RA1_MASK                    (RT_BIT(10))
-/** Bits which reads as zeros. */
+/** Bits which reads as zeros.  These are related to ICE (bits 12, 14, 15). */
 #define X86_DR7_RAZ_MASK                    UINT64_C(0x0000d800)
 /** Bits which must be 0s when writing to DR7. */