Changeset 53466 in vbox
- Timestamp:
- Dec 5, 2014 4:07:33 PM (10 years ago)
- svn:sync-xref-src-repo-rev:
- 97194
- Location:
- trunk
- Files:
-
- 17 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/err.h
r53330 r53466 625 625 /** Invalid CPUMCPU offset in MSR range. */ 626 626 #define VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET (-1757) 627 /** Return to ring-3 to read the MSR there. */ 628 #define VINF_CPUM_R3_MSR_READ (1758) 629 /** Return to ring-3 to write the MSR there. */ 630 #define VINF_CPUM_R3_MSR_WRITE (1759) 627 631 /** @} */ 628 632 -
trunk/include/VBox/vmm/cpum.h
r51797 r53466 923 923 VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM); 924 924 VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu); 925 VMMDECL( int)CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);926 VMMDECL( int)CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);925 VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue); 926 VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue); 927 927 VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM); 928 928 VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM); -
trunk/include/VBox/vmm/gim.h
r52760 r53466 178 178 VMM_INT_DECL(bool) GIMAreHypercallsEnabled(PVMCPU pVCpu); 179 179 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 180 VMM_INT_DECL( int)GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);181 VMM_INT_DECL( int)GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);180 VMM_INT_DECL(VBOXSTRICTRC) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 181 VMM_INT_DECL(VBOXSTRICTRC) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue); 182 182 183 183 /** @} */ -
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r52770 r53466 58 58 * @returns VBox status code. 59 59 * @retval VINF_SUCCESS on success. 60 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the 61 * current context (raw-mode or ring-0). 60 62 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR). 61 63 * … … 65 67 * @param puValue Where to return the value. 66 68 */ 67 typedef DECLCALLBACK( int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);69 typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 68 70 /** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */ 69 71 typedef FNCPUMRDMSR *PFNCPUMRDMSR; … … 74 76 * 75 77 * @retval VINF_SUCCESS on success. 78 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the 79 * current context (raw-mode or ring-0). 76 80 * @retval VERR_CPUM_RAISE_GP_0 on failure. 77 81 * … … 82 86 * @param uRawValue The raw value with the ignored bits not masked. 83 87 */ 84 typedef DECLCALLBACK( int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);88 typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue); 85 89 /** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */ 86 90 typedef FNCPUMWRMSR *PFNCPUMWRMSR; … … 96 100 97 101 /** @callback_method_impl{FNCPUMRDMSR} */ 98 static DECLCALLBACK( int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)102 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 99 103 { 100 104 *puValue = pRange->uValue; … … 104 108 105 109 /** @callback_method_impl{FNCPUMWRMSR} */ 106 static DECLCALLBACK( int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)110 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 107 111 { 108 112 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue)); … … 112 116 113 117 /** @callback_method_impl{FNCPUMRDMSR} */ 114 static DECLCALLBACK( int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)118 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 115 119 { 116 120 return VERR_CPUM_RAISE_GP_0; … … 119 123 120 124 /** @callback_method_impl{FNCPUMWRMSR} */ 121 static DECLCALLBACK( int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)125 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 122 126 { 123 127 Assert(pRange->fWrGpMask == UINT64_MAX); … … 135 139 136 140 /** @callback_method_impl{FNCPUMRDMSR} */ 137 static DECLCALLBACK( int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)141 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 138 142 { 139 143 *puValue = 0; /** @todo implement machine check injection. */ … … 143 147 144 148 /** @callback_method_impl{FNCPUMWRMSR} */ 145 static DECLCALLBACK( int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)149 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 146 150 { 147 151 /** @todo implement machine check injection. */ … … 151 155 152 156 /** @callback_method_impl{FNCPUMRDMSR} */ 153 static DECLCALLBACK( int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)157 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 154 158 { 155 159 *puValue = 0; /** @todo implement machine check injection. */ … … 159 163 160 164 /** @callback_method_impl{FNCPUMWRMSR} */ 161 static DECLCALLBACK( int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)165 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 162 166 { 163 167 /** @todo implement machine check injection. */ … … 167 171 168 172 /** @callback_method_impl{FNCPUMRDMSR} */ 169 static DECLCALLBACK( int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)173 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 170 174 { 171 175 *puValue = TMCpuTickGet(pVCpu); … … 175 179 176 180 /** @callback_method_impl{FNCPUMWRMSR} */ 177 static DECLCALLBACK( int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)181 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 178 182 { 179 183 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue); … … 183 187 184 188 /** @callback_method_impl{FNCPUMRDMSR} */ 185 static DECLCALLBACK( int) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)189 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 186 190 { 187 191 uint64_t uValue = pRange->uValue; … … 198 202 199 203 /** @callback_method_impl{FNCPUMRDMSR} */ 200 static DECLCALLBACK( int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)204 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 201 205 { 202 206 PVM pVM = pVCpu->CTX_SUFF(pVM); … … 218 222 219 223 /** @callback_method_impl{FNCPUMWRMSR} */ 220 static DECLCALLBACK( int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)224 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 221 225 { 222 226 int rc = PDMApicSetBase(pVCpu, uValue); … … 228 232 229 233 /** @callback_method_impl{FNCPUMRDMSR} */ 230 static DECLCALLBACK( int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)234 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 231 235 { 232 236 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */ … … 236 240 237 241 /** @callback_method_impl{FNCPUMWRMSR} */ 238 static DECLCALLBACK( int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)242 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 239 243 { 240 244 return VERR_CPUM_RAISE_GP_0; … … 243 247 244 248 /** @callback_method_impl{FNCPUMRDMSR} */ 245 static DECLCALLBACK( int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)249 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 246 250 { 247 251 /** @todo fake microcode update. */ … … 252 256 253 257 /** @callback_method_impl{FNCPUMWRMSR} */ 254 static DECLCALLBACK( int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)258 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 255 259 { 256 260 /* Normally, zero is written to Ia32BiosSignId before reading it in order … … 263 267 264 268 /** @callback_method_impl{FNCPUMWRMSR} */ 265 static DECLCALLBACK( int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)269 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 266 270 { 267 271 /** @todo Fake bios update trigger better. The value is the address to an … … 272 276 273 277 /** @callback_method_impl{FNCPUMRDMSR} */ 274 static DECLCALLBACK( int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)278 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 275 279 { 276 280 /** @todo SMM. */ … … 281 285 282 286 /** @callback_method_impl{FNCPUMWRMSR} */ 283 static DECLCALLBACK( int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)287 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 284 288 { 285 289 /** @todo SMM. */ … … 289 293 290 294 /** @callback_method_impl{FNCPUMRDMSR} */ 291 static DECLCALLBACK( int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)295 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 292 296 { 293 297 /** @todo check CPUID leaf 0ah. */ … … 298 302 299 303 /** @callback_method_impl{FNCPUMWRMSR} */ 300 static DECLCALLBACK( int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)304 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 301 305 { 302 306 /** @todo check CPUID leaf 0ah. */ … … 306 310 307 311 /** @callback_method_impl{FNCPUMRDMSR} */ 308 static DECLCALLBACK( int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)312 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 309 313 { 310 314 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */ … … 315 319 316 320 /** @callback_method_impl{FNCPUMWRMSR} */ 317 static DECLCALLBACK( int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)321 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 318 322 { 319 323 /** @todo should remember writes, though it's supposedly something only a BIOS … … 323 327 324 328 /** @callback_method_impl{FNCPUMRDMSR} */ 325 static DECLCALLBACK( int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)329 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 326 330 { 327 331 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC … … 333 337 334 338 /** @callback_method_impl{FNCPUMWRMSR} */ 335 static DECLCALLBACK( int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)339 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 336 340 { 337 341 /** @todo Write MPERF: Calc adjustment. */ … … 341 345 342 346 /** @callback_method_impl{FNCPUMRDMSR} */ 343 static DECLCALLBACK( int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)347 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 344 348 { 345 349 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC … … 351 355 352 356 /** @callback_method_impl{FNCPUMWRMSR} */ 353 static DECLCALLBACK( int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)357 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 354 358 { 355 359 /** @todo Write APERF: Calc adjustment. */ … … 359 363 360 364 /** @callback_method_impl{FNCPUMWRMSR} */ 361 static DECLCALLBACK( int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)365 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 362 366 { 363 367 /* This is currently a bit weird. :-) */ … … 375 379 376 380 /** @callback_method_impl{FNCPUMRDMSR} */ 377 static DECLCALLBACK( int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)381 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 378 382 { 379 383 /** @todo Implement variable MTRR storage. */ … … 385 389 386 390 /** @callback_method_impl{FNCPUMWRMSR} */ 387 static DECLCALLBACK( int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)391 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 388 392 { 389 393 /* … … 415 419 416 420 /** @callback_method_impl{FNCPUMRDMSR} */ 417 static DECLCALLBACK( int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)421 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 418 422 { 419 423 /** @todo Implement variable MTRR storage. */ … … 425 429 426 430 /** @callback_method_impl{FNCPUMWRMSR} */ 427 static DECLCALLBACK( int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)431 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 428 432 { 429 433 /* … … 449 453 450 454 /** @callback_method_impl{FNCPUMRDMSR} */ 451 static DECLCALLBACK( int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)455 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 452 456 { 453 457 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr); … … 458 462 459 463 /** @callback_method_impl{FNCPUMWRMSR} */ 460 static DECLCALLBACK( int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)464 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 461 465 { 462 466 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr); … … 477 481 478 482 /** @callback_method_impl{FNCPUMRDMSR} */ 479 static DECLCALLBACK( int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)483 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 480 484 { 481 485 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType; … … 485 489 486 490 /** @callback_method_impl{FNCPUMWRMSR} */ 487 static DECLCALLBACK( int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)491 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 488 492 { 489 493 if ((uValue & 0xff) >= 7) … … 499 503 500 504 /** @callback_method_impl{FNCPUMRDMSR} */ 501 static DECLCALLBACK( int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)505 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 502 506 { 503 507 *puValue = pVCpu->cpum.s.Guest.msrPAT; … … 507 511 508 512 /** @callback_method_impl{FNCPUMWRMSR} */ 509 static DECLCALLBACK( int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)513 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 510 514 { 511 515 pVCpu->cpum.s.Guest.msrPAT = uValue; … … 515 519 516 520 /** @callback_method_impl{FNCPUMRDMSR} */ 517 static DECLCALLBACK( int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)521 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 518 522 { 519 523 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs; … … 523 527 524 528 /** @callback_method_impl{FNCPUMWRMSR} */ 525 static DECLCALLBACK( int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)529 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 526 530 { 527 531 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and … … 533 537 534 538 /** @callback_method_impl{FNCPUMRDMSR} */ 535 static DECLCALLBACK( int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)539 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 536 540 { 537 541 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp; … … 541 545 542 546 /** @callback_method_impl{FNCPUMWRMSR} */ 543 static DECLCALLBACK( int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)547 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 544 548 { 545 549 if (X86_IS_CANONICAL(uValue)) … … 554 558 555 559 /** @callback_method_impl{FNCPUMRDMSR} */ 556 static DECLCALLBACK( int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)560 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 557 561 { 558 562 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip; … … 562 566 563 567 /** @callback_method_impl{FNCPUMWRMSR} */ 564 static DECLCALLBACK( int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)568 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 565 569 { 566 570 if (X86_IS_CANONICAL(uValue)) … … 579 583 580 584 /** @callback_method_impl{FNCPUMRDMSR} */ 581 static DECLCALLBACK( int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)585 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 582 586 { 583 587 #if 0 /** @todo implement machine checks. */ … … 591 595 592 596 /** @callback_method_impl{FNCPUMRDMSR} */ 593 static DECLCALLBACK( int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)597 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 594 598 { 595 599 /** @todo implement machine checks. */ … … 600 604 601 605 /** @callback_method_impl{FNCPUMWRMSR} */ 602 static DECLCALLBACK( int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)606 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 603 607 { 604 608 /** @todo implement machine checks. */ … … 608 612 609 613 /** @callback_method_impl{FNCPUMRDMSR} */ 610 static DECLCALLBACK( int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)614 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 611 615 { 612 616 /** @todo implement machine checks. */ … … 617 621 618 622 /** @callback_method_impl{FNCPUMWRMSR} */ 619 static DECLCALLBACK( int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)623 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 620 624 { 621 625 /** @todo implement machine checks. */ … … 625 629 626 630 /** @callback_method_impl{FNCPUMRDMSR} */ 627 static DECLCALLBACK( int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)631 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 628 632 { 629 633 /** @todo implement IA32_DEBUGCTL. */ … … 634 638 635 639 /** @callback_method_impl{FNCPUMWRMSR} */ 636 static DECLCALLBACK( int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)640 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 637 641 { 638 642 /** @todo implement IA32_DEBUGCTL. */ … … 642 646 643 647 /** @callback_method_impl{FNCPUMRDMSR} */ 644 static DECLCALLBACK( int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)648 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 645 649 { 646 650 /** @todo implement intel SMM. */ … … 651 655 652 656 /** @callback_method_impl{FNCPUMWRMSR} */ 653 static DECLCALLBACK( int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)657 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 654 658 { 655 659 /** @todo implement intel SMM. */ … … 659 663 660 664 /** @callback_method_impl{FNCPUMRDMSR} */ 661 static DECLCALLBACK( int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)665 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 662 666 { 663 667 /** @todo implement intel SMM. */ … … 668 672 669 673 /** @callback_method_impl{FNCPUMWRMSR} */ 670 static DECLCALLBACK( int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)674 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 671 675 { 672 676 /** @todo implement intel SMM. */ … … 676 680 677 681 /** @callback_method_impl{FNCPUMRDMSR} */ 678 static DECLCALLBACK( int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)682 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 679 683 { 680 684 /** @todo implement intel direct cache access (DCA)?? */ … … 685 689 686 690 /** @callback_method_impl{FNCPUMWRMSR} */ 687 static DECLCALLBACK( int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)691 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 688 692 { 689 693 /** @todo implement intel direct cache access (DCA)?? */ … … 693 697 694 698 /** @callback_method_impl{FNCPUMRDMSR} */ 695 static DECLCALLBACK( int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)699 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 696 700 { 697 701 /** @todo implement intel direct cache access (DCA)?? */ … … 702 706 703 707 /** @callback_method_impl{FNCPUMRDMSR} */ 704 static DECLCALLBACK( int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)708 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 705 709 { 706 710 /** @todo implement intel direct cache access (DCA)?? */ … … 711 715 712 716 /** @callback_method_impl{FNCPUMWRMSR} */ 713 static DECLCALLBACK( int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)717 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 714 718 { 715 719 /** @todo implement intel direct cache access (DCA)?? */ … … 719 723 720 724 /** @callback_method_impl{FNCPUMRDMSR} */ 721 static DECLCALLBACK( int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)725 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 722 726 { 723 727 /** @todo implement IA32_PERFEVTSEL0+. */ … … 728 732 729 733 /** @callback_method_impl{FNCPUMWRMSR} */ 730 static DECLCALLBACK( int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)734 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 731 735 { 732 736 /** @todo implement IA32_PERFEVTSEL0+. */ … … 736 740 737 741 /** @callback_method_impl{FNCPUMRDMSR} */ 738 static DECLCALLBACK( int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)742 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 739 743 { 740 744 uint64_t uValue = pRange->uValue; … … 757 761 758 762 /** @callback_method_impl{FNCPUMWRMSR} */ 759 static DECLCALLBACK( int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)763 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 760 764 { 761 765 /* Pentium4 allows writing, but all bits are ignored. */ … … 765 769 766 770 /** @callback_method_impl{FNCPUMRDMSR} */ 767 static DECLCALLBACK( int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)771 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 768 772 { 769 773 /** @todo implement IA32_PERFCTL. */ … … 774 778 775 779 /** @callback_method_impl{FNCPUMWRMSR} */ 776 static DECLCALLBACK( int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)780 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 777 781 { 778 782 /** @todo implement IA32_PERFCTL. */ … … 782 786 783 787 /** @callback_method_impl{FNCPUMRDMSR} */ 784 static DECLCALLBACK( int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)788 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 785 789 { 786 790 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */ … … 791 795 792 796 /** @callback_method_impl{FNCPUMWRMSR} */ 793 static DECLCALLBACK( int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)797 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 794 798 { 795 799 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */ … … 799 803 800 804 /** @callback_method_impl{FNCPUMRDMSR} */ 801 static DECLCALLBACK( int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)805 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 802 806 { 803 807 /** @todo implement performance counters. */ … … 808 812 809 813 /** @callback_method_impl{FNCPUMWRMSR} */ 810 static DECLCALLBACK( int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)814 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 811 815 { 812 816 /** @todo implement performance counters. */ … … 816 820 817 821 /** @callback_method_impl{FNCPUMRDMSR} */ 818 static DECLCALLBACK( int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)822 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 819 823 { 820 824 /** @todo implement performance counters. */ … … 825 829 826 830 /** @callback_method_impl{FNCPUMWRMSR} */ 827 static DECLCALLBACK( int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)831 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 828 832 { 829 833 /** @todo implement performance counters. */ … … 833 837 834 838 /** @callback_method_impl{FNCPUMRDMSR} */ 835 static DECLCALLBACK( int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)839 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 836 840 { 837 841 /** @todo implement performance counters. */ … … 842 846 843 847 /** @callback_method_impl{FNCPUMWRMSR} */ 844 static DECLCALLBACK( int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)848 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 845 849 { 846 850 /** @todo implement performance counters. */ … … 850 854 851 855 /** @callback_method_impl{FNCPUMRDMSR} */ 852 static DECLCALLBACK( int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)856 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 853 857 { 854 858 /** @todo implement performance counters. */ … … 859 863 860 864 /** @callback_method_impl{FNCPUMWRMSR} */ 861 static DECLCALLBACK( int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)865 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 862 866 { 863 867 /** @todo implement performance counters. */ … … 867 871 868 872 /** @callback_method_impl{FNCPUMRDMSR} */ 869 static DECLCALLBACK( int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)873 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 870 874 { 871 875 /** @todo implement performance counters. */ … … 876 880 877 881 /** @callback_method_impl{FNCPUMWRMSR} */ 878 static DECLCALLBACK( int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)882 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 879 883 { 880 884 /** @todo implement performance counters. */ … … 884 888 885 889 /** @callback_method_impl{FNCPUMRDMSR} */ 886 static DECLCALLBACK( int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)890 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 887 891 { 888 892 /** @todo implement performance counters. */ … … 893 897 894 898 /** @callback_method_impl{FNCPUMWRMSR} */ 895 static DECLCALLBACK( int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)899 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 896 900 { 897 901 /** @todo implement performance counters. */ … … 901 905 902 906 /** @callback_method_impl{FNCPUMRDMSR} */ 903 static DECLCALLBACK( int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)907 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 904 908 { 905 909 /** @todo implement IA32_CLOCK_MODULATION. */ … … 910 914 911 915 /** @callback_method_impl{FNCPUMWRMSR} */ 912 static DECLCALLBACK( int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)916 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 913 917 { 914 918 /** @todo implement IA32_CLOCK_MODULATION. */ … … 918 922 919 923 /** @callback_method_impl{FNCPUMRDMSR} */ 920 static DECLCALLBACK( int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)924 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 921 925 { 922 926 /** @todo implement IA32_THERM_INTERRUPT. */ … … 927 931 928 932 /** @callback_method_impl{FNCPUMWRMSR} */ 929 static DECLCALLBACK( int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)933 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 930 934 { 931 935 /** @todo implement IA32_THERM_STATUS. */ … … 935 939 936 940 /** @callback_method_impl{FNCPUMRDMSR} */ 937 static DECLCALLBACK( int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)941 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 938 942 { 939 943 /** @todo implement IA32_THERM_STATUS. */ … … 944 948 945 949 /** @callback_method_impl{FNCPUMWRMSR} */ 946 static DECLCALLBACK( int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)950 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 947 951 { 948 952 /** @todo implement IA32_THERM_INTERRUPT. */ … … 952 956 953 957 /** @callback_method_impl{FNCPUMRDMSR} */ 954 static DECLCALLBACK( int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)958 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 955 959 { 956 960 /** @todo implement IA32_THERM2_CTL. */ … … 961 965 962 966 /** @callback_method_impl{FNCPUMWRMSR} */ 963 static DECLCALLBACK( int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)967 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 964 968 { 965 969 /** @todo implement IA32_THERM2_CTL. */ … … 969 973 970 974 /** @callback_method_impl{FNCPUMRDMSR} */ 971 static DECLCALLBACK( int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)975 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 972 976 { 973 977 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable; … … 977 981 978 982 /** @callback_method_impl{FNCPUMWRMSR} */ 979 static DECLCALLBACK( int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)983 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 980 984 { 981 985 #ifdef LOG_ENABLED … … 999 1003 1000 1004 /** @callback_method_impl{FNCPUMRDMSR} */ 1001 static DECLCALLBACK( int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1005 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1002 1006 { 1003 1007 /** @todo Implement machine check exception injection. */ … … 1023 1027 1024 1028 /** @callback_method_impl{FNCPUMWRMSR} */ 1025 static DECLCALLBACK( int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1029 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1026 1030 { 1027 1031 switch (idMsr & 3) … … 1068 1072 1069 1073 /** @callback_method_impl{FNCPUMRDMSR} */ 1070 static DECLCALLBACK( int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1074 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1071 1075 { 1072 1076 /** @todo Implement machine check exception injection. */ … … 1077 1081 1078 1082 /** @callback_method_impl{FNCPUMWRMSR} */ 1079 static DECLCALLBACK( int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1083 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1080 1084 { 1081 1085 /** @todo Implement machine check exception injection. */ … … 1085 1089 1086 1090 /** @callback_method_impl{FNCPUMRDMSR} */ 1087 static DECLCALLBACK( int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1091 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1088 1092 { 1089 1093 /** @todo implement IA32_DS_AREA. */ … … 1094 1098 1095 1099 /** @callback_method_impl{FNCPUMWRMSR} */ 1096 static DECLCALLBACK( int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1097 { 1098 return VINF_SUCCESS; 1099 } 1100 1101 1102 /** @callback_method_impl{FNCPUMRDMSR} */ 1103 static DECLCALLBACK( int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1100 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1101 { 1102 return VINF_SUCCESS; 1103 } 1104 1105 1106 /** @callback_method_impl{FNCPUMRDMSR} */ 1107 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1104 1108 { 1105 1109 /** @todo implement TSC deadline timer. */ … … 1110 1114 1111 1115 /** @callback_method_impl{FNCPUMWRMSR} */ 1112 static DECLCALLBACK( int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1116 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1113 1117 { 1114 1118 /** @todo implement TSC deadline timer. */ … … 1118 1122 1119 1123 /** @callback_method_impl{FNCPUMRDMSR} */ 1120 static DECLCALLBACK( int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1124 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1121 1125 { 1122 1126 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue); … … 1131 1135 1132 1136 /** @callback_method_impl{FNCPUMWRMSR} */ 1133 static DECLCALLBACK( int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1137 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1134 1138 { 1135 1139 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue); … … 1144 1148 1145 1149 /** @callback_method_impl{FNCPUMRDMSR} */ 1146 static DECLCALLBACK( int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1150 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1147 1151 { 1148 1152 /** @todo IA32_DEBUG_INTERFACE (no docs) */ … … 1153 1157 1154 1158 /** @callback_method_impl{FNCPUMWRMSR} */ 1155 static DECLCALLBACK( int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1159 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1156 1160 { 1157 1161 /** @todo IA32_DEBUG_INTERFACE (no docs) */ … … 1161 1165 1162 1166 /** @callback_method_impl{FNCPUMRDMSR} */ 1163 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1164 { 1165 *puValue = 0; 1166 return VINF_SUCCESS; 1167 } 1168 1169 1170 /** @callback_method_impl{FNCPUMRDMSR} */ 1171 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1172 { 1173 *puValue = 0; 1174 return VINF_SUCCESS; 1175 } 1176 1177 1178 /** @callback_method_impl{FNCPUMRDMSR} */ 1179 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1180 { 1181 *puValue = 0; 1182 return VINF_SUCCESS; 1183 } 1184 1185 1186 /** @callback_method_impl{FNCPUMRDMSR} */ 1187 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1188 { 1189 *puValue = 0; 1190 return VINF_SUCCESS; 1191 } 1192 1193 1194 /** @callback_method_impl{FNCPUMRDMSR} */ 1195 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1196 { 1197 *puValue = 0; 1198 return VINF_SUCCESS; 1199 } 1200 1201 1202 /** @callback_method_impl{FNCPUMRDMSR} */ 1203 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1204 { 1205 *puValue = 0; 1206 return VINF_SUCCESS; 1207 } 1208 1209 1210 /** @callback_method_impl{FNCPUMRDMSR} */ 1211 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1212 { 1213 *puValue = 0; 1214 return VINF_SUCCESS; 1215 } 1216 1217 1218 /** @callback_method_impl{FNCPUMRDMSR} */ 1219 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1220 { 1221 *puValue = 0; 1222 return VINF_SUCCESS; 1223 } 1224 1225 1226 /** @callback_method_impl{FNCPUMRDMSR} */ 1227 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1228 { 1229 *puValue = 0; 1230 return VINF_SUCCESS; 1231 } 1232 1233 1234 /** @callback_method_impl{FNCPUMRDMSR} */ 1235 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1236 { 1237 *puValue = 0; 1238 return VINF_SUCCESS; 1239 } 1240 1241 1242 /** @callback_method_impl{FNCPUMRDMSR} */ 1243 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1244 { 1245 *puValue = 0; 1246 return VINF_SUCCESS; 1247 } 1248 1249 1250 /** @callback_method_impl{FNCPUMRDMSR} */ 1251 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1252 { 1253 *puValue = 0; 1254 return VINF_SUCCESS; 1255 } 1256 1257 1258 /** @callback_method_impl{FNCPUMRDMSR} */ 1259 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1260 { 1261 *puValue = 0; 1262 return VINF_SUCCESS; 1263 } 1264 1265 1266 /** @callback_method_impl{FNCPUMRDMSR} */ 1267 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1268 { 1269 *puValue = 0; 1270 return VINF_SUCCESS; 1271 } 1272 1273 1274 /** @callback_method_impl{FNCPUMRDMSR} */ 1275 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1276 { 1277 *puValue = 0; 1278 return VINF_SUCCESS; 1279 } 1280 1281 1282 /** @callback_method_impl{FNCPUMRDMSR} */ 1283 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1284 { 1285 *puValue = 0; 1286 return VINF_SUCCESS; 1287 } 1288 1289 1290 /** @callback_method_impl{FNCPUMRDMSR} */ 1291 static DECLCALLBACK( int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1167 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1168 { 1169 *puValue = 0; 1170 return VINF_SUCCESS; 1171 } 1172 1173 1174 /** @callback_method_impl{FNCPUMRDMSR} */ 1175 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1176 { 1177 *puValue = 0; 1178 return VINF_SUCCESS; 1179 } 1180 1181 1182 /** @callback_method_impl{FNCPUMRDMSR} */ 1183 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1184 { 1185 *puValue = 0; 1186 return VINF_SUCCESS; 1187 } 1188 1189 1190 /** @callback_method_impl{FNCPUMRDMSR} */ 1191 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1192 { 1193 *puValue = 0; 1194 return VINF_SUCCESS; 1195 } 1196 1197 1198 /** @callback_method_impl{FNCPUMRDMSR} */ 1199 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1200 { 1201 *puValue = 0; 1202 return VINF_SUCCESS; 1203 } 1204 1205 1206 /** @callback_method_impl{FNCPUMRDMSR} */ 1207 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1208 { 1209 *puValue = 0; 1210 return VINF_SUCCESS; 1211 } 1212 1213 1214 /** @callback_method_impl{FNCPUMRDMSR} */ 1215 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1216 { 1217 *puValue = 0; 1218 return VINF_SUCCESS; 1219 } 1220 1221 1222 /** @callback_method_impl{FNCPUMRDMSR} */ 1223 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1224 { 1225 *puValue = 0; 1226 return VINF_SUCCESS; 1227 } 1228 1229 1230 /** @callback_method_impl{FNCPUMRDMSR} */ 1231 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1232 { 1233 *puValue = 0; 1234 return VINF_SUCCESS; 1235 } 1236 1237 1238 /** @callback_method_impl{FNCPUMRDMSR} */ 1239 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1240 { 1241 *puValue = 0; 1242 return VINF_SUCCESS; 1243 } 1244 1245 1246 /** @callback_method_impl{FNCPUMRDMSR} */ 1247 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1248 { 1249 *puValue = 0; 1250 return VINF_SUCCESS; 1251 } 1252 1253 1254 /** @callback_method_impl{FNCPUMRDMSR} */ 1255 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1256 { 1257 *puValue = 0; 1258 return VINF_SUCCESS; 1259 } 1260 1261 1262 /** @callback_method_impl{FNCPUMRDMSR} */ 1263 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1264 { 1265 *puValue = 0; 1266 return VINF_SUCCESS; 1267 } 1268 1269 1270 /** @callback_method_impl{FNCPUMRDMSR} */ 1271 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1272 { 1273 *puValue = 0; 1274 return VINF_SUCCESS; 1275 } 1276 1277 1278 /** @callback_method_impl{FNCPUMRDMSR} */ 1279 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1280 { 1281 *puValue = 0; 1282 return VINF_SUCCESS; 1283 } 1284 1285 1286 /** @callback_method_impl{FNCPUMRDMSR} */ 1287 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1288 { 1289 *puValue = 0; 1290 return VINF_SUCCESS; 1291 } 1292 1293 1294 /** @callback_method_impl{FNCPUMRDMSR} */ 1295 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1292 1296 { 1293 1297 *puValue = 0; … … 1312 1316 1313 1317 /** @callback_method_impl{FNCPUMRDMSR} */ 1314 static DECLCALLBACK( int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1318 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1315 1319 { 1316 1320 *puValue = pVCpu->cpum.s.Guest.msrEFER; … … 1320 1324 1321 1325 /** @callback_method_impl{FNCPUMWRMSR} */ 1322 static DECLCALLBACK( int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1326 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1323 1327 { 1324 1328 PVM pVM = pVCpu->CTX_SUFF(pVM); … … 1379 1383 1380 1384 /** @callback_method_impl{FNCPUMRDMSR} */ 1381 static DECLCALLBACK( int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1385 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1382 1386 { 1383 1387 *puValue = pVCpu->cpum.s.Guest.msrSTAR; … … 1387 1391 1388 1392 /** @callback_method_impl{FNCPUMWRMSR} */ 1389 static DECLCALLBACK( int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1393 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1390 1394 { 1391 1395 pVCpu->cpum.s.Guest.msrSTAR = uValue; … … 1395 1399 1396 1400 /** @callback_method_impl{FNCPUMRDMSR} */ 1397 static DECLCALLBACK( int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1401 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1398 1402 { 1399 1403 *puValue = pVCpu->cpum.s.Guest.msrLSTAR; … … 1403 1407 1404 1408 /** @callback_method_impl{FNCPUMWRMSR} */ 1405 static DECLCALLBACK( int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1409 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1406 1410 { 1407 1411 if (!X86_IS_CANONICAL(uValue)) … … 1416 1420 1417 1421 /** @callback_method_impl{FNCPUMRDMSR} */ 1418 static DECLCALLBACK( int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1422 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1419 1423 { 1420 1424 *puValue = pVCpu->cpum.s.Guest.msrCSTAR; … … 1424 1428 1425 1429 /** @callback_method_impl{FNCPUMWRMSR} */ 1426 static DECLCALLBACK( int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1430 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1427 1431 { 1428 1432 if (!X86_IS_CANONICAL(uValue)) … … 1437 1441 1438 1442 /** @callback_method_impl{FNCPUMRDMSR} */ 1439 static DECLCALLBACK( int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1443 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1440 1444 { 1441 1445 *puValue = pVCpu->cpum.s.Guest.msrSFMASK; … … 1445 1449 1446 1450 /** @callback_method_impl{FNCPUMWRMSR} */ 1447 static DECLCALLBACK( int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1451 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1448 1452 { 1449 1453 pVCpu->cpum.s.Guest.msrSFMASK = uValue; … … 1453 1457 1454 1458 /** @callback_method_impl{FNCPUMRDMSR} */ 1455 static DECLCALLBACK( int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1459 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1456 1460 { 1457 1461 *puValue = pVCpu->cpum.s.Guest.fs.u64Base; … … 1461 1465 1462 1466 /** @callback_method_impl{FNCPUMWRMSR} */ 1463 static DECLCALLBACK( int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1467 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1464 1468 { 1465 1469 pVCpu->cpum.s.Guest.fs.u64Base = uValue; … … 1469 1473 1470 1474 /** @callback_method_impl{FNCPUMRDMSR} */ 1471 static DECLCALLBACK( int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1475 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1472 1476 { 1473 1477 *puValue = pVCpu->cpum.s.Guest.gs.u64Base; … … 1476 1480 1477 1481 /** @callback_method_impl{FNCPUMWRMSR} */ 1478 static DECLCALLBACK( int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1482 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1479 1483 { 1480 1484 pVCpu->cpum.s.Guest.gs.u64Base = uValue; … … 1485 1489 1486 1490 /** @callback_method_impl{FNCPUMRDMSR} */ 1487 static DECLCALLBACK( int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1491 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1488 1492 { 1489 1493 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE; … … 1492 1496 1493 1497 /** @callback_method_impl{FNCPUMWRMSR} */ 1494 static DECLCALLBACK( int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1498 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1495 1499 { 1496 1500 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue; … … 1500 1504 1501 1505 /** @callback_method_impl{FNCPUMRDMSR} */ 1502 static DECLCALLBACK( int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1506 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1503 1507 { 1504 1508 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux; … … 1507 1511 1508 1512 /** @callback_method_impl{FNCPUMWRMSR} */ 1509 static DECLCALLBACK( int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1513 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1510 1514 { 1511 1515 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue; … … 1521 1525 1522 1526 /** @callback_method_impl{FNCPUMRDMSR} */ 1523 static DECLCALLBACK( int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1527 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1524 1528 { 1525 1529 /** @todo recalc clock frequency ratio? */ … … 1530 1534 1531 1535 /** @callback_method_impl{FNCPUMWRMSR} */ 1532 static DECLCALLBACK( int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1536 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1533 1537 { 1534 1538 /** @todo Write EBL_CR_POWERON: Remember written bits. */ … … 1538 1542 1539 1543 /** @callback_method_impl{FNCPUMRDMSR} */ 1540 static DECLCALLBACK( int) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1544 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1541 1545 { 1542 1546 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only … … 1550 1554 1551 1555 /** @callback_method_impl{FNCPUMRDMSR} */ 1552 static DECLCALLBACK( int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1556 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1553 1557 { 1554 1558 /** @todo P4 hard power on config */ … … 1559 1563 1560 1564 /** @callback_method_impl{FNCPUMWRMSR} */ 1561 static DECLCALLBACK( int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1565 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1562 1566 { 1563 1567 /** @todo P4 hard power on config */ … … 1567 1571 1568 1572 /** @callback_method_impl{FNCPUMRDMSR} */ 1569 static DECLCALLBACK( int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1573 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1570 1574 { 1571 1575 /** @todo P4 soft power on config */ … … 1576 1580 1577 1581 /** @callback_method_impl{FNCPUMWRMSR} */ 1578 static DECLCALLBACK( int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1582 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1579 1583 { 1580 1584 /** @todo P4 soft power on config */ … … 1584 1588 1585 1589 /** @callback_method_impl{FNCPUMRDMSR} */ 1586 static DECLCALLBACK( int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1590 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1587 1591 { 1588 1592 uint64_t uValue; … … 1642 1646 1643 1647 /** @callback_method_impl{FNCPUMWRMSR} */ 1644 static DECLCALLBACK( int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1648 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1645 1649 { 1646 1650 /** @todo P4 bus frequency config */ … … 1650 1654 1651 1655 /** @callback_method_impl{FNCPUMRDMSR} */ 1652 static DECLCALLBACK( int) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1656 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1653 1657 { 1654 1658 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */ … … 1676 1680 1677 1681 /** @callback_method_impl{FNCPUMRDMSR} */ 1678 static DECLCALLBACK( int) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1682 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1679 1683 { 1680 1684 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */ … … 1696 1700 1697 1701 /** @callback_method_impl{FNCPUMRDMSR} */ 1698 static DECLCALLBACK( int) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1702 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1699 1703 { 1700 1704 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00); … … 1712 1716 1713 1717 /** @callback_method_impl{FNCPUMWRMSR} */ 1714 static DECLCALLBACK( int) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1718 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1715 1719 { 1716 1720 /** @todo implement writing MSR_FLEX_RATIO. */ … … 1720 1724 1721 1725 /** @callback_method_impl{FNCPUMRDMSR} */ 1722 static DECLCALLBACK( int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1726 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1723 1727 { 1724 1728 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl; … … 1728 1732 1729 1733 /** @callback_method_impl{FNCPUMWRMSR} */ 1730 static DECLCALLBACK( int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1734 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1731 1735 { 1732 1736 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15)) … … 1748 1752 1749 1753 /** @callback_method_impl{FNCPUMRDMSR} */ 1750 static DECLCALLBACK( int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1754 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1751 1755 { 1752 1756 /** @todo implement I/O mwait wakeup. */ … … 1757 1761 1758 1762 /** @callback_method_impl{FNCPUMWRMSR} */ 1759 static DECLCALLBACK( int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1763 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1760 1764 { 1761 1765 /** @todo implement I/O mwait wakeup. */ … … 1765 1769 1766 1770 /** @callback_method_impl{FNCPUMRDMSR} */ 1767 static DECLCALLBACK( int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1771 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1768 1772 { 1769 1773 /** @todo implement last branch records. */ … … 1774 1778 1775 1779 /** @callback_method_impl{FNCPUMWRMSR} */ 1776 static DECLCALLBACK( int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1780 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1777 1781 { 1778 1782 /** @todo implement last branch records. */ … … 1782 1786 1783 1787 /** @callback_method_impl{FNCPUMRDMSR} */ 1784 static DECLCALLBACK( int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1788 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1785 1789 { 1786 1790 /** @todo implement last branch records. */ … … 1791 1795 1792 1796 /** @callback_method_impl{FNCPUMWRMSR} */ 1793 static DECLCALLBACK( int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1797 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1794 1798 { 1795 1799 /** @todo implement last branch records. */ … … 1807 1811 1808 1812 /** @callback_method_impl{FNCPUMRDMSR} */ 1809 static DECLCALLBACK( int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1813 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1810 1814 { 1811 1815 /** @todo implement last branch records. */ … … 1816 1820 1817 1821 /** @callback_method_impl{FNCPUMWRMSR} */ 1818 static DECLCALLBACK( int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1822 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1819 1823 { 1820 1824 /** @todo implement last branch records. */ … … 1832 1836 1833 1837 /** @callback_method_impl{FNCPUMRDMSR} */ 1834 static DECLCALLBACK( int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1838 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1835 1839 { 1836 1840 /** @todo implement last branch records. */ … … 1841 1845 1842 1846 /** @callback_method_impl{FNCPUMWRMSR} */ 1843 static DECLCALLBACK( int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1847 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1844 1848 { 1845 1849 /** @todo implement last branch records. */ … … 1849 1853 1850 1854 /** @callback_method_impl{FNCPUMRDMSR} */ 1851 static DECLCALLBACK( int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1855 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1852 1856 { 1853 1857 *puValue = pRange->uValue; … … 1857 1861 1858 1862 /** @callback_method_impl{FNCPUMWRMSR} */ 1859 static DECLCALLBACK( int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1860 { 1861 return VINF_SUCCESS; 1862 } 1863 1864 1865 /** @callback_method_impl{FNCPUMRDMSR} */ 1866 static DECLCALLBACK( int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1863 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1864 { 1865 return VINF_SUCCESS; 1866 } 1867 1868 1869 /** @callback_method_impl{FNCPUMRDMSR} */ 1870 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1867 1871 { 1868 1872 *puValue = pRange->uValue; … … 1872 1876 1873 1877 /** @callback_method_impl{FNCPUMWRMSR} */ 1874 static DECLCALLBACK( int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1875 { 1876 return VINF_SUCCESS; 1877 } 1878 1879 1880 /** @callback_method_impl{FNCPUMRDMSR} */ 1881 static DECLCALLBACK( int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1878 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1879 { 1880 return VINF_SUCCESS; 1881 } 1882 1883 1884 /** @callback_method_impl{FNCPUMRDMSR} */ 1885 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1882 1886 { 1883 1887 *puValue = pRange->uValue; … … 1887 1891 1888 1892 /** @callback_method_impl{FNCPUMWRMSR} */ 1889 static DECLCALLBACK( int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1890 { 1891 return VINF_SUCCESS; 1892 } 1893 1894 1895 /** @callback_method_impl{FNCPUMRDMSR} */ 1896 static DECLCALLBACK( int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1893 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1894 { 1895 return VINF_SUCCESS; 1896 } 1897 1898 1899 /** @callback_method_impl{FNCPUMRDMSR} */ 1900 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1897 1901 { 1898 1902 /** @todo machine check. */ … … 1903 1907 1904 1908 /** @callback_method_impl{FNCPUMWRMSR} */ 1905 static DECLCALLBACK( int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1909 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1906 1910 { 1907 1911 /** @todo machine check. */ … … 1911 1915 1912 1916 /** @callback_method_impl{FNCPUMRDMSR} */ 1913 static DECLCALLBACK( int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1914 { 1915 *puValue = 0; 1916 return VINF_SUCCESS; 1917 } 1918 1919 1920 /** @callback_method_impl{FNCPUMWRMSR} */ 1921 static DECLCALLBACK( int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1922 { 1923 return VINF_SUCCESS; 1924 } 1925 1926 1927 /** @callback_method_impl{FNCPUMRDMSR} */ 1928 static DECLCALLBACK( int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1917 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1918 { 1919 *puValue = 0; 1920 return VINF_SUCCESS; 1921 } 1922 1923 1924 /** @callback_method_impl{FNCPUMWRMSR} */ 1925 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1926 { 1927 return VINF_SUCCESS; 1928 } 1929 1930 1931 /** @callback_method_impl{FNCPUMRDMSR} */ 1932 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1929 1933 { 1930 1934 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue); … … 1935 1939 1936 1940 /** @callback_method_impl{FNCPUMWRMSR} */ 1937 static DECLCALLBACK( int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1941 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1938 1942 { 1939 1943 /* This CRx interface differs from the MOV CRx, GReg interface in that … … 1947 1951 1948 1952 /** @callback_method_impl{FNCPUMRDMSR} */ 1949 static DECLCALLBACK( int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1953 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1950 1954 { 1951 1955 /** @todo implement CPUID masking. */ … … 1956 1960 1957 1961 /** @callback_method_impl{FNCPUMWRMSR} */ 1958 static DECLCALLBACK( int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1962 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1959 1963 { 1960 1964 /** @todo implement CPUID masking. */ … … 1964 1968 1965 1969 /** @callback_method_impl{FNCPUMRDMSR} */ 1966 static DECLCALLBACK( int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1970 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1967 1971 { 1968 1972 /** @todo implement CPUID masking. */ … … 1972 1976 1973 1977 /** @callback_method_impl{FNCPUMWRMSR} */ 1974 static DECLCALLBACK( int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1978 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1975 1979 { 1976 1980 /** @todo implement CPUID masking. */ … … 1981 1985 1982 1986 /** @callback_method_impl{FNCPUMRDMSR} */ 1983 static DECLCALLBACK( int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)1987 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1984 1988 { 1985 1989 /** @todo implement CPUID masking. */ … … 1990 1994 1991 1995 /** @callback_method_impl{FNCPUMWRMSR} */ 1992 static DECLCALLBACK( int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)1996 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 1993 1997 { 1994 1998 /** @todo implement CPUID masking. */ … … 1999 2003 2000 2004 /** @callback_method_impl{FNCPUMRDMSR} */ 2001 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2005 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2002 2006 { 2003 2007 /** @todo implement AES-NI. */ … … 2008 2012 2009 2013 /** @callback_method_impl{FNCPUMWRMSR} */ 2010 static DECLCALLBACK( int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2014 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2011 2015 { 2012 2016 /** @todo implement AES-NI. */ … … 2016 2020 2017 2021 /** @callback_method_impl{FNCPUMRDMSR} */ 2018 static DECLCALLBACK( int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2022 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2019 2023 { 2020 2024 /** @todo implement intel C states. */ … … 2025 2029 2026 2030 /** @callback_method_impl{FNCPUMWRMSR} */ 2027 static DECLCALLBACK( int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2031 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2028 2032 { 2029 2033 /** @todo implement intel C states. */ … … 2033 2037 2034 2038 /** @callback_method_impl{FNCPUMRDMSR} */ 2035 static DECLCALLBACK( int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2039 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2036 2040 { 2037 2041 /** @todo implement last-branch-records. */ … … 2042 2046 2043 2047 /** @callback_method_impl{FNCPUMWRMSR} */ 2044 static DECLCALLBACK( int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2048 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2045 2049 { 2046 2050 /** @todo implement last-branch-records. */ … … 2050 2054 2051 2055 /** @callback_method_impl{FNCPUMRDMSR} */ 2052 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2056 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2053 2057 { 2054 2058 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */ … … 2059 2063 2060 2064 /** @callback_method_impl{FNCPUMWRMSR} */ 2061 static DECLCALLBACK( int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2065 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2062 2066 { 2063 2067 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */ … … 2067 2071 2068 2072 /** @callback_method_impl{FNCPUMRDMSR} */ 2069 static DECLCALLBACK( int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2073 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2070 2074 { 2071 2075 /** @todo implement memory VLW? */ … … 2084 2088 2085 2089 /** @callback_method_impl{FNCPUMRDMSR} */ 2086 static DECLCALLBACK( int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2090 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2087 2091 { 2088 2092 /** @todo intel power management */ … … 2093 2097 2094 2098 /** @callback_method_impl{FNCPUMWRMSR} */ 2095 static DECLCALLBACK( int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2099 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2096 2100 { 2097 2101 /** @todo intel power management */ … … 2101 2105 2102 2106 /** @callback_method_impl{FNCPUMRDMSR} */ 2103 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2107 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2104 2108 { 2105 2109 /** @todo intel performance counters. */ … … 2110 2114 2111 2115 /** @callback_method_impl{FNCPUMWRMSR} */ 2112 static DECLCALLBACK( int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2116 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2113 2117 { 2114 2118 /** @todo intel performance counters. */ … … 2118 2122 2119 2123 /** @callback_method_impl{FNCPUMRDMSR} */ 2120 static DECLCALLBACK( int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2124 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2121 2125 { 2122 2126 /** @todo intel performance counters. */ … … 2127 2131 2128 2132 /** @callback_method_impl{FNCPUMWRMSR} */ 2129 static DECLCALLBACK( int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2133 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2130 2134 { 2131 2135 /** @todo intel performance counters. */ … … 2135 2139 2136 2140 /** @callback_method_impl{FNCPUMRDMSR} */ 2137 static DECLCALLBACK( int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2141 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2138 2142 { 2139 2143 /** @todo intel power management. */ … … 2144 2148 2145 2149 /** @callback_method_impl{FNCPUMRDMSR} */ 2146 static DECLCALLBACK( int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2150 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2147 2151 { 2148 2152 /** @todo intel power management. */ … … 2153 2157 2154 2158 /** @callback_method_impl{FNCPUMRDMSR} */ 2155 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2159 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2156 2160 { 2157 2161 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */ … … 2162 2166 2163 2167 /** @callback_method_impl{FNCPUMWRMSR} */ 2164 static DECLCALLBACK( int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2168 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2165 2169 { 2166 2170 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */ … … 2170 2174 2171 2175 /** @callback_method_impl{FNCPUMRDMSR} */ 2172 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2176 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2173 2177 { 2174 2178 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */ … … 2179 2183 2180 2184 /** @callback_method_impl{FNCPUMWRMSR} */ 2181 static DECLCALLBACK( int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2185 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2182 2186 { 2183 2187 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */ … … 2187 2191 2188 2192 /** @callback_method_impl{FNCPUMRDMSR} */ 2189 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2193 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2190 2194 { 2191 2195 /** @todo intel RAPL. */ … … 2196 2200 2197 2201 /** @callback_method_impl{FNCPUMRDMSR} */ 2198 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2202 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2199 2203 { 2200 2204 /** @todo intel power management. */ … … 2205 2209 2206 2210 /** @callback_method_impl{FNCPUMWRMSR} */ 2207 static DECLCALLBACK( int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2211 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2208 2212 { 2209 2213 /** @todo intel power management. */ … … 2213 2217 2214 2218 /** @callback_method_impl{FNCPUMRDMSR} */ 2215 static DECLCALLBACK( int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2219 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2216 2220 { 2217 2221 /** @todo intel power management. */ … … 2222 2226 2223 2227 /** @callback_method_impl{FNCPUMRDMSR} */ 2224 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2228 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2225 2229 { 2226 2230 /** @todo intel RAPL. */ … … 2231 2235 2232 2236 /** @callback_method_impl{FNCPUMWRMSR} */ 2233 static DECLCALLBACK( int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2237 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2234 2238 { 2235 2239 /** @todo intel RAPL. */ … … 2239 2243 2240 2244 /** @callback_method_impl{FNCPUMRDMSR} */ 2241 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2245 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2242 2246 { 2243 2247 /** @todo intel power management. */ … … 2248 2252 2249 2253 /** @callback_method_impl{FNCPUMRDMSR} */ 2250 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2254 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2251 2255 { 2252 2256 /** @todo intel power management. */ … … 2257 2261 2258 2262 /** @callback_method_impl{FNCPUMRDMSR} */ 2259 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2263 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2260 2264 { 2261 2265 /** @todo intel power management. */ … … 2266 2270 2267 2271 /** @callback_method_impl{FNCPUMRDMSR} */ 2268 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2272 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2269 2273 { 2270 2274 /** @todo intel RAPL. */ … … 2275 2279 2276 2280 /** @callback_method_impl{FNCPUMWRMSR} */ 2277 static DECLCALLBACK( int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2281 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2278 2282 { 2279 2283 /** @todo intel RAPL. */ … … 2283 2287 2284 2288 /** @callback_method_impl{FNCPUMRDMSR} */ 2285 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2289 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2286 2290 { 2287 2291 /** @todo intel power management. */ … … 2292 2296 2293 2297 /** @callback_method_impl{FNCPUMRDMSR} */ 2294 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2298 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2295 2299 { 2296 2300 /** @todo intel power management. */ … … 2301 2305 2302 2306 /** @callback_method_impl{FNCPUMRDMSR} */ 2303 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2307 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2304 2308 { 2305 2309 /** @todo intel power management. */ … … 2310 2314 2311 2315 /** @callback_method_impl{FNCPUMRDMSR} */ 2312 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2316 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2313 2317 { 2314 2318 /** @todo intel RAPL. */ … … 2319 2323 2320 2324 /** @callback_method_impl{FNCPUMWRMSR} */ 2321 static DECLCALLBACK( int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2325 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2322 2326 { 2323 2327 /** @todo intel RAPL. */ … … 2327 2331 2328 2332 /** @callback_method_impl{FNCPUMRDMSR} */ 2329 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2333 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2330 2334 { 2331 2335 /** @todo intel power management. */ … … 2336 2340 2337 2341 /** @callback_method_impl{FNCPUMRDMSR} */ 2338 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2342 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2339 2343 { 2340 2344 /** @todo intel RAPL. */ … … 2345 2349 2346 2350 /** @callback_method_impl{FNCPUMWRMSR} */ 2347 static DECLCALLBACK( int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2351 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2348 2352 { 2349 2353 /** @todo intel RAPL. */ … … 2353 2357 2354 2358 /** @callback_method_impl{FNCPUMRDMSR} */ 2355 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2359 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2356 2360 { 2357 2361 /** @todo intel power management. */ … … 2362 2366 2363 2367 /** @callback_method_impl{FNCPUMRDMSR} */ 2364 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2368 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2365 2369 { 2366 2370 /** @todo intel RAPL. */ … … 2371 2375 2372 2376 /** @callback_method_impl{FNCPUMWRMSR} */ 2373 static DECLCALLBACK( int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2377 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2374 2378 { 2375 2379 /** @todo intel RAPL. */ … … 2379 2383 2380 2384 /** @callback_method_impl{FNCPUMRDMSR} */ 2381 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2385 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2382 2386 { 2383 2387 /** @todo intel power management. */ … … 2388 2392 2389 2393 /** @callback_method_impl{FNCPUMRDMSR} */ 2390 static DECLCALLBACK( int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2394 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2391 2395 { 2392 2396 /** @todo intel RAPL. */ … … 2397 2401 2398 2402 /** @callback_method_impl{FNCPUMWRMSR} */ 2399 static DECLCALLBACK( int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2403 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2400 2404 { 2401 2405 /** @todo intel RAPL. */ … … 2405 2409 2406 2410 /** @callback_method_impl{FNCPUMRDMSR} */ 2407 static DECLCALLBACK( int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2411 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2408 2412 { 2409 2413 /** @todo intel power management. */ … … 2414 2418 2415 2419 /** @callback_method_impl{FNCPUMRDMSR} */ 2416 static DECLCALLBACK( int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2420 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2417 2421 { 2418 2422 /** @todo intel power management. */ … … 2423 2427 2424 2428 /** @callback_method_impl{FNCPUMRDMSR} */ 2425 static DECLCALLBACK( int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2429 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2426 2430 { 2427 2431 /** @todo intel power management. */ … … 2432 2436 2433 2437 /** @callback_method_impl{FNCPUMRDMSR} */ 2434 static DECLCALLBACK( int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2438 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2435 2439 { 2436 2440 /** @todo intel power management. */ … … 2441 2445 2442 2446 /** @callback_method_impl{FNCPUMWRMSR} */ 2443 static DECLCALLBACK( int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2447 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2444 2448 { 2445 2449 /** @todo intel power management. */ … … 2449 2453 2450 2454 /** @callback_method_impl{FNCPUMRDMSR} */ 2451 static DECLCALLBACK( int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2455 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2452 2456 { 2453 2457 /** @todo intel power management. */ … … 2458 2462 2459 2463 /** @callback_method_impl{FNCPUMWRMSR} */ 2460 static DECLCALLBACK( int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2464 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2461 2465 { 2462 2466 /** @todo intel power management. */ … … 2466 2470 2467 2471 /** @callback_method_impl{FNCPUMRDMSR} */ 2468 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2472 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2469 2473 { 2470 2474 /** @todo uncore msrs. */ … … 2475 2479 2476 2480 /** @callback_method_impl{FNCPUMWRMSR} */ 2477 static DECLCALLBACK( int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2481 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2478 2482 { 2479 2483 /** @todo uncore msrs. */ … … 2483 2487 2484 2488 /** @callback_method_impl{FNCPUMRDMSR} */ 2485 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2489 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2486 2490 { 2487 2491 /** @todo uncore msrs. */ … … 2492 2496 2493 2497 /** @callback_method_impl{FNCPUMWRMSR} */ 2494 static DECLCALLBACK( int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2498 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2495 2499 { 2496 2500 /** @todo uncore msrs. */ … … 2500 2504 2501 2505 /** @callback_method_impl{FNCPUMRDMSR} */ 2502 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2506 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2503 2507 { 2504 2508 /** @todo uncore msrs. */ … … 2509 2513 2510 2514 /** @callback_method_impl{FNCPUMWRMSR} */ 2511 static DECLCALLBACK( int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2515 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2512 2516 { 2513 2517 /** @todo uncore msrs. */ … … 2517 2521 2518 2522 /** @callback_method_impl{FNCPUMRDMSR} */ 2519 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2523 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2520 2524 { 2521 2525 /** @todo uncore msrs. */ … … 2526 2530 2527 2531 /** @callback_method_impl{FNCPUMWRMSR} */ 2528 static DECLCALLBACK( int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2532 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2529 2533 { 2530 2534 /** @todo uncore msrs. */ … … 2534 2538 2535 2539 /** @callback_method_impl{FNCPUMRDMSR} */ 2536 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2540 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2537 2541 { 2538 2542 /** @todo uncore msrs. */ … … 2543 2547 2544 2548 /** @callback_method_impl{FNCPUMWRMSR} */ 2545 static DECLCALLBACK( int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2549 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2546 2550 { 2547 2551 /** @todo uncore msrs. */ … … 2551 2555 2552 2556 /** @callback_method_impl{FNCPUMRDMSR} */ 2553 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2557 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2554 2558 { 2555 2559 /** @todo uncore msrs. */ … … 2560 2564 2561 2565 /** @callback_method_impl{FNCPUMRDMSR} */ 2562 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2566 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2563 2567 { 2564 2568 /** @todo uncore msrs. */ … … 2569 2573 2570 2574 /** @callback_method_impl{FNCPUMWRMSR} */ 2571 static DECLCALLBACK( int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2575 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2572 2576 { 2573 2577 /** @todo uncore msrs. */ … … 2577 2581 2578 2582 /** @callback_method_impl{FNCPUMRDMSR} */ 2579 static DECLCALLBACK( int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2583 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2580 2584 { 2581 2585 /** @todo uncore msrs. */ … … 2586 2590 2587 2591 /** @callback_method_impl{FNCPUMWRMSR} */ 2588 static DECLCALLBACK( int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2592 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2589 2593 { 2590 2594 /** @todo uncore msrs. */ … … 2594 2598 2595 2599 /** @callback_method_impl{FNCPUMRDMSR} */ 2596 static DECLCALLBACK( int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2600 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2597 2601 { 2598 2602 /** @todo implement enhanced multi thread termal monitoring? */ … … 2603 2607 2604 2608 /** @callback_method_impl{FNCPUMWRMSR} */ 2605 static DECLCALLBACK( int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2609 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2606 2610 { 2607 2611 /** @todo implement enhanced multi thread termal monitoring? */ … … 2611 2615 2612 2616 /** @callback_method_impl{FNCPUMRDMSR} */ 2613 static DECLCALLBACK( int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2617 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2614 2618 { 2615 2619 /** @todo SMM & C-states? */ … … 2620 2624 2621 2625 /** @callback_method_impl{FNCPUMWRMSR} */ 2622 static DECLCALLBACK( int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2626 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2623 2627 { 2624 2628 /** @todo SMM & C-states? */ … … 2628 2632 2629 2633 /** @callback_method_impl{FNCPUMRDMSR} */ 2630 static DECLCALLBACK( int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2634 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2631 2635 { 2632 2636 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */ … … 2637 2641 2638 2642 /** @callback_method_impl{FNCPUMWRMSR} */ 2639 static DECLCALLBACK( int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2643 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2640 2644 { 2641 2645 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */ … … 2645 2649 2646 2650 /** @callback_method_impl{FNCPUMRDMSR} */ 2647 static DECLCALLBACK( int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2651 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2648 2652 { 2649 2653 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */ … … 2654 2658 2655 2659 /** @callback_method_impl{FNCPUMWRMSR} */ 2656 static DECLCALLBACK( int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2660 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2657 2661 { 2658 2662 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */ … … 2662 2666 2663 2667 /** @callback_method_impl{FNCPUMRDMSR} */ 2664 static DECLCALLBACK( int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2668 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2665 2669 { 2666 2670 /** @todo Core2+ platform environment control interface control register? */ … … 2671 2675 2672 2676 /** @callback_method_impl{FNCPUMWRMSR} */ 2673 static DECLCALLBACK( int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2677 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2674 2678 { 2675 2679 /** @todo Core2+ platform environment control interface control register? */ … … 2690 2694 2691 2695 /** @callback_method_impl{FNCPUMRDMSR} */ 2692 static DECLCALLBACK( int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2696 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2693 2697 { 2694 2698 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE … … 2701 2705 2702 2706 /** @callback_method_impl{FNCPUMRDMSR} */ 2703 static DECLCALLBACK( int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2707 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2704 2708 { 2705 2709 /** @todo implement last branch records. */ … … 2710 2714 2711 2715 /** @callback_method_impl{FNCPUMRDMSR} */ 2712 static DECLCALLBACK( int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2716 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2713 2717 { 2714 2718 /** @todo implement last exception records. */ … … 2719 2723 2720 2724 /** @callback_method_impl{FNCPUMWRMSR} */ 2721 static DECLCALLBACK( int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2725 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2722 2726 { 2723 2727 /** @todo implement last exception records. */ … … 2729 2733 2730 2734 /** @callback_method_impl{FNCPUMRDMSR} */ 2731 static DECLCALLBACK( int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2735 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2732 2736 { 2733 2737 /** @todo implement last exception records. */ … … 2738 2742 2739 2743 /** @callback_method_impl{FNCPUMWRMSR} */ 2740 static DECLCALLBACK( int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2744 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2741 2745 { 2742 2746 /** @todo implement last exception records. */ … … 2754 2758 2755 2759 /** @callback_method_impl{FNCPUMRDMSR} */ 2756 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2760 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2757 2761 { 2758 2762 /** @todo Implement TscRateMsr */ … … 2763 2767 2764 2768 /** @callback_method_impl{FNCPUMWRMSR} */ 2765 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2769 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2766 2770 { 2767 2771 /** @todo Implement TscRateMsr */ … … 2771 2775 2772 2776 /** @callback_method_impl{FNCPUMRDMSR} */ 2773 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2777 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2774 2778 { 2775 2779 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */ … … 2781 2785 2782 2786 /** @callback_method_impl{FNCPUMWRMSR} */ 2783 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2787 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2784 2788 { 2785 2789 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */ … … 2789 2793 2790 2794 /** @callback_method_impl{FNCPUMRDMSR} */ 2791 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2795 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2792 2796 { 2793 2797 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */ … … 2799 2803 2800 2804 /** @callback_method_impl{FNCPUMWRMSR} */ 2801 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2805 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2802 2806 { 2803 2807 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */ … … 2807 2811 2808 2812 /** @callback_method_impl{FNCPUMRDMSR} */ 2809 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2813 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2810 2814 { 2811 2815 /** @todo machine check. */ … … 2816 2820 2817 2821 /** @callback_method_impl{FNCPUMWRMSR} */ 2818 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2822 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2819 2823 { 2820 2824 /** @todo machine check. */ … … 2824 2828 2825 2829 /** @callback_method_impl{FNCPUMRDMSR} */ 2826 static DECLCALLBACK( int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2830 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2827 2831 { 2828 2832 /** @todo AMD performance events. */ … … 2833 2837 2834 2838 /** @callback_method_impl{FNCPUMWRMSR} */ 2835 static DECLCALLBACK( int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2839 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2836 2840 { 2837 2841 /** @todo AMD performance events. */ … … 2841 2845 2842 2846 /** @callback_method_impl{FNCPUMRDMSR} */ 2843 static DECLCALLBACK( int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2847 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2844 2848 { 2845 2849 /** @todo AMD performance events. */ … … 2850 2854 2851 2855 /** @callback_method_impl{FNCPUMWRMSR} */ 2852 static DECLCALLBACK( int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2856 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2853 2857 { 2854 2858 /** @todo AMD performance events. */ … … 2858 2862 2859 2863 /** @callback_method_impl{FNCPUMRDMSR} */ 2860 static DECLCALLBACK( int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2864 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2861 2865 { 2862 2866 /** @todo AMD SYS_CFG */ … … 2867 2871 2868 2872 /** @callback_method_impl{FNCPUMWRMSR} */ 2869 static DECLCALLBACK( int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2873 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2870 2874 { 2871 2875 /** @todo AMD SYS_CFG */ … … 2875 2879 2876 2880 /** @callback_method_impl{FNCPUMRDMSR} */ 2877 static DECLCALLBACK( int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2881 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2878 2882 { 2879 2883 /** @todo AMD HW_CFG */ … … 2884 2888 2885 2889 /** @callback_method_impl{FNCPUMWRMSR} */ 2886 static DECLCALLBACK( int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2890 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2887 2891 { 2888 2892 /** @todo AMD HW_CFG */ … … 2892 2896 2893 2897 /** @callback_method_impl{FNCPUMRDMSR} */ 2894 static DECLCALLBACK( int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2898 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2895 2899 { 2896 2900 /** @todo AMD IorrMask/IorrBase */ … … 2901 2905 2902 2906 /** @callback_method_impl{FNCPUMWRMSR} */ 2903 static DECLCALLBACK( int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2907 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2904 2908 { 2905 2909 /** @todo AMD IorrMask/IorrBase */ … … 2909 2913 2910 2914 /** @callback_method_impl{FNCPUMRDMSR} */ 2911 static DECLCALLBACK( int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2915 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2912 2916 { 2913 2917 /** @todo AMD IorrMask/IorrBase */ … … 2918 2922 2919 2923 /** @callback_method_impl{FNCPUMWRMSR} */ 2920 static DECLCALLBACK( int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2924 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2921 2925 { 2922 2926 /** @todo AMD IorrMask/IorrBase */ … … 2926 2930 2927 2931 /** @callback_method_impl{FNCPUMRDMSR} */ 2928 static DECLCALLBACK( int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2932 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2929 2933 { 2930 2934 *puValue = 0; … … 2938 2942 2939 2943 /** @callback_method_impl{FNCPUMWRMSR} */ 2940 static DECLCALLBACK( int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2944 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2941 2945 { 2942 2946 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */ … … 2946 2950 2947 2951 /** @callback_method_impl{FNCPUMRDMSR} */ 2948 static DECLCALLBACK( int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2952 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2949 2953 { 2950 2954 /** @todo AMD NB_CFG1 */ … … 2955 2959 2956 2960 /** @callback_method_impl{FNCPUMWRMSR} */ 2957 static DECLCALLBACK( int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2961 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2958 2962 { 2959 2963 /** @todo AMD NB_CFG1 */ … … 2963 2967 2964 2968 /** @callback_method_impl{FNCPUMRDMSR} */ 2965 static DECLCALLBACK( int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2969 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2966 2970 { 2967 2971 /** @todo machine check. */ … … 2972 2976 2973 2977 /** @callback_method_impl{FNCPUMWRMSR} */ 2974 static DECLCALLBACK( int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)2978 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2975 2979 { 2976 2980 /** @todo machine check. */ … … 2980 2984 2981 2985 /** @callback_method_impl{FNCPUMRDMSR} */ 2982 static DECLCALLBACK( int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)2986 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2983 2987 { 2984 2988 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0); … … 2997 3001 2998 3002 /** @callback_method_impl{FNCPUMWRMSR} */ 2999 static DECLCALLBACK( int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3003 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3000 3004 { 3001 3005 /** @todo Remember guest programmed CPU name. */ … … 3005 3009 3006 3010 /** @callback_method_impl{FNCPUMRDMSR} */ 3007 static DECLCALLBACK( int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3011 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3008 3012 { 3009 3013 /** @todo AMD HTC. */ … … 3014 3018 3015 3019 /** @callback_method_impl{FNCPUMWRMSR} */ 3016 static DECLCALLBACK( int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3020 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3017 3021 { 3018 3022 /** @todo AMD HTC. */ … … 3022 3026 3023 3027 /** @callback_method_impl{FNCPUMRDMSR} */ 3024 static DECLCALLBACK( int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3028 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3025 3029 { 3026 3030 /** @todo AMD STC. */ … … 3031 3035 3032 3036 /** @callback_method_impl{FNCPUMWRMSR} */ 3033 static DECLCALLBACK( int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3037 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3034 3038 { 3035 3039 /** @todo AMD STC. */ … … 3039 3043 3040 3044 /** @callback_method_impl{FNCPUMRDMSR} */ 3041 static DECLCALLBACK( int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3045 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3042 3046 { 3043 3047 /** @todo AMD FIDVID_CTL. */ … … 3048 3052 3049 3053 /** @callback_method_impl{FNCPUMWRMSR} */ 3050 static DECLCALLBACK( int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3054 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3051 3055 { 3052 3056 /** @todo AMD FIDVID_CTL. */ … … 3056 3060 3057 3061 /** @callback_method_impl{FNCPUMRDMSR} */ 3058 static DECLCALLBACK( int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3062 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3059 3063 { 3060 3064 /** @todo AMD FIDVID_STATUS. */ … … 3065 3069 3066 3070 /** @callback_method_impl{FNCPUMRDMSR} */ 3067 static DECLCALLBACK( int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3071 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3068 3072 { 3069 3073 /** @todo AMD MC. */ … … 3074 3078 3075 3079 /** @callback_method_impl{FNCPUMWRMSR} */ 3076 static DECLCALLBACK( int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3080 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3077 3081 { 3078 3082 /** @todo AMD MC. */ … … 3082 3086 3083 3087 /** @callback_method_impl{FNCPUMRDMSR} */ 3084 static DECLCALLBACK( int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3088 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3085 3089 { 3086 3090 /** @todo AMD SMM/SMI and I/O trap. */ … … 3091 3095 3092 3096 /** @callback_method_impl{FNCPUMWRMSR} */ 3093 static DECLCALLBACK( int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3097 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3094 3098 { 3095 3099 /** @todo AMD SMM/SMI and I/O trap. */ … … 3099 3103 3100 3104 /** @callback_method_impl{FNCPUMRDMSR} */ 3101 static DECLCALLBACK( int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3105 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3102 3106 { 3103 3107 /** @todo AMD SMM/SMI and I/O trap. */ … … 3108 3112 3109 3113 /** @callback_method_impl{FNCPUMWRMSR} */ 3110 static DECLCALLBACK( int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3114 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3111 3115 { 3112 3116 /** @todo AMD SMM/SMI and I/O trap. */ … … 3116 3120 3117 3121 /** @callback_method_impl{FNCPUMRDMSR} */ 3118 static DECLCALLBACK( int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3122 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3119 3123 { 3120 3124 /** @todo Interrupt pending message. */ … … 3125 3129 3126 3130 /** @callback_method_impl{FNCPUMWRMSR} */ 3127 static DECLCALLBACK( int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3131 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3128 3132 { 3129 3133 /** @todo Interrupt pending message. */ … … 3133 3137 3134 3138 /** @callback_method_impl{FNCPUMRDMSR} */ 3135 static DECLCALLBACK( int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3139 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3136 3140 { 3137 3141 /** @todo AMD SMM/SMI and trigger I/O cycle. */ … … 3142 3146 3143 3147 /** @callback_method_impl{FNCPUMWRMSR} */ 3144 static DECLCALLBACK( int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3148 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3145 3149 { 3146 3150 /** @todo AMD SMM/SMI and trigger I/O cycle. */ … … 3150 3154 3151 3155 /** @callback_method_impl{FNCPUMRDMSR} */ 3152 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3156 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3153 3157 { 3154 3158 /** @todo AMD MMIO Configuration base address. */ … … 3159 3163 3160 3164 /** @callback_method_impl{FNCPUMWRMSR} */ 3161 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3165 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3162 3166 { 3163 3167 /** @todo AMD MMIO Configuration base address. */ … … 3167 3171 3168 3172 /** @callback_method_impl{FNCPUMRDMSR} */ 3169 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3173 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3170 3174 { 3171 3175 /** @todo AMD 0xc0010059. */ … … 3176 3180 3177 3181 /** @callback_method_impl{FNCPUMWRMSR} */ 3178 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3182 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3179 3183 { 3180 3184 /** @todo AMD 0xc0010059. */ … … 3184 3188 3185 3189 /** @callback_method_impl{FNCPUMRDMSR} */ 3186 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3190 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3187 3191 { 3188 3192 /** @todo AMD P-states. */ … … 3193 3197 3194 3198 /** @callback_method_impl{FNCPUMRDMSR} */ 3195 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3199 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3196 3200 { 3197 3201 /** @todo AMD P-states. */ … … 3202 3206 3203 3207 /** @callback_method_impl{FNCPUMWRMSR} */ 3204 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3208 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3205 3209 { 3206 3210 /** @todo AMD P-states. */ … … 3210 3214 3211 3215 /** @callback_method_impl{FNCPUMRDMSR} */ 3212 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3216 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3213 3217 { 3214 3218 /** @todo AMD P-states. */ … … 3219 3223 3220 3224 /** @callback_method_impl{FNCPUMWRMSR} */ 3221 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3225 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3222 3226 { 3223 3227 /** @todo AMD P-states. */ … … 3227 3231 3228 3232 /** @callback_method_impl{FNCPUMRDMSR} */ 3229 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3233 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3230 3234 { 3231 3235 /** @todo AMD P-states. */ … … 3236 3240 3237 3241 /** @callback_method_impl{FNCPUMWRMSR} */ 3238 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3242 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3239 3243 { 3240 3244 /** @todo AMD P-states. */ … … 3244 3248 3245 3249 /** @callback_method_impl{FNCPUMRDMSR} */ 3246 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3250 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3247 3251 { 3248 3252 /** @todo AMD P-states. */ … … 3253 3257 3254 3258 /** @callback_method_impl{FNCPUMWRMSR} */ 3255 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3259 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3256 3260 { 3257 3261 /** @todo AMD P-states. */ … … 3261 3265 3262 3266 /** @callback_method_impl{FNCPUMRDMSR} */ 3263 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3267 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3264 3268 { 3265 3269 /** @todo AMD P-states. */ … … 3270 3274 3271 3275 /** @callback_method_impl{FNCPUMWRMSR} */ 3272 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3276 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3273 3277 { 3274 3278 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */ … … 3279 3283 3280 3284 /** @callback_method_impl{FNCPUMRDMSR} */ 3281 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3285 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3282 3286 { 3283 3287 /** @todo AMD C-states. */ … … 3288 3292 3289 3293 /** @callback_method_impl{FNCPUMWRMSR} */ 3290 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3294 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3291 3295 { 3292 3296 /** @todo AMD C-states. */ … … 3296 3300 3297 3301 /** @callback_method_impl{FNCPUMRDMSR} */ 3298 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3302 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3299 3303 { 3300 3304 /** @todo AMD machine checks. */ … … 3305 3309 3306 3310 /** @callback_method_impl{FNCPUMWRMSR} */ 3307 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3311 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3308 3312 { 3309 3313 /** @todo AMD machine checks. */ … … 3313 3317 3314 3318 /** @callback_method_impl{FNCPUMRDMSR} */ 3315 static DECLCALLBACK( int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3319 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3316 3320 { 3317 3321 /** @todo AMD SMM. */ … … 3322 3326 3323 3327 /** @callback_method_impl{FNCPUMWRMSR} */ 3324 static DECLCALLBACK( int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3328 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3325 3329 { 3326 3330 /** @todo AMD SMM. */ … … 3330 3334 3331 3335 /** @callback_method_impl{FNCPUMRDMSR} */ 3332 static DECLCALLBACK( int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3336 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3333 3337 { 3334 3338 /** @todo AMD SMM. */ … … 3339 3343 3340 3344 /** @callback_method_impl{FNCPUMWRMSR} */ 3341 static DECLCALLBACK( int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3345 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3342 3346 { 3343 3347 /** @todo AMD SMM. */ … … 3348 3352 3349 3353 /** @callback_method_impl{FNCPUMRDMSR} */ 3350 static DECLCALLBACK( int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3354 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3351 3355 { 3352 3356 /** @todo AMD SMM. */ … … 3357 3361 3358 3362 /** @callback_method_impl{FNCPUMWRMSR} */ 3359 static DECLCALLBACK( int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3363 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3360 3364 { 3361 3365 /** @todo AMD SMM. */ … … 3365 3369 3366 3370 /** @callback_method_impl{FNCPUMRDMSR} */ 3367 static DECLCALLBACK( int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3371 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3368 3372 { 3369 3373 /** @todo AMD SVM. */ … … 3374 3378 3375 3379 /** @callback_method_impl{FNCPUMWRMSR} */ 3376 static DECLCALLBACK( int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3380 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3377 3381 { 3378 3382 /** @todo AMD SVM. */ … … 3382 3386 3383 3387 /** @callback_method_impl{FNCPUMRDMSR} */ 3384 static DECLCALLBACK( int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3388 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3385 3389 { 3386 3390 /** @todo AMD IGNNE\# control. */ … … 3391 3395 3392 3396 /** @callback_method_impl{FNCPUMWRMSR} */ 3393 static DECLCALLBACK( int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3397 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3394 3398 { 3395 3399 /** @todo AMD IGNNE\# control. */ … … 3399 3403 3400 3404 /** @callback_method_impl{FNCPUMRDMSR} */ 3401 static DECLCALLBACK( int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3405 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3402 3406 { 3403 3407 /** @todo AMD SMM. */ … … 3408 3412 3409 3413 /** @callback_method_impl{FNCPUMWRMSR} */ 3410 static DECLCALLBACK( int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3414 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3411 3415 { 3412 3416 /** @todo AMD SMM. */ … … 3416 3420 3417 3421 /** @callback_method_impl{FNCPUMRDMSR} */ 3418 static DECLCALLBACK( int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3422 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3419 3423 { 3420 3424 /** @todo AMD SVM. */ … … 3425 3429 3426 3430 /** @callback_method_impl{FNCPUMWRMSR} */ 3427 static DECLCALLBACK( int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3431 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3428 3432 { 3429 3433 /** @todo AMD SVM. */ … … 3433 3437 3434 3438 /** @callback_method_impl{FNCPUMRDMSR} */ 3435 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3439 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3436 3440 { 3437 3441 /** @todo AMD SVM. */ … … 3442 3446 3443 3447 /** @callback_method_impl{FNCPUMWRMSR} */ 3444 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3448 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3445 3449 { 3446 3450 /** @todo AMD SVM. */ … … 3450 3454 3451 3455 /** @callback_method_impl{FNCPUMRDMSR} */ 3452 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3456 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3453 3457 { 3454 3458 /** @todo AMD SMM. */ … … 3459 3463 3460 3464 /** @callback_method_impl{FNCPUMWRMSR} */ 3461 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3465 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3462 3466 { 3463 3467 /** @todo AMD SMM. */ … … 3467 3471 3468 3472 /** @callback_method_impl{FNCPUMRDMSR} */ 3469 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3473 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3470 3474 { 3471 3475 /** @todo AMD SMM/SMI. */ … … 3476 3480 3477 3481 /** @callback_method_impl{FNCPUMWRMSR} */ 3478 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3482 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3479 3483 { 3480 3484 /** @todo AMD SMM/SMI. */ … … 3484 3488 3485 3489 /** @callback_method_impl{FNCPUMRDMSR} */ 3486 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3490 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3487 3491 { 3488 3492 /** @todo AMD OS visible workaround. */ … … 3493 3497 3494 3498 /** @callback_method_impl{FNCPUMWRMSR} */ 3495 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3499 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3496 3500 { 3497 3501 /** @todo AMD OS visible workaround. */ … … 3501 3505 3502 3506 /** @callback_method_impl{FNCPUMRDMSR} */ 3503 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3507 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3504 3508 { 3505 3509 /** @todo AMD OS visible workaround. */ … … 3510 3514 3511 3515 /** @callback_method_impl{FNCPUMWRMSR} */ 3512 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3516 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3513 3517 { 3514 3518 /** @todo AMD OS visible workaround. */ … … 3518 3522 3519 3523 /** @callback_method_impl{FNCPUMRDMSR} */ 3520 static DECLCALLBACK( int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3524 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3521 3525 { 3522 3526 /** @todo AMD L2I performance counters. */ … … 3527 3531 3528 3532 /** @callback_method_impl{FNCPUMWRMSR} */ 3529 static DECLCALLBACK( int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3533 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3530 3534 { 3531 3535 /** @todo AMD L2I performance counters. */ … … 3535 3539 3536 3540 /** @callback_method_impl{FNCPUMRDMSR} */ 3537 static DECLCALLBACK( int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3541 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3538 3542 { 3539 3543 /** @todo AMD L2I performance counters. */ … … 3544 3548 3545 3549 /** @callback_method_impl{FNCPUMWRMSR} */ 3546 static DECLCALLBACK( int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3550 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3547 3551 { 3548 3552 /** @todo AMD L2I performance counters. */ … … 3552 3556 3553 3557 /** @callback_method_impl{FNCPUMRDMSR} */ 3554 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3558 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3555 3559 { 3556 3560 /** @todo AMD Northbridge performance counters. */ … … 3561 3565 3562 3566 /** @callback_method_impl{FNCPUMWRMSR} */ 3563 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3567 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3564 3568 { 3565 3569 /** @todo AMD Northbridge performance counters. */ … … 3569 3573 3570 3574 /** @callback_method_impl{FNCPUMRDMSR} */ 3571 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3575 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3572 3576 { 3573 3577 /** @todo AMD Northbridge performance counters. */ … … 3578 3582 3579 3583 /** @callback_method_impl{FNCPUMWRMSR} */ 3580 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3584 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3581 3585 { 3582 3586 /** @todo AMD Northbridge performance counters. */ … … 3586 3590 3587 3591 /** @callback_method_impl{FNCPUMRDMSR} */ 3588 static DECLCALLBACK( int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3592 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3589 3593 { 3590 3594 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3597 3601 3598 3602 /** @callback_method_impl{FNCPUMWRMSR} */ 3599 static DECLCALLBACK( int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3603 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3600 3604 { 3601 3605 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3607 3611 3608 3612 /** @callback_method_impl{FNCPUMRDMSR} */ 3609 static DECLCALLBACK( int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3613 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3610 3614 { 3611 3615 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3619 3623 3620 3624 /** @callback_method_impl{FNCPUMWRMSR} */ 3621 static DECLCALLBACK( int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3625 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3622 3626 { 3623 3627 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3630 3634 3631 3635 /** @callback_method_impl{FNCPUMRDMSR} */ 3632 static DECLCALLBACK( int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3636 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3633 3637 { 3634 3638 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0); … … 3642 3646 3643 3647 /** @callback_method_impl{FNCPUMWRMSR} */ 3644 static DECLCALLBACK( int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3648 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3645 3649 { 3646 3650 /** @todo Changing CPUID leaf 7/0. */ … … 3650 3654 3651 3655 /** @callback_method_impl{FNCPUMRDMSR} */ 3652 static DECLCALLBACK( int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3656 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3653 3657 { 3654 3658 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0); … … 3662 3666 3663 3667 /** @callback_method_impl{FNCPUMWRMSR} */ 3664 static DECLCALLBACK( int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3668 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3665 3669 { 3666 3670 /** @todo Changing CPUID leaf 6. */ … … 3670 3674 3671 3675 /** @callback_method_impl{FNCPUMRDMSR} */ 3672 static DECLCALLBACK( int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3676 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3673 3677 { 3674 3678 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0); … … 3682 3686 3683 3687 /** @callback_method_impl{FNCPUMWRMSR} */ 3684 static DECLCALLBACK( int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3688 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3685 3689 { 3686 3690 /** @todo Changing CPUID leaf 0x80000001. */ … … 3690 3694 3691 3695 /** @callback_method_impl{FNCPUMRDMSR} */ 3692 static DECLCALLBACK( int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3696 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3693 3697 { 3694 3698 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0); … … 3702 3706 3703 3707 /** @callback_method_impl{FNCPUMWRMSR} */ 3704 static DECLCALLBACK( int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3708 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3705 3709 { 3706 3710 /** @todo Changing CPUID leaf 0x80000001. */ … … 3710 3714 3711 3715 /** @callback_method_impl{FNCPUMRDMSR} */ 3712 static DECLCALLBACK( int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3716 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3713 3717 { 3714 3718 /** @todo Fake AMD microcode patching. */ … … 3719 3723 3720 3724 /** @callback_method_impl{FNCPUMWRMSR} */ 3721 static DECLCALLBACK( int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3725 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3722 3726 { 3723 3727 /** @todo Fake AMD microcode patching. */ … … 3727 3731 3728 3732 /** @callback_method_impl{FNCPUMRDMSR} */ 3729 static DECLCALLBACK( int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3733 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3730 3734 { 3731 3735 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3738 3742 3739 3743 /** @callback_method_impl{FNCPUMWRMSR} */ 3740 static DECLCALLBACK( int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3744 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3741 3745 { 3742 3746 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3748 3752 3749 3753 /** @callback_method_impl{FNCPUMRDMSR} */ 3750 static DECLCALLBACK( int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3754 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3751 3755 { 3752 3756 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3759 3763 3760 3764 /** @callback_method_impl{FNCPUMWRMSR} */ 3761 static DECLCALLBACK( int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3765 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3762 3766 { 3763 3767 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3769 3773 3770 3774 /** @callback_method_impl{FNCPUMRDMSR} */ 3771 static DECLCALLBACK( int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3775 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3772 3776 { 3773 3777 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3780 3784 3781 3785 /** @callback_method_impl{FNCPUMWRMSR} */ 3782 static DECLCALLBACK( int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3786 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3783 3787 { 3784 3788 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3790 3794 3791 3795 /** @callback_method_impl{FNCPUMRDMSR} */ 3792 static DECLCALLBACK( int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3796 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3793 3797 { 3794 3798 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3801 3805 3802 3806 /** @callback_method_impl{FNCPUMWRMSR} */ 3803 static DECLCALLBACK( int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3807 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3804 3808 { 3805 3809 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3811 3815 3812 3816 /** @callback_method_impl{FNCPUMRDMSR} */ 3813 static DECLCALLBACK( int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3817 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3814 3818 { 3815 3819 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3822 3826 3823 3827 /** @callback_method_impl{FNCPUMWRMSR} */ 3824 static DECLCALLBACK( int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3828 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3825 3829 { 3826 3830 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3832 3836 3833 3837 /** @callback_method_impl{FNCPUMRDMSR} */ 3834 static DECLCALLBACK( int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3838 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3835 3839 { 3836 3840 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3843 3847 3844 3848 /** @callback_method_impl{FNCPUMWRMSR} */ 3845 static DECLCALLBACK( int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3849 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3846 3850 { 3847 3851 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3853 3857 3854 3858 /** @callback_method_impl{FNCPUMRDMSR} */ 3855 static DECLCALLBACK( int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3859 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3856 3860 { 3857 3861 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3864 3868 3865 3869 /** @callback_method_impl{FNCPUMWRMSR} */ 3866 static DECLCALLBACK( int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3870 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3867 3871 { 3868 3872 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3874 3878 3875 3879 /** @callback_method_impl{FNCPUMRDMSR} */ 3876 static DECLCALLBACK( int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3880 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3877 3881 { 3878 3882 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3885 3889 3886 3890 /** @callback_method_impl{FNCPUMWRMSR} */ 3887 static DECLCALLBACK( int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3891 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3888 3892 { 3889 3893 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3895 3899 3896 3900 /** @callback_method_impl{FNCPUMRDMSR} */ 3897 static DECLCALLBACK( int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3901 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3898 3902 { 3899 3903 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3906 3910 3907 3911 /** @callback_method_impl{FNCPUMWRMSR} */ 3908 static DECLCALLBACK( int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3912 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3909 3913 { 3910 3914 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3916 3920 3917 3921 /** @callback_method_impl{FNCPUMRDMSR} */ 3918 static DECLCALLBACK( int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3922 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3919 3923 { 3920 3924 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3927 3931 3928 3932 /** @callback_method_impl{FNCPUMWRMSR} */ 3929 static DECLCALLBACK( int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3933 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3930 3934 { 3931 3935 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3937 3941 3938 3942 /** @callback_method_impl{FNCPUMRDMSR} */ 3939 static DECLCALLBACK( int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3943 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3940 3944 { 3941 3945 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3948 3952 3949 3953 /** @callback_method_impl{FNCPUMWRMSR} */ 3950 static DECLCALLBACK( int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3954 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3951 3955 { 3952 3956 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3958 3962 3959 3963 /** @callback_method_impl{FNCPUMRDMSR} */ 3960 static DECLCALLBACK( int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3964 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3961 3965 { 3962 3966 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3969 3973 3970 3974 /** @callback_method_impl{FNCPUMWRMSR} */ 3971 static DECLCALLBACK( int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3975 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3972 3976 { 3973 3977 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3979 3983 3980 3984 /** @callback_method_impl{FNCPUMRDMSR} */ 3981 static DECLCALLBACK( int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)3985 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3982 3986 { 3983 3987 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 3990 3994 3991 3995 /** @callback_method_impl{FNCPUMWRMSR} */ 3992 static DECLCALLBACK( int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)3996 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 3993 3997 { 3994 3998 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 4000 4004 4001 4005 /** @callback_method_impl{FNCPUMRDMSR} */ 4002 static DECLCALLBACK( int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4006 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4003 4007 { 4004 4008 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 4011 4015 4012 4016 /** @callback_method_impl{FNCPUMWRMSR} */ 4013 static DECLCALLBACK( int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4017 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4014 4018 { 4015 4019 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 4021 4025 4022 4026 /** @callback_method_impl{FNCPUMRDMSR} */ 4023 static DECLCALLBACK( int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4027 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4024 4028 { 4025 4029 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 4032 4036 4033 4037 /** @callback_method_impl{FNCPUMWRMSR} */ 4034 static DECLCALLBACK( int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4038 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4035 4039 { 4036 4040 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older … … 4042 4046 4043 4047 /** @callback_method_impl{FNCPUMRDMSR} */ 4044 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4048 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4045 4049 { 4046 4050 /** @todo AMD FPU config. */ … … 4051 4055 4052 4056 /** @callback_method_impl{FNCPUMWRMSR} */ 4053 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4057 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4054 4058 { 4055 4059 /** @todo AMD FPU config. */ … … 4059 4063 4060 4064 /** @callback_method_impl{FNCPUMRDMSR} */ 4061 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4065 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4062 4066 { 4063 4067 /** @todo AMD decoder config. */ … … 4068 4072 4069 4073 /** @callback_method_impl{FNCPUMWRMSR} */ 4070 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4074 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4071 4075 { 4072 4076 /** @todo AMD decoder config. */ … … 4076 4080 4077 4081 /** @callback_method_impl{FNCPUMRDMSR} */ 4078 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4082 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4079 4083 { 4080 4084 /* Note! 10h and 16h */ … … 4086 4090 4087 4091 /** @callback_method_impl{FNCPUMWRMSR} */ 4088 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4092 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4089 4093 { 4090 4094 /* Note! 10h and 16h */ … … 4095 4099 4096 4100 /** @callback_method_impl{FNCPUMRDMSR} */ 4097 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4101 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4098 4102 { 4099 4103 /** @todo AMD unit config. */ … … 4104 4108 4105 4109 /** @callback_method_impl{FNCPUMWRMSR} */ 4106 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4110 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4107 4111 { 4108 4112 /** @todo AMD unit config. */ … … 4112 4116 4113 4117 /** @callback_method_impl{FNCPUMRDMSR} */ 4114 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4118 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4115 4119 { 4116 4120 /** @todo AMD unit config 2. */ … … 4121 4125 4122 4126 /** @callback_method_impl{FNCPUMWRMSR} */ 4123 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4127 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4124 4128 { 4125 4129 /** @todo AMD unit config 2. */ … … 4129 4133 4130 4134 /** @callback_method_impl{FNCPUMRDMSR} */ 4131 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4135 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4132 4136 { 4133 4137 /** @todo AMD combined unit config 3. */ … … 4138 4142 4139 4143 /** @callback_method_impl{FNCPUMWRMSR} */ 4140 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4144 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4141 4145 { 4142 4146 /** @todo AMD combined unit config 3. */ … … 4146 4150 4147 4151 /** @callback_method_impl{FNCPUMRDMSR} */ 4148 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4152 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4149 4153 { 4150 4154 /** @todo AMD execution unit config. */ … … 4155 4159 4156 4160 /** @callback_method_impl{FNCPUMWRMSR} */ 4157 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4161 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4158 4162 { 4159 4163 /** @todo AMD execution unit config. */ … … 4163 4167 4164 4168 /** @callback_method_impl{FNCPUMRDMSR} */ 4165 static DECLCALLBACK( int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4169 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4166 4170 { 4167 4171 /** @todo AMD load-store config 2. */ … … 4172 4176 4173 4177 /** @callback_method_impl{FNCPUMWRMSR} */ 4174 static DECLCALLBACK( int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4178 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4175 4179 { 4176 4180 /** @todo AMD load-store config 2. */ … … 4180 4184 4181 4185 /** @callback_method_impl{FNCPUMRDMSR} */ 4182 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4186 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4183 4187 { 4184 4188 /** @todo AMD IBS. */ … … 4189 4193 4190 4194 /** @callback_method_impl{FNCPUMWRMSR} */ 4191 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4195 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4192 4196 { 4193 4197 /** @todo AMD IBS. */ … … 4197 4201 4198 4202 /** @callback_method_impl{FNCPUMRDMSR} */ 4199 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4203 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4200 4204 { 4201 4205 /** @todo AMD IBS. */ … … 4206 4210 4207 4211 /** @callback_method_impl{FNCPUMWRMSR} */ 4208 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4212 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4209 4213 { 4210 4214 /** @todo AMD IBS. */ … … 4214 4218 4215 4219 /** @callback_method_impl{FNCPUMRDMSR} */ 4216 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4220 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4217 4221 { 4218 4222 /** @todo AMD IBS. */ … … 4223 4227 4224 4228 /** @callback_method_impl{FNCPUMWRMSR} */ 4225 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4229 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4226 4230 { 4227 4231 /** @todo AMD IBS. */ … … 4231 4235 4232 4236 /** @callback_method_impl{FNCPUMRDMSR} */ 4233 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4237 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4234 4238 { 4235 4239 /** @todo AMD IBS. */ … … 4240 4244 4241 4245 /** @callback_method_impl{FNCPUMWRMSR} */ 4242 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4246 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4243 4247 { 4244 4248 /** @todo AMD IBS. */ … … 4248 4252 4249 4253 /** @callback_method_impl{FNCPUMRDMSR} */ 4250 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4254 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4251 4255 { 4252 4256 /** @todo AMD IBS. */ … … 4257 4261 4258 4262 /** @callback_method_impl{FNCPUMWRMSR} */ 4259 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4263 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4260 4264 { 4261 4265 /** @todo AMD IBS. */ … … 4270 4274 4271 4275 /** @callback_method_impl{FNCPUMRDMSR} */ 4272 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4276 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4273 4277 { 4274 4278 /** @todo AMD IBS. */ … … 4279 4283 4280 4284 /** @callback_method_impl{FNCPUMWRMSR} */ 4281 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4285 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4282 4286 { 4283 4287 /** @todo AMD IBS. */ … … 4287 4291 4288 4292 /** @callback_method_impl{FNCPUMRDMSR} */ 4289 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4293 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4290 4294 { 4291 4295 /** @todo AMD IBS. */ … … 4296 4300 4297 4301 /** @callback_method_impl{FNCPUMWRMSR} */ 4298 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4302 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4299 4303 { 4300 4304 /** @todo AMD IBS. */ … … 4304 4308 4305 4309 /** @callback_method_impl{FNCPUMRDMSR} */ 4306 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4310 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4307 4311 { 4308 4312 /** @todo AMD IBS. */ … … 4313 4317 4314 4318 /** @callback_method_impl{FNCPUMWRMSR} */ 4315 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4319 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4316 4320 { 4317 4321 /** @todo AMD IBS. */ … … 4321 4325 4322 4326 /** @callback_method_impl{FNCPUMRDMSR} */ 4323 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4327 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4324 4328 { 4325 4329 /** @todo AMD IBS. */ … … 4330 4334 4331 4335 /** @callback_method_impl{FNCPUMWRMSR} */ 4332 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4336 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4333 4337 { 4334 4338 /** @todo AMD IBS. */ … … 4343 4347 4344 4348 /** @callback_method_impl{FNCPUMRDMSR} */ 4345 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4349 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4346 4350 { 4347 4351 /** @todo AMD IBS. */ … … 4352 4356 4353 4357 /** @callback_method_impl{FNCPUMWRMSR} */ 4354 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4358 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4355 4359 { 4356 4360 /** @todo AMD IBS. */ … … 4360 4364 4361 4365 /** @callback_method_impl{FNCPUMRDMSR} */ 4362 static DECLCALLBACK( int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4366 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4363 4367 { 4364 4368 /** @todo AMD IBS. */ … … 4369 4373 4370 4374 /** @callback_method_impl{FNCPUMWRMSR} */ 4371 static DECLCALLBACK( int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4375 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4372 4376 { 4373 4377 /** @todo AMD IBS. */ … … 4377 4381 4378 4382 /** @callback_method_impl{FNCPUMRDMSR} */ 4379 static DECLCALLBACK( int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4383 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4380 4384 { 4381 4385 /** @todo AMD IBS. */ … … 4386 4390 4387 4391 /** @callback_method_impl{FNCPUMWRMSR} */ 4388 static DECLCALLBACK( int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4392 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4389 4393 { 4390 4394 /** @todo AMD IBS. */ … … 4407 4411 4408 4412 /** @callback_method_impl{FNCPUMRDMSR} */ 4409 static DECLCALLBACK( int) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)4413 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 4410 4414 { 4411 4415 return GIMReadMsr(pVCpu, idMsr, pRange, puValue); … … 4414 4418 4415 4419 /** @callback_method_impl{FNCPUMWRMSR} */ 4416 static DECLCALLBACK( int) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)4420 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 4417 4421 { 4418 4422 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue); … … 4971 4975 * 4972 4976 * @retval VINF_SUCCESS on success. 4977 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the 4978 * current context (raw-mode or ring-0). 4973 4979 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is 4974 4980 * expected to take the appropriate actions. @a *puValue is set to 0. … … 4980 4986 * recompiler. 4981 4987 */ 4982 VMMDECL( int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)4983 { 4984 *puValue = 0; 4985 4986 int rc;4988 VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue) 4989 { 4990 *puValue = 0; 4991 4992 VBOXSTRICTRC rcStrict; 4987 4993 PVM pVM = pVCpu->CTX_SUFF(pVM); 4988 4994 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr); … … 4998 5004 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads); 4999 5005 5000 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue); 5001 if (RT_SUCCESS(rc)) 5002 { 5006 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue); 5007 if (rcStrict == VINF_SUCCESS) 5003 5008 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue)); 5004 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr)); 5005 } 5006 else if (rc == VERR_CPUM_RAISE_GP_0) 5009 else if (rcStrict == VERR_CPUM_RAISE_GP_0) 5007 5010 { 5008 5011 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName)); … … 5010 5013 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp); 5011 5014 } 5015 #ifndef IN_RING3 5016 else if (rcStrict == VINF_CPUM_R3_MSR_READ) 5017 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName)); 5018 #endif 5012 5019 else 5013 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc)); 5020 { 5021 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict))); 5022 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr), 5023 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS); 5024 Assert(rcStrict != VERR_EM_INTERPRETER); 5025 } 5014 5026 } 5015 5027 else … … 5018 5030 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads); 5019 5031 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown); 5020 rc = VERR_CPUM_RAISE_GP_0;5032 rcStrict = VERR_CPUM_RAISE_GP_0; 5021 5033 } 5022 return rc ;5034 return rcStrict; 5023 5035 } 5024 5036 … … 5031 5043 * 5032 5044 * @retval VINF_SUCCESS on success. 5045 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the 5046 * current context (raw-mode or ring-0). 5033 5047 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the 5034 5048 * appropriate actions. … … 5046 5060 * this. 5047 5061 */ 5048 VMMDECL( int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)5049 { 5050 int rc;5062 VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue) 5063 { 5064 VBOXSTRICTRC rcStrict; 5051 5065 PVM pVM = pVCpu->CTX_SUFF(pVM); 5052 5066 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr); … … 5071 5085 } 5072 5086 5073 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue); 5074 if (RT_SUCCESS(rc)) 5075 { 5087 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue); 5088 if (rcStrict == VINF_SUCCESS) 5076 5089 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue)); 5077 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr)); 5078 } 5079 else if (rc == VERR_CPUM_RAISE_GP_0) 5090 else if (rcStrict == VERR_CPUM_RAISE_GP_0) 5080 5091 { 5081 5092 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue)); … … 5083 5094 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp); 5084 5095 } 5096 #ifndef IN_RING3 5097 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE) 5098 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue)); 5099 #endif 5085 5100 else 5086 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc)); 5101 { 5102 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n", 5103 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict))); 5104 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr), 5105 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS); 5106 Assert(rcStrict != VERR_EM_INTERPRETER); 5107 } 5087 5108 } 5088 5109 else … … 5092 5113 STAM_COUNTER_INC(&pRange->cGps); 5093 5114 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp); 5094 rc = VERR_CPUM_RAISE_GP_0;5115 rcStrict = VERR_CPUM_RAISE_GP_0; 5095 5116 } 5096 5117 } … … 5100 5121 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites); 5101 5122 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown); 5102 rc = VERR_CPUM_RAISE_GP_0;5123 rcStrict = VERR_CPUM_RAISE_GP_0; 5103 5124 } 5104 return rc ;5125 return rcStrict; 5105 5126 } 5106 5127 -
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r53101 r53466 1292 1292 #endif 1293 1293 /* Low dword of the TSC_AUX msr only. */ 1294 CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx);1294 VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS); 1295 1295 pCtx->rcx &= UINT32_C(0xffffffff); 1296 1296 … … 1746 1746 1747 1747 uint64_t uValue; 1748 int rc= CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);1749 if (RT_UNLIKELY(rc != VINF_SUCCESS))1750 { 1751 Assert(rc == VERR_CPUM_RAISE_GP_0 || rc == VERR_EM_INTERPRETER);1752 Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));1748 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue); 1749 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS)) 1750 { 1751 Log4(("EM: Refuse RDMSR: rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 1752 Assert(rcStrict == VERR_CPUM_RAISE_GP_0 || rcStrict == VERR_EM_INTERPRETER || rcStrict == VINF_CPUM_R3_MSR_READ); 1753 1753 return VERR_EM_INTERPRETER; 1754 1754 } … … 1756 1756 pRegFrame->rdx = (uint32_t)(uValue >> 32); 1757 1757 LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue)); 1758 return rc;1758 return VINF_SUCCESS; 1759 1759 } 1760 1760 … … 1779 1779 } 1780 1780 1781 int rc= CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));1782 if (rc != VINF_SUCCESS)1783 { 1784 Assert(rc == VERR_CPUM_RAISE_GP_0 || rc == VERR_EM_INTERPRETER);1785 Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", rc));1781 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)); 1782 if (rcStrict != VINF_SUCCESS) 1783 { 1784 Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 1785 Assert(rcStrict == VERR_CPUM_RAISE_GP_0 || rcStrict == VERR_EM_INTERPRETER || rcStrict == VINF_CPUM_R3_MSR_WRITE); 1786 1786 return VERR_EM_INTERPRETER; 1787 1787 } … … 1789 1789 RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx))); 1790 1790 NOREF(pVM); 1791 return rc;1791 return VINF_SUCCESS; 1792 1792 } 1793 1793 -
trunk/src/VBox/VMM/VMMAll/GIMAll.cpp
r52768 r53466 133 133 * Invokes the read-MSR handler for the GIM provider configured for the VM. 134 134 * 135 * @returns VBox status code. 135 * @returns Strict VBox status code like CPUMQueryGuestMsr. 136 * @retval VINF_CPUM_R3_MSR_READ 137 * @retval VERR_CPUM_RAISE_GP_0 138 * 136 139 * @param pVCpu Pointer to the VMCPU. 137 140 * @param idMsr The MSR to read. … … 139 142 * @param puValue Where to store the MSR value read. 140 143 */ 141 VMM_INT_DECL( int) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)144 VMM_INT_DECL(VBOXSTRICTRC) GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 142 145 { 143 146 Assert(pVCpu); … … 161 164 * Invokes the write-MSR handler for the GIM provider configured for the VM. 162 165 * 163 * @returns VBox status code. 166 * @returns Strict VBox status code like CPUMSetGuestMsr. 167 * @retval VINF_CPUM_R3_MSR_WRITE 168 * @retval VERR_CPUM_RAISE_GP_0 169 * 164 170 * @param pVCpu Pointer to the VMCPU. 165 171 * @param idMsr The MSR to write. … … 168 174 * @param uRawValue The raw value with the ignored bits not masked. 169 175 */ 170 VMM_INT_DECL( int) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)176 VMM_INT_DECL(VBOXSTRICTRC) GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 171 177 { 172 178 AssertPtr(pVCpu); -
trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp
r52671 r53466 82 82 * MSR read handler for Hyper-V. 83 83 * 84 * @returns VBox status code. 84 * @returns Strict VBox status code like CPUMQueryGuestMsr. 85 * @retval VINF_CPUM_R3_MSR_READ 86 * @retval VERR_CPUM_RAISE_GP_0 87 * 85 88 * @param pVCpu Pointer to the VMCPU. 86 89 * @param idMsr The MSR being read. … … 88 91 * @param puValue Where to store the MSR value read. 89 92 */ 90 VMM_INT_DECL( int) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)93 VMM_INT_DECL(VBOXSTRICTRC) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 91 94 { 92 95 NOREF(pRange); … … 167 170 * MSR write handler for Hyper-V. 168 171 * 169 * @returns VBox status code. 172 * @returns Strict VBox status code like CPUMSetGuestMsr. 173 * @retval VINF_CPUM_R3_MSR_WRITE 174 * @retval VERR_CPUM_RAISE_GP_0 175 * 170 176 * @param pVCpu Pointer to the VMCPU. 171 177 * @param idMsr The MSR being written. … … 173 179 * @param uRawValue The raw value with the ignored bits not masked. 174 180 */ 175 VMM_INT_DECL( int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)181 VMM_INT_DECL(VBOXSTRICTRC) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue) 176 182 { 177 183 NOREF(pRange); … … 196 202 { 197 203 #ifndef IN_RING3 198 return V ERR_EM_INTERPRETER;204 return VINF_CPUM_R3_MSR_WRITE; 199 205 #else 200 206 /* Disable the hypercall-page if 0 is written to this MSR. */ … … 206 212 pHv->u64GuestOsIdMsr = uRawValue; 207 213 return VINF_SUCCESS; 208 #endif /* !IN_RING3 */214 #endif /* IN_RING3 */ 209 215 } 210 216 … … 212 218 { 213 219 #ifndef IN_RING3 214 return V ERR_EM_INTERPRETER;215 #else 220 return VINF_CPUM_R3_MSR_WRITE; 221 #else /* IN_RING3 */ 216 222 /* First, update all but the hypercall enable bit. */ 217 223 pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_ENABLE_BIT); … … 243 249 244 250 return VERR_CPUM_RAISE_GP_0; 245 #endif /* !IN_RING3 */251 #endif /* IN_RING3 */ 246 252 } 247 253 … … 249 255 { 250 256 #ifndef IN_RING3 251 return V ERR_EM_INTERPRETER;252 #else 257 return VINF_CPUM_R3_MSR_WRITE; 258 #else /* IN_RING3 */ 253 259 /* First, update all but the TSC-page enable bit. */ 254 260 pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT); … … 273 279 274 280 return VERR_CPUM_RAISE_GP_0; 275 #endif /* !IN_RING3 */281 #endif /* IN_RING3 */ 276 282 } 277 283 … … 279 285 { 280 286 #ifndef IN_RING3 281 return V ERR_EM_INTERPRETER;287 return VINF_CPUM_R3_MSR_WRITE; 282 288 #else 283 289 if (MSR_GIM_HV_RESET_IS_SET(uRawValue)) … … 289 295 /* else: Ignore writes to other bits. */ 290 296 return VINF_SUCCESS; 291 #endif /* !IN_RING3 */297 #endif /* IN_RING3 */ 292 298 } 293 299 -
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r53188 r53466 10158 10158 || rc == VINF_IOM_R3_MMIO_READ_WRITE 10159 10159 || rc == VINF_IOM_R3_MMIO_WRITE 10160 || rc == VINF_CPUM_R3_MSR_READ 10161 || rc == VINF_CPUM_R3_MSR_WRITE 10160 10162 || rc == VINF_EM_RESCHEDULE 10161 10163 ) … … 10561 10563 || rcStrict == VINF_IOM_R3_MMIO_READ_WRITE 10562 10564 || rcStrict == VINF_IOM_R3_MMIO_WRITE 10565 || rcStrict == VINF_CPUM_R3_MSR_READ 10566 || rcStrict == VINF_CPUM_R3_MSR_WRITE 10563 10567 , ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 10564 10568 int32_t const rcPassUp = pIemCpu->rcPassUp; -
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
r53181 r53466 5379 5379 */ 5380 5380 RTUINT64U uValue; 5381 int rc = CPUMQueryGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, &uValue.u); 5382 if (rc != VINF_SUCCESS) 5383 { 5384 #ifdef IN_RING3 5385 static uint32_t s_cTimes = 0; 5386 if (s_cTimes++ < 10) 5387 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pCtx->ecx)); 5381 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, &uValue.u); 5382 if (rcStrict == VINF_SUCCESS) 5383 { 5384 pCtx->rax = uValue.s.Lo; 5385 pCtx->rdx = uValue.s.Hi; 5386 5387 iemRegAddToRipAndClearRF(pIemCpu, cbInstr); 5388 return VINF_SUCCESS; 5389 } 5390 5391 #ifndef IN_RING3 5392 /* Deferred to ring-3. */ 5393 if (rcStrict == VINF_CPUM_R3_MSR_READ) 5394 { 5395 Log(("IEM: rdmsr(%#x) -> ring-3\n", pCtx->ecx)); 5396 return rcStrict; 5397 } 5398 #else /* IN_RING3 */ 5399 /* Often a unimplemented MSR or MSR bit, so worth logging. */ 5400 static uint32_t s_cTimes = 0; 5401 if (s_cTimes++ < 10) 5402 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pCtx->ecx)); 5403 else 5388 5404 #endif 5389 5405 Log(("IEM: rdmsr(%#x) -> #GP(0)\n", pCtx->ecx)); 5390 AssertMsgReturn(rc == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_STATUS); 5391 return iemRaiseGeneralProtectionFault0(pIemCpu); 5392 } 5393 5394 pCtx->rax = uValue.s.Lo; 5395 pCtx->rdx = uValue.s.Hi; 5396 5397 iemRegAddToRipAndClearRF(pIemCpu, cbInstr); 5398 return VINF_SUCCESS; 5406 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS); 5407 return iemRaiseGeneralProtectionFault0(pIemCpu); 5399 5408 } 5400 5409 … … 5422 5431 uValue.s.Hi = pCtx->edx; 5423 5432 5424 int rc;5433 VBOXSTRICTRC rcStrict; 5425 5434 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 5426 rc = CPUMSetGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, uValue.u);5435 rcStrict = CPUMSetGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, uValue.u); 5427 5436 else 5428 5437 { 5429 5438 CPUMCTX CtxTmp = *pCtx; 5430 rc = CPUMSetGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, uValue.u);5439 rcStrict = CPUMSetGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, uValue.u); 5431 5440 PCPUMCTX pCtx2 = CPUMQueryGuestCtxPtr(IEMCPU_TO_VMCPU(pIemCpu)); 5432 5441 *pCtx = *pCtx2; 5433 5442 *pCtx2 = CtxTmp; 5434 5443 } 5435 if (rc != VINF_SUCCESS) 5436 { 5437 #ifdef IN_RING3 5438 static uint32_t s_cTimes = 0; 5439 if (s_cTimes++ < 10) 5440 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pCtx->ecx, uValue.s.Hi, uValue.s.Lo)); 5444 if (rcStrict == VINF_SUCCESS) 5445 { 5446 iemRegAddToRipAndClearRF(pIemCpu, cbInstr); 5447 return VINF_SUCCESS; 5448 } 5449 5450 #ifndef IN_RING3 5451 /* Deferred to ring-3. */ 5452 if (rcStrict == VINF_CPUM_R3_MSR_WRITE) 5453 { 5454 Log(("IEM: rdmsr(%#x) -> ring-3\n", pCtx->ecx)); 5455 return rcStrict; 5456 } 5457 #else /* IN_RING3 */ 5458 /* Often a unimplemented MSR or MSR bit, so worth logging. */ 5459 static uint32_t s_cTimes = 0; 5460 if (s_cTimes++ < 10) 5461 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pCtx->ecx, uValue.s.Hi, uValue.s.Lo)); 5462 else 5441 5463 #endif 5442 5464 Log(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pCtx->ecx, uValue.s.Hi, uValue.s.Lo)); 5443 AssertMsgReturn(rc == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_STATUS); 5444 return iemRaiseGeneralProtectionFault0(pIemCpu); 5445 } 5446 5447 iemRegAddToRipAndClearRF(pIemCpu, cbInstr); 5448 return VINF_SUCCESS; 5465 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS); 5466 return iemRaiseGeneralProtectionFault0(pIemCpu); 5449 5467 } 5450 5468 -
trunk/src/VBox/VMM/VMMR0/VMMR0.cpp
r51643 r53466 656 656 case VINF_PATM_HC_MMIO_PATCH_WRITE: 657 657 STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetMMIOPatchWrite); 658 break; 659 case VINF_CPUM_R3_MSR_READ: 660 STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetMSRRead); 661 break; 662 case VINF_CPUM_R3_MSR_WRITE: 663 STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetMSRWrite); 658 664 break; 659 665 case VINF_EM_RAW_EMULATE_INSTR: -
trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp
r45793 r53466 423 423 424 424 uint64_t u64Value; 425 int rc= CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);426 if ( RT_SUCCESS(rc))425 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value); 426 if (rcStrict == VINF_SUCCESS) 427 427 { 428 428 switch (pDesc->enmType) … … 436 436 } 437 437 /** @todo what to do about errors? */ 438 return rc; 438 Assert(RT_FAILURE_NP(rcStrict)); 439 return VBOXSTRICTRC_VAL(rcStrict); 439 440 } 440 441 … … 445 446 static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 446 447 { 447 int rc; 448 PVMCPU pVCpu = (PVMCPU)pvUser; 448 PVMCPU pVCpu = (PVMCPU)pvUser; 449 449 450 450 VMCPU_ASSERT_EMT(pVCpu); … … 479 479 { 480 480 uint64_t u64FullValue; 481 rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue); 482 if (RT_FAILURE(rc)) 483 return rc; 481 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue); 482 if (rcStrict != VINF_SUCCESS) 483 { 484 AssertRC(RT_FAILURE_NP(rcStrict)); 485 return VBOXSTRICTRC_VAL(rcStrict); 486 } 484 487 u64Value = (u64FullValue & ~fMask) 485 488 | (u64Value & fMask); … … 489 492 * Perform the assignment. 490 493 */ 491 return CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value); 494 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value); 495 if (rcStrict == VINF_SUCCESS) 496 return VINF_SUCCESS; 497 AssertRC(RT_FAILURE_NP(rcStrict)); 498 return VBOXSTRICTRC_VAL(rcStrict); 492 499 } 493 500 -
trunk/src/VBox/VMM/VMMR3/VMM.cpp
r53300 r53466 426 426 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns."); 427 427 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns."); 428 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMSRRead, STAMTYPE_COUNTER, "/VMM/RZRet/MSRRead", STAMUNIT_OCCURENCES, "Number of VINF_CPUM_R3_MSR_READ returns."); 429 STAM_REG(pVM, &pVM->vmm.s.StatRZRetMSRWrite, STAMTYPE_COUNTER, "/VMM/RZRet/MSRWrite", STAMUNIT_OCCURENCES, "Number of VINF_CPUM_R3_MSR_WRITE returns."); 428 430 STAM_REG(pVM, &pVM->vmm.s.StatRZRetLDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns."); 429 431 STAM_REG(pVM, &pVM->vmm.s.StatRZRetGDTFault, STAMTYPE_COUNTER, "/VMM/RZRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns."); -
trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
r49141 r53466 1204 1204 case VINF_IOM_R3_MMIO_READ: 1205 1205 case VINF_IOM_R3_MMIO_READ_WRITE: 1206 case VINF_CPUM_R3_MSR_READ: 1207 case VINF_CPUM_R3_MSR_WRITE: 1206 1208 case VINF_PATM_PATCH_INT3: 1207 1209 case VINF_EM_NO_MEMORY: -
trunk/src/VBox/VMM/include/EMHandleRCTmpl.h
r52660 r53466 224 224 break; 225 225 226 /* 227 * Machine specific register access - emulate the instruction. 228 */ 229 case VINF_CPUM_R3_MSR_READ: 230 case VINF_CPUM_R3_MSR_WRITE: 231 rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR"); 232 break; 233 226 234 #ifdef EMHANDLERC_WITH_HM 227 235 /* -
trunk/src/VBox/VMM/include/GIMHvInternal.h
r52763 r53466 495 495 RT_C_DECLS_BEGIN 496 496 497 /** @todo r=bird: Internal header, internal prefix: s/GIM\(R.|\)Hv/gim\1Hv/g */ 498 497 499 #ifdef IN_RING0 498 500 VMMR0_INT_DECL(int) GIMR0HvInitVM(PVM pVM); … … 520 522 VMM_INT_DECL(bool) GIMHvAreHypercallsEnabled(PVMCPU pVCpu); 521 523 VMM_INT_DECL(int) GIMHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx); 522 VMM_INT_DECL( int)GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);523 VMM_INT_DECL( int)GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);524 VMM_INT_DECL(VBOXSTRICTRC) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 525 VMM_INT_DECL(VBOXSTRICTRC) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue); 524 526 525 527 RT_C_DECLS_END -
trunk/src/VBox/VMM/include/VMMInternal.h
r49141 r53466 344 344 STAMCOUNTER StatRZRetMMIOPatchWrite; 345 345 STAMCOUNTER StatRZRetMMIOReadWrite; 346 STAMCOUNTER StatRZRetMSRRead; 347 STAMCOUNTER StatRZRetMSRWrite; 346 348 STAMCOUNTER StatRZRetLDTFault; 347 349 STAMCOUNTER StatRZRetGDTFault; -
trunk/src/recompiler/VBoxRecompiler.c
r52066 r53466 4514 4514 { 4515 4515 uint64_t u64; 4516 int rc= CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64);4517 if (RT_SUCCESS(rc ))4516 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64); 4517 if (RT_SUCCESS(rcStrict)) 4518 4518 { 4519 4519 LogFlow(("cpu_get_apic_base: returns %#llx \n", u64)); 4520 4520 return u64; 4521 4521 } 4522 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", rc));4522 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict))); 4523 4523 return 0; 4524 4524 }
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