Changeset 54072 in vbox
- Timestamp:
- Feb 3, 2015 4:25:44 PM (10 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/USB/DevOHCI.cpp
r53911 r54072 119 119 120 120 121 /** Number of Downstream Ports on the root hub. 121 /** Maximum supported number of Downstream Ports on the root hub. 15 ports 122 * is the maximum defined by the OHCI spec. 122 123 * If you change this you need to add more status register words to the 'opreg' 123 124 * array. 124 125 */ 125 #define OHCI_NDP 15 126 #define OHCI_NDP_MAX 15 127 128 /** Default NDP, chosen to be compatible with everything. */ 129 #define OHCI_NDP_DEFAULT 12 130 131 /* Macro to query the number of currently configured ports. */ 132 #define OHCI_NDP_CFG(pohci) ((pohci)->RootHub.desc_a & OHCI_RHA_NDP) 126 133 127 134 /** Pointer to OHCI device data. */ … … 183 190 uint32_t Alignment0; /**< Align aPorts on a 8 byte boundary. */ 184 191 #endif 185 OHCIHUBPORT aPorts[OHCI_NDP ];192 OHCIHUBPORT aPorts[OHCI_NDP_MAX]; 186 193 R3PTRTYPE(POHCI) pOhci; 187 194 } OHCIROOTHUB; … … 204 211 unsigned cDevs; 205 212 /** Array of devices which were detached. */ 206 PVUSBIDEVICE apDevs[OHCI_NDP ];213 PVUSBIDEVICE apDevs[OHCI_NDP_MAX]; 207 214 } OHCILOAD; 208 215 /** Pointer to an OHCILOAD structure. */ … … 921 928 922 929 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED); 923 for (iPort = 0; iPort < RT_ELEMENTS(pThis->RootHub.aPorts); iPort++)930 for (iPort = 0; iPort < OHCI_NDP_CFG(pThis); iPort++) 924 931 { 925 932 if (!pThis->RootHub.aPorts[iPort].pDev) … … 963 970 * Validate and adjust input. 964 971 */ 965 Assert(uPort >= 1 && uPort <= RT_ELEMENTS(pThis->RootHub.aPorts));972 Assert(uPort >= 1 && uPort <= OHCI_NDP_CFG(pThis)); 966 973 uPort--; 967 974 Assert(!pThis->RootHub.aPorts[uPort].pDev); … … 1000 1007 * Validate and adjust input. 1001 1008 */ 1002 Assert(uPort >= 1 && uPort <= RT_ELEMENTS(pThis->RootHub.aPorts));1009 Assert(uPort >= 1 && uPort <= OHCI_NDP_CFG(pThis)); 1003 1010 uPort--; 1004 1011 Assert(pThis->RootHub.aPorts[uPort].pDev == pDev); … … 1057 1064 1058 1065 pThis->RootHub.status = 0; 1059 pThis->RootHub.desc_a = OHCI_RHA_NPS | OHCI_NDP ;1066 pThis->RootHub.desc_a = OHCI_RHA_NPS | OHCI_NDP_CFG(pThis); /* Preserve NDP value. */ 1060 1067 pThis->RootHub.desc_b = 0x0; /* Impl. specific */ 1061 1068 … … 1072 1079 * into this. For the time being we stick with simple. 1073 1080 */ 1074 for (unsigned iPort = 0; iPort < RT_ELEMENTS(pThis->RootHub.aPorts); iPort++)1081 for (unsigned iPort = 0; iPort < OHCI_NDP_CFG(pThis); iPort++) 1075 1082 { 1076 1083 if (pThis->RootHub.aPorts[iPort].pDev) … … 4633 4640 Log2(("HcRhDescriptorA_w(%#010x) => %sNDP=%d %sPSM=%d %sNPS=%d %sDT=%d %sOCPM=%d %sNOCP=%d %sPOTGT=%#x - %sPowerSwitching Set%sPower\n", 4634 4641 val, 4635 chg & 0xff ?"!!!": "", OHCI_NDP,4642 chg & 0xff ?"!!!": "", val & 0xff, 4636 4643 (chg >> 8) & 1 ? "*" : "", (val >> 8) & 1, 4637 4644 (chg >> 9) & 1 ? "*" : "", (val >> 9) & 1, … … 4646 4653 4647 4654 4648 if ((val & (OHCI_RHA_NDP | OHCI_RHA_DT)) != OHCI_NDP )4655 if ((val & (OHCI_RHA_NDP | OHCI_RHA_DT)) != OHCI_NDP_CFG(pThis)) 4649 4656 { 4650 4657 Log(("ohci: %s: invalid write to NDP or DT in roothub descriptor A!!! val=0x%.8x\n", 4651 4658 pThis->PciDev.name, val)); 4652 4659 val &= ~(OHCI_RHA_NDP | OHCI_RHA_DT); 4653 val |= OHCI_NDP ;4660 val |= OHCI_NDP_CFG(pThis); 4654 4661 } 4655 4662 … … 4726 4733 if ( val & OHCI_RHS_LPSC ) 4727 4734 { 4728 inti;4735 unsigned i; 4729 4736 Log2(("ohci: %s: global power up\n", pThis->PciDev.name)); 4730 for (i = 0; i < OHCI_NDP ; i++)4737 for (i = 0; i < OHCI_NDP_CFG(pThis); i++) 4731 4738 rhport_power(&pThis->RootHub, i, true /* power up */); 4732 4739 } … … 4735 4742 if ( val & OHCI_RHS_LPS ) 4736 4743 { 4737 inti;4744 unsigned i; 4738 4745 Log2(("ohci: %s: global power down\n", pThis->PciDev.name)); 4739 for (i = 0; i < OHCI_NDP ; i++)4746 for (i = 0; i < OHCI_NDP_CFG(pThis); i++) 4740 4747 rhport_power(&pThis->RootHub, i, false /* power down */); 4741 4748 } … … 4800 4807 POHCIHUBPORT pPort = NULL; 4801 4808 unsigned iPort; 4802 for (iPort = 0; iPort < RT_ELEMENTS(pThis->RootHub.aPorts); iPort++) /* lazy bird */4809 for (iPort = 0; iPort < OHCI_NDP_CFG(pThis); iPort++) /* lazy bird */ 4803 4810 if (pThis->RootHub.aPorts[iPort].pDev == pDev) 4804 4811 { … … 5021 5028 5022 5029 /* The number of port status register depends on the definition 5023 * of OHCI_NDP macro5030 * of OHCI_NDP_MAX macro 5024 5031 */ 5025 5032 { "HcRhPortStatus[0]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 21 */ … … 5040 5047 }; 5041 5048 5049 /* Quick way to determine how many op regs are valid. Since at least one port must 5050 * be configured (and no more than 15), there will be between 22 and 36 registers. 5051 */ 5052 #define NUM_OP_REGS(pohci) (21 + OHCI_NDP_CFG(pohci)) 5053 5054 AssertCompile(RT_ELEMENTS(g_aOpRegs) > 21); 5055 AssertCompile(RT_ELEMENTS(g_aOpRegs) <= 36); 5042 5056 5043 5057 /** … … 5057 5071 int rc; 5058 5072 const uint32_t iReg = (GCPhysAddr - pThis->MMIOBase) >> 2; 5059 if (iReg < RT_ELEMENTS(g_aOpRegs))5073 if (iReg < NUM_OP_REGS(pThis)) 5060 5074 { 5061 5075 const OHCIOPREG *pReg = &g_aOpRegs[iReg]; … … 5064 5078 else 5065 5079 { 5066 Log(("ohci: Trying to read register %u/%u!!!\n", iReg, RT_ELEMENTS(g_aOpRegs)));5080 Log(("ohci: Trying to read register %u/%u!!!\n", iReg, NUM_OP_REGS(pThis))); 5067 5081 rc = VINF_IOM_MMIO_UNUSED_FF; 5068 5082 } … … 5087 5101 int rc; 5088 5102 const uint32_t iReg = (GCPhysAddr - pThis->MMIOBase) >> 2; 5089 if (iReg < RT_ELEMENTS(g_aOpRegs))5103 if (iReg < NUM_OP_REGS(pThis)) 5090 5104 { 5091 5105 const OHCIOPREG *pReg = &g_aOpRegs[iReg]; … … 5094 5108 else 5095 5109 { 5096 Log(("ohci: Trying to write to register %u/%u!!!\n", iReg, RT_ELEMENTS(g_aOpRegs)));5110 Log(("ohci: Trying to write to register %u/%u!!!\n", iReg, NUM_OP_REGS(pThis))); 5097 5111 rc = VINF_SUCCESS; 5098 5112 } … … 5703 5717 static DECLCALLBACK(int) ohciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 5704 5718 { 5705 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI); 5719 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI); 5720 uint32_t cPorts; 5706 5721 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 5707 5722 … … 5740 5755 5741 5756 /* 5742 * Read configuration. No configuration keys are currently supported.5757 * Read configuration. 5743 5758 */ 5744 5759 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RZEnabled", ""); … … 5746 5761 AssertLogRelRCReturn(rc, rc); 5747 5762 5763 /* Number of ports option. */ 5764 rc = CFGMR3QueryU32Def(pCfg, "Ports", &cPorts, OHCI_NDP_DEFAULT); 5765 if (RT_FAILURE(rc)) 5766 return PDMDEV_SET_ERROR(pDevIns, rc, 5767 N_("OHCI configuration error: failed to read Ports as integer")); 5768 5769 if (cPorts == 0 || cPorts > OHCI_NDP_MAX) 5770 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS, 5771 N_("OHCI configuration error: Ports must be in range [%u,%u]"), 5772 1, OHCI_NDP_MAX); 5773 5774 /* Store the configured NDP; it will be used everywhere else from now on. */ 5775 pThis->RootHub.desc_a = cPorts; 5748 5776 5749 5777 /* -
trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp
r54061 r54072 992 992 GEN_CHECK_OFF(OHCIROOTHUB, aPorts); 993 993 GEN_CHECK_OFF(OHCIROOTHUB, aPorts[1]); 994 GEN_CHECK_OFF(OHCIROOTHUB, aPorts[OHCI_NDP - 1]);994 GEN_CHECK_OFF(OHCIROOTHUB, aPorts[OHCI_NDP_MAX - 1]); 995 995 GEN_CHECK_OFF(OHCIROOTHUB, pOhci); 996 996
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