Changeset 54256 in vbox

Timestamp:

Feb 17, 2015 11:20:44 PM (10 years ago)

Author:

vboxsync

Message:

VMCPU: Added a iHostCpuSet field to go with the idHostCpu one. This allows for better GIP time & TSC code in raw-mode context.

Location:

trunk

Files:

• include/VBox/vmm/vm.h (modified) (2 diffs)
• include/VBox/vmm/vm.mac (modified) (1 diff)
• src/VBox/VMM/VMMR0/VMMR0.cpp (modified) (6 diffs)

trunk/include/VBox/vmm/vm.h

@@ -117 +117 @@
      * Only valid when in RC or HMR0 with scheduling disabled. */
     RTCPUID volatile        idHostCpu;                              /* 56 / 36 */
+    /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
+     * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
+    uint32_t volatile       iHostCpuSet;                            /* 60 / 40 */
 
     /** Trace groups enable flags.  */
-    uint32_t                fTraceGroups;                           /* 60 / 40 */
+    uint32_t                fTraceGroups;                           /* 64 / 44 */
     /** Align the structures below bit on a 64-byte boundary and make sure it starts
      * at the same offset in both 64-bit and 32-bit builds.
@@ -128 +131 @@
      *          following it (to grow into and align the struct size).
      *   */
-    uint8_t                 abAlignment1[HC_ARCH_BITS == 64 ? 60 : 16+64];
+    uint8_t                 abAlignment1[HC_ARCH_BITS == 64 ? 56 : 12+64];
     /** State data for use by ad hoc profiling. */
     uint32_t                uAdHoc;

trunk/include/VBox/vmm/vm.mac

@@ -123 +123 @@
     .hNativeThreadR0        RTR0PTR_RES 1
     .idHostCpu              resd 1
+    .iHostCpuSet            resd 1
     .fTraceGroups           resd 1
 %if HC_ARCH_BITS == 32
-    .abAlignment1           resb 16+64
+    .abAlignment1           resb 12+64
 %else
-    .abAlignment1           resb 60
+    .abAlignment1           resb 56
 %endif
     .uAdHoc                 resd 1

trunk/src/VBox/VMM/VMMR0/VMMR0.cpp

@@ -566 +566 @@
 
             /* We need to update the VCPU <-> host CPU mapping. */
-            RTCPUID idHostCpu = RTMpCpuId();
+            RTCPUID idHostCpu  = RTMpCpuId();
+            pVCpu->iHostCpuSet = RTMpCpuIdToSetIndex(idHostCpu);
             ASMAtomicWriteU32(&pVCpu->idHostCpu, idHostCpu);
 
@@ -586 +587 @@
              * have the same host CPU associated with it.
              */
+            pVCpu->iHostCpuSet = UINT32_MAX;
             ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
             break;
@@ -867 +869 @@
             CPUMR0SetLApic(pVCpu, idHostCpu);
 #endif
+            pVCpu->iHostCpuSet = RTMpCpuIdToSetIndex(idHostCpu);
             ASMAtomicWriteU32(&pVCpu->idHostCpu, idHostCpu);
             if (pVM->vmm.s.fUsePeriodicPreemptionTimers)
@@ -911 +914 @@
             else
                 pVCpu->vmm.s.iLastGZRc = rc;
+            pVCpu->iHostCpuSet = UINT32_MAX;
             ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
             RTThreadPreemptRestore(&PreemptState);
@@ -926 +930 @@
 
             /* Update the VCPU <-> host CPU mapping before doing anything else. */
-            ASMAtomicWriteU32(&pVCpu->idHostCpu, RTMpCpuId());
+            RTCPUID  idHostCpu = RTMpCpuId();
+            pVCpu->iHostCpuSet = RTMpCpuIdToSetIndex(idHostCpu);
+            ASMAtomicWriteU32(&pVCpu->idHostCpu, idHostCpu);
+
             if (pVM->vmm.s.fUsePeriodicPreemptionTimers)
                 GVMMR0SchedUpdatePeriodicPreemptionTimer(pVM, pVCpu->idHostCpu, TMCalcHostTimerFrequency(pVM, pVCpu));
@@ -1000 +1007 @@
 
             /* Clear the VCPU <-> host CPU mapping as we've left HM context. */
+            pVCpu->iHostCpuSet = UINT32_MAX;
             ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);